From e8d5097ecbe9866e52f425639531786676a9dd24 Mon Sep 17 00:00:00 2001 From: marqs Date: Sun, 7 Oct 2018 23:34:58 +0300 Subject: [PATCH] replace nios crcCI with hw_crc32 qsys module --- ip/hw_crc32_qsys/CRC_Component.v | 314 +++++++++ ip/hw_crc32_qsys/hw_crc32_hw.tcl | 105 +++ software/sys_controller/memory/flash.c | 8 +- software/sys_controller/ossc/firmware.c | 14 +- software/sys_controller/ossc/utils.c | 80 +++ software/sys_controller/ossc/utils.h | 31 + .../sys_controller_bsp/drivers/inc/ci_crc.h | 38 -- software/sys_controller_bsp/drivers/inc/crc.h | 109 --- .../sys_controller_bsp/drivers/src/ci_crc.c | 97 --- software/sys_controller_bsp/drivers/src/crc.c | 265 -------- software/sys_controller_bsp/system.h | 19 +- sys.qsys | 63 +- sys.sopcinfo | 630 +++++++++++++++++- 13 files changed, 1226 insertions(+), 547 deletions(-) create mode 100644 ip/hw_crc32_qsys/CRC_Component.v create mode 100644 ip/hw_crc32_qsys/hw_crc32_hw.tcl create mode 100644 software/sys_controller/ossc/utils.c create mode 100644 software/sys_controller/ossc/utils.h delete mode 100644 software/sys_controller_bsp/drivers/inc/ci_crc.h delete mode 100644 software/sys_controller_bsp/drivers/inc/crc.h delete mode 100644 software/sys_controller_bsp/drivers/src/ci_crc.c delete mode 100644 software/sys_controller_bsp/drivers/src/crc.c diff --git a/ip/hw_crc32_qsys/CRC_Component.v b/ip/hw_crc32_qsys/CRC_Component.v new file mode 100644 index 0000000..5c67836 --- /dev/null +++ b/ip/hw_crc32_qsys/CRC_Component.v @@ -0,0 +1,314 @@ +/* + Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your + use of Altera Corporation's design tools, logic functions and other + software and tools, and its AMPP partner logic functions, and any + output files any of the foregoing (including device programming or + simulation files), and any associated documentation or information are + expressly subject to the terms and conditions of the Altera Program + License Subscription Agreement or other applicable license agreement, + including, without limitation, that your use is for the sole purpose + of programming logic devices manufactured by Altera and sold by Altera + or its authorized distributors. Please refer to the applicable + agreement for further details. +*/ + +/* + This component supports 8, 16, 24, and 32 bit little endian data + and any CRC standard between 1 to 128 bits. Through parameterization + you can change the CRC standard which will take effect after you + regenerate your system in SOPC Builder. + + Register Map: + 000 -> reset the CRC peripheral to the inital value (data and byte enables ignored) + 001 -> data write between 1-32 bits + 010 -> reserved + 011 -> reserved + 100 -> read bits 1-32 of the crc result + 101 -> read bits 33-64 of the crc result (where applicable) + 110 -> read bits 65-96 of the crc result (where applicable) + 111 -> read bits 97-128 of the crc result (where applicable) + + Write latency = 0 + Read latency = 1 + + Note: This component uses four blocks of eight bits of data in cascade. + To improve the timing of logic you can create seperate cascades + for 8, 16, 24, and 32 bit data which will allow for smaller area + and a shorter combinational depth. Since CRC logic consumes power + even when not in use you can also add a logic disable feature using + the chipselect signal. Even though the registered CRC value is + held constant when the circuit is not in use the input data will + change during this time and cause the CRC cascade logic to react. +*/ + + +module CRC_Component (clk, + reset, + address, + writedata, + byteenable, + write, + read, + chipselect, + readdata); + +/* + Using these parameters you can create any CRC ranging from one bit (parity checker) + up to 128 bits. The following list describes the function of each parameter: + + crc_width: + The width of the registered CRC result, this value is typically apart of + the name of the standard (CRC32 is 32 bits wide). Adjusting this value + will impact the logic resource usage. + + polynomial_initial: + The initial value set for the CRC result register. By writing any data to address 0 + this value will be stored in the result register thereby clearing any previously existing + value. This value must be the same width as 'crc_width' + + polynomial: + This is the divisor value used on the input data. Typically shown in polynomial format + the value symbolizes the placement of xor operation on the input data. In synthesis, the + polynomial bits that are '1' will create a not gate, whereas the bits that are '0' will + simply create a wire. Even with 32 stages of these operations cascaded, the simple logic + will not become a significant factor on logic utilization or fmax. This value must be the + same width as 'crc_width' + + reflected_input: + Some CRC standards require that all the input bits be reflected around the center point. + This option is enabled with '1' and disabled with '0'. Typically this option is enabled + or disabled with 'reflected_output'. + + reflected_output: + Some CRC standards require that all the output bits be reflected around the center point. + This operation occurs before the final optional xor output step. This option is enabled + with '1' and disabled with '0'. Typically this option is enabled or disabled with + 'reflected_input' (to undo the input reversal typically). + + xor_output: + This is the value used to bitwise xor the CRC result. Most standards use either all zeros + or all ones for this value. When zeros are used the CRC result is passed directly and when + ones are used the CRC result is inverted. Since it's no mandatory that this value be all + ones or zeros, this operation occurs before the output reflection when applicable. +*/ + + parameter crc_width = 32; + parameter polynomial_inital = 32'hFFFFFFFF; + parameter polynomial = 32'h04C11DB7; + parameter reflected_input = 1; + parameter reflected_output = 1; + parameter xor_output = 32'hFFFFFFFF; + + + input clk; + input reset; + input [2:0] address; + input [31:0] writedata; + input [3:0] byteenable; + input write; + input read; + input chipselect; + output [31:0] readdata; + + reg [crc_width-1:0] crc_value; + wire [crc_width-1:0] poly = polynomial; + wire [crc_width-1:0] cascade [3:0]; + wire [7:0] block0_data, block1_data, block2_data, block3_data; + wire [crc_width-1:0] result, result_xored; + wire [31:0] mux_result; + reg [31:0] readdata; + + + /* + Some standards like CRC16 and CRC32 require this bitreversal for serial + devices like ethernet, uarts, usb, etc... + */ + genvar index; + generate if (reflected_input == 1) + begin + for(index = 0; index < 8; index = index + 1) + begin: input_reflection + assign block0_data[index] = writedata[7-index]; + assign block1_data[index] = writedata[15-index]; + assign block2_data[index] = writedata[23-index]; + assign block3_data[index] = writedata[31-index]; + end + end + else + begin + assign block0_data = writedata[7:0]; + assign block1_data = writedata[15:8]; + assign block2_data = writedata[23:16]; + assign block3_data = writedata[31:24]; + end + endgenerate + + + /* + Control for the registered events. It assumes that either 8, 16, 24, or 32 + bit data is being written using byte enables. It is important that the data + be in little endian format and no gaps of byte enables be present (like + 1011 or 1101 for example) + */ + always @ (posedge clk or posedge reset) + begin + if(reset == 1) + begin + crc_value <= 0; + end + else + begin + if(write && chipselect && (address == 3'b000)) + begin + crc_value <= polynomial_inital; // reset the crc to the initial value + end + else if(write && chipselect && (address == 3'b001)) + begin + if(byteenable == 4'b0001) // 8 bit data input + begin + crc_value <= cascade[0]; + end + else if(byteenable == 4'b0011) // 16 bit data input + begin + crc_value <= cascade[1]; + end + else if(byteenable == 4'b0111) // 24 bit data input + begin + crc_value <= cascade[2]; + end + else if(byteenable == 4'b1111) // 32 bit data input + begin + crc_value <= cascade[3]; + end + end + end + end + + + /* four stages of cascade blocks (each block is crc_width x 8 bits) */ + XOR_Shift_Block cascade_block0(.block_input(crc_value), .poly(poly), .data_input(block0_data), .block_output(cascade[0])); + defparam cascade_block0.crc_width = crc_width; + XOR_Shift_Block cascade_block1(.block_input(cascade[0]), .poly(poly), .data_input(block1_data), .block_output(cascade[1])); + defparam cascade_block1.crc_width = crc_width; + XOR_Shift_Block cascade_block2(.block_input(cascade[1]), .poly(poly), .data_input(block2_data), .block_output(cascade[2])); + defparam cascade_block2.crc_width = crc_width; + XOR_Shift_Block cascade_block3(.block_input(cascade[2]), .poly(poly), .data_input(block3_data), .block_output(cascade[3])); + defparam cascade_block3.crc_width = crc_width; + + + + /* + Some standards like CRC16 and CRC32 require this bitreversal. + This is to better support serial devices like uarts, ethernet, usb, etc...) + */ + generate if (reflected_output == 1) + begin + for(index = 0; index < crc_width; index = index + 1) + begin: output_reflection32 + assign result[index] = crc_value[(crc_width-1)-index]; + end + end + else + begin + assign result = crc_value; + end + endgenerate + + + /* This final xor operation occurs after the bit swap */ + assign result_xored = result ^ xor_output; + + + /* Generates the appropriate MUX logic depending on the CRC width */ + generate if((crc_width > 32) && (crc_width < 65)) + begin + assign mux_result = (address == 3'b100)? result_xored[31:0] : result_xored[crc_width-1:32]; + end + else if((crc_width > 64) && (crc_width < 97)) + begin + assign mux_result = (address == 3'b100)? result_xored[31:0] : + ((address == 3'b101)? result_xored[63:32] : result_xored[crc_width-1:64]); + end + else if((crc_width > 96) && (crc_width < 129)) + begin + assign mux_result = (address == 3'b100)? result_xored[31:0] : + ((address == 3'b101)? result_xored[63:32] : + ((address == 3'b110)? result_xored[95:64] : result_xored[crc_width-1:96])); + end + else + begin + assign mux_result = result_xored; + end + endgenerate + + + /* Registering the return path of the CRC data (32 bits of it) */ + always @ (posedge clk or posedge reset) + begin + if(reset == 1) + begin + readdata <= 0; + end + else if((read == 1) && (chipselect == 1)) + begin + readdata <= mux_result; + end + end + +endmodule + + + +/* a single cascade block of width: crc_width and a length of eight input bits */ +module XOR_Shift_Block(block_input, + poly, + data_input, + block_output); + parameter crc_width = 32; + + input [(crc_width-1):0] block_input; + input [(crc_width-1):0] poly; + input [7:0] data_input; + output [(crc_width-1):0] block_output; + + wire [(crc_width-1):0] cascade [7:0]; + + XOR_Shift bit_0(.stage_input(block_input), .poly(poly), .new_bit(data_input[7]), .stage_output(cascade[0])); + defparam bit_0.crc_width = crc_width; + XOR_Shift bit_1(.stage_input(cascade[0]), .poly(poly), .new_bit(data_input[6]), .stage_output(cascade[1])); + defparam bit_1.crc_width = crc_width; + XOR_Shift bit_2(.stage_input(cascade[1]), .poly(poly), .new_bit(data_input[5]), .stage_output(cascade[2])); + defparam bit_2.crc_width = crc_width; + XOR_Shift bit_3(.stage_input(cascade[2]), .poly(poly), .new_bit(data_input[4]), .stage_output(cascade[3])); + defparam bit_3.crc_width = crc_width; + XOR_Shift bit_4(.stage_input(cascade[3]), .poly(poly), .new_bit(data_input[3]), .stage_output(cascade[4])); + defparam bit_4.crc_width = crc_width; + XOR_Shift bit_5(.stage_input(cascade[4]), .poly(poly), .new_bit(data_input[2]), .stage_output(cascade[5])); + defparam bit_5.crc_width = crc_width; + XOR_Shift bit_6(.stage_input(cascade[5]), .poly(poly), .new_bit(data_input[1]), .stage_output(cascade[6])); + defparam bit_6.crc_width = crc_width; + XOR_Shift bit_7(.stage_input(cascade[6]), .poly(poly), .new_bit(data_input[0]), .stage_output(cascade[7])); + defparam bit_7.crc_width = crc_width; + + assign block_output = cascade[7]; + +endmodule + + +/* performs the 'new_bit' stuffing, shifting, and XOR operations for a single input bit */ +module XOR_Shift (stage_input, + poly, + new_bit, + stage_output); + + parameter crc_width = 32; + + input [crc_width-1:0] stage_input; + input [crc_width-1:0] poly; + input new_bit; + output [crc_width-1:0] stage_output; + + assign stage_output[0] = new_bit ^ stage_input[crc_width-1]; + assign stage_output[crc_width-1:1] = stage_input[crc_width-2:0] ^ ({crc_width-1{stage_output[0]}} & poly[crc_width-1:1]); + +endmodule diff --git a/ip/hw_crc32_qsys/hw_crc32_hw.tcl b/ip/hw_crc32_qsys/hw_crc32_hw.tcl new file mode 100644 index 0000000..558a1e0 --- /dev/null +++ b/ip/hw_crc32_qsys/hw_crc32_hw.tcl @@ -0,0 +1,105 @@ +# +# request TCL package from ACDS 16.1 +# +package require -exact qsys 16.1 + + +# +# module pulpino +# +set_module_property DESCRIPTION "HW CRC32" +set_module_property NAME hw_crc32 +#set_module_property VERSION 1.0 +set_module_property INTERNAL false +set_module_property OPAQUE_ADDRESS_MAP true +set_module_property GROUP "DSP" +set_module_property AUTHOR "" +set_module_property DISPLAY_NAME hw_crc32 +set_module_property INSTANTIATE_IN_SYSTEM_MODULE true +set_module_property EDITABLE true +set_module_property REPORT_TO_TALKBACK false +set_module_property ALLOW_GREYBOX_GENERATION false +set_module_property REPORT_HIERARCHY false + + +set adv_dbg_if false + +# +# file sets +# +add_fileset QUARTUS_SYNTH QUARTUS_SYNTH "" "" +set_fileset_property QUARTUS_SYNTH TOP_LEVEL CRC_Component +set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false +add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE + + +add_fileset sim_verilog SIM_VERILOG "" "Verilog Simulation" +set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false +set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE false +set_fileset_property SIM_VERILOG TOP_LEVEL CRC_Component +add_fileset_file CRC_Component.v SYSTEM_VERILOG PATH CRC_Component.v TOP_LEVEL_FILE + + + +# +# connection point clk_sink +# +add_interface clk_sink clock end +set_interface_property clk_sink ENABLED true +set_interface_property clk_sink EXPORT_OF "" +set_interface_property clk_sink PORT_NAME_MAP "" +set_interface_property clk_sink CMSIS_SVD_VARIABLES "" +set_interface_property clk_sink SVD_ADDRESS_GROUP "" + +add_interface_port clk_sink clk clk Input 1 + + + +# +# connection point reset_sink +# +add_interface reset_sink reset end +set_interface_property reset_sink associatedClock clk_sink +set_interface_property reset_sink synchronousEdges DEASSERT +set_interface_property reset_sink ENABLED true +set_interface_property reset_sink EXPORT_OF "" +set_interface_property reset_sink PORT_NAME_MAP "" +set_interface_property reset_sink CMSIS_SVD_VARIABLES "" +set_interface_property reset_sink SVD_ADDRESS_GROUP "" + +add_interface_port reset_sink reset reset Input 1 + + + +# +# connection point avalon_slave +# +add_interface avalon_slave avalon end +set_interface_property avalon_slave addressUnits WORDS +set_interface_property avalon_slave associatedClock clk_sink +set_interface_property avalon_slave associatedReset reset_sink +set_interface_property avalon_slave bitsPerSymbol 8 +set_interface_property avalon_slave burstOnBurstBoundariesOnly false +set_interface_property avalon_slave burstcountUnits WORDS +set_interface_property avalon_slave explicitAddressSpan 0 +set_interface_property avalon_slave holdTime 0 +set_interface_property avalon_slave linewrapBursts false +set_interface_property avalon_slave maximumPendingReadTransactions 0 +set_interface_property avalon_slave readLatency 1 +set_interface_property avalon_slave readWaitTime 1 +set_interface_property avalon_slave setupTime 0 +set_interface_property avalon_slave timingUnits Cycles +set_interface_property avalon_slave writeWaitTime 0 +set_interface_property avalon_slave ENABLED true +set_interface_property avalon_slave EXPORT_OF "" +set_interface_property avalon_slave PORT_NAME_MAP "" +set_interface_property avalon_slave CMSIS_SVD_VARIABLES "" +set_interface_property avalon_slave SVD_ADDRESS_GROUP "" +add_interface_port avalon_slave address address Input 3 +add_interface_port avalon_slave readdata readdata Output 32 +add_interface_port avalon_slave read read Input 1 +add_interface_port avalon_slave chipselect chipselect Input 1 +add_interface_port avalon_slave byteenable byteenable Input 4 +add_interface_port avalon_slave write write Input 1 +add_interface_port avalon_slave writedata writedata Input 32 diff --git a/software/sys_controller/memory/flash.c b/software/sys_controller/memory/flash.c index df146f8..4561bf4 100644 --- a/software/sys_controller/memory/flash.c +++ b/software/sys_controller/memory/flash.c @@ -21,7 +21,7 @@ #include #include "system.h" #include "flash.h" -#include "ci_crc.h" +#include "utils.h" extern alt_epcq_controller_dev epcq_controller_0; @@ -50,7 +50,7 @@ int read_flash(alt_u32 offset, alt_u32 length, alt_u8 *dstbuf) return -FLASH_READ_ERROR; for (i=0; i> 24; + dstbuf[i] = bitswap8(dstbuf[i]); return 0; } @@ -71,7 +71,7 @@ int write_flash_page(alt_u8 *pagedata, alt_u32 length, alt_u32 pagenum) // Bit-reverse bytes for flash for (i=0; i> 24; + pagedata[i] = bitswap8(pagedata[i]); retval = alt_epcq_controller_write_block(&epcq_controller_dev->dev, (pagenum/PAGES_PER_SECTOR)*PAGES_PER_SECTOR*PAGESIZE, pagenum*PAGESIZE, pagedata, length); @@ -95,7 +95,7 @@ int verify_flash(alt_u32 offset, alt_u32 length, alt_u32 golden_crc, alt_u8 *tmp if (retval != 0) return retval; - //crcval = crcCI(tmpbuf, bytes_to_read, (i==0)); + crcval = crc32(tmpbuf, bytes_to_read, (i==0)); } if (crcval != golden_crc) diff --git a/software/sys_controller/ossc/firmware.c b/software/sys_controller/ossc/firmware.c index 6f490f9..e480591 100644 --- a/software/sys_controller/ossc/firmware.c +++ b/software/sys_controller/ossc/firmware.c @@ -26,7 +26,7 @@ #include "tvp7002.h" #include "av_controller.h" #include "lcd.h" -#include "ci_crc.h" +#include "utils.h" #include "altera_avalon_pio_regs.h" extern char menu_row1[LCD_ROW_LEN+1], menu_row2[LCD_ROW_LEN+1]; @@ -48,19 +48,19 @@ static int check_fw_header(alt_u8 *databuf, fw_hdr *hdr) hdr->version_suffix[7] = 0; memcpy(&tmp, databuf+14, 4); - hdr->hdr_len = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp); + hdr->hdr_len = bswap32(tmp); memcpy(&tmp, databuf+18, 4); - hdr->data_len = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp); + hdr->data_len = bswap32(tmp); memcpy(&tmp, databuf+22, 4); - hdr->data_crc = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp); + hdr->data_crc = bswap32(tmp); // Always at bytes [508-511] memcpy(&tmp, databuf+508, 4); - hdr->hdr_crc = ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(tmp); + hdr->hdr_crc = bswap32(tmp); if (hdr->hdr_len < 26 || hdr->hdr_len > 508) return FW_HDR_ERROR; - //crcval = crcCI(databuf, hdr->hdr_len, 1); + crcval = crc32(databuf, hdr->hdr_len, 1); if (crcval != hdr->hdr_crc) return FW_HDR_CRC_ERROR; @@ -81,7 +81,7 @@ static int check_fw_image(alt_u32 offset, alt_u32 size, alt_u32 golden_crc, alt_ if (retval != SD_OK) return retval; - //crcval = crcCI(tmpbuf, bytes_to_read, (i==0)); + crcval = crc32(tmpbuf, bytes_to_read, (i==0)); } if (crcval != golden_crc) diff --git a/software/sys_controller/ossc/utils.c b/software/sys_controller/ossc/utils.c new file mode 100644 index 0000000..db7b984 --- /dev/null +++ b/software/sys_controller/ossc/utils.c @@ -0,0 +1,80 @@ +// +// Copyright (C) 2018 Markus Hiienkari +// +// This file is part of Open Source Scan Converter project. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#include "utils.h" +#include "system.h" +#include "io.h" + +unsigned char bitswap8(unsigned char v) +{ + return ((v * 0x0802LU & 0x22110LU) | + (v * 0x8020LU & 0x88440LU)) * 0x10101LU >> 16; +} + +alt_u32 bswap32(alt_u32 w) +{ + return (((w << 24) & 0xff000000) | + ((w << 8) & 0x00ff0000) | + ((w >> 8) & 0x0000ff00) | + ((w >> 24) & 0x000000ff)); +} + +unsigned long crc32(unsigned char *input_data, unsigned long input_data_length, int do_initialize) +{ + unsigned long index; + + /* copy of the data buffer pointer so that it can advance by different widths */ + void * input_data_copy = (void *)input_data; + + /* The custom instruction CRC will initialize to the inital remainder value */ + if (do_initialize) + IOWR_32DIRECT(HW_CRC32_0_BASE, 0x0, 0x0); + + /* Write 32 bit data to the custom instruction. If the buffer does not end + * on a 32 bit boundary then the remaining data will be sent to the custom + * instruction in the 'if' statement below. + */ + for(index = 0; index < (input_data_length & 0xFFFFFFFC); index+=4) + { + IOWR_32DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned long *)input_data_copy); + input_data_copy += 4; /* void pointer, must move by 4 for each word */ + } + + /* Write the remainder of the buffer if it does not end on a word boundary */ + if((input_data_length & 0x3) == 0x3) /* 3 bytes left */ + { + IOWR_16DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned short *)input_data_copy); + input_data_copy += 2; + IOWR_8DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned char *)input_data_copy); + } + else if((input_data_length & 0x3) == 0x2) /* 2 bytes left */ + { + IOWR_16DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned short *)input_data_copy); + } + else if((input_data_length & 0x3) == 0x1) /* 1 byte left */ + { + IOWR_8DIRECT(HW_CRC32_0_BASE, 0x4, *(unsigned char *)input_data_copy); + } + + /* There are 4 registers in the CRC custom instruction. Since + * this example uses CRC-32 only the first register must be read + * in order to receive the full result. + */ + return IORD_32DIRECT(HW_CRC32_0_BASE, 0x10); +} diff --git a/software/sys_controller/ossc/utils.h b/software/sys_controller/ossc/utils.h new file mode 100644 index 0000000..80a81e6 --- /dev/null +++ b/software/sys_controller/ossc/utils.h @@ -0,0 +1,31 @@ +// +// Copyright (C) 2018 Markus Hiienkari +// +// This file is part of Open Source Scan Converter project. +// +// This program is free software: you can redistribute it and/or modify +// it under the terms of the GNU General Public License as published by +// the Free Software Foundation, either version 3 of the License, or +// (at your option) any later version. +// +// This program is distributed in the hope that it will be useful, +// but WITHOUT ANY WARRANTY; without even the implied warranty of +// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +// GNU General Public License for more details. +// +// You should have received a copy of the GNU General Public License +// along with this program. If not, see . +// + +#ifndef UTILS_H_ +#define UTILS_H_ + +#include + +unsigned char bitswap8(unsigned char v); + +alt_u32 bswap32(alt_u32 w); + +unsigned long crc32(unsigned char *input_data, unsigned long input_data_length, int do_initialize); + +#endif diff --git a/software/sys_controller_bsp/drivers/inc/ci_crc.h b/software/sys_controller_bsp/drivers/inc/ci_crc.h deleted file mode 100644 index ba4d983..0000000 --- a/software/sys_controller_bsp/drivers/inc/ci_crc.h +++ /dev/null @@ -1,38 +0,0 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - - -#ifndef _CRCCI_H_ -#define _CRCCI_H_ - -unsigned long crcCI(unsigned char * input_data, unsigned long input_data_length, int do_initialize); - -#endif //_CRCCI_H_ diff --git a/software/sys_controller_bsp/drivers/inc/crc.h b/software/sys_controller_bsp/drivers/inc/crc.h deleted file mode 100644 index 4db516e..0000000 --- a/software/sys_controller_bsp/drivers/inc/crc.h +++ /dev/null @@ -1,109 +0,0 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - - -/********************************************************************** - * - * Filename: crc.h - * - * Description: A header file describing the various CRC standards. - * - * Notes: - * - * - * Copyright (c) 2000 by Michael Barr. This software is placed into - * the public domain and may be used for any purpose. However, this - * notice must not be changed or removed and no warranty is either - * expressed or implied by its publication or distribution. - **********************************************************************/ - -#ifndef _crc_h -#define _crc_h - - -#define FALSE 0 -#define TRUE !FALSE - -/* - * Select the CRC standard from the list that follows. - */ -#define CRC32 - - -#if defined(CRC_CCITT) - -typedef unsigned short crc; - -#define CRC_NAME "CRC-CCITT" -#define POLYNOMIAL 0x1021 -#define INITIAL_REMAINDER 0xFFFF -#define FINAL_XOR_VALUE 0x0000 -#define REFLECT_DATA FALSE -#define REFLECT_REMAINDER FALSE -#define CHECK_VALUE 0x29B1 - -#elif defined(CRC16) - -typedef unsigned short crc; - -#define CRC_NAME "CRC-16" -#define POLYNOMIAL 0x8005 -#define INITIAL_REMAINDER 0x0000 -#define FINAL_XOR_VALUE 0x0000 -#define REFLECT_DATA TRUE -#define REFLECT_REMAINDER TRUE -#define CHECK_VALUE 0xBB3D - -#elif defined(CRC32) - -typedef unsigned long crc; - -#define CRC_NAME "CRC-32" -#define POLYNOMIAL 0x04C11DB7 -#define INITIAL_REMAINDER 0xFFFFFFFF -#define FINAL_XOR_VALUE 0xFFFFFFFF -#define REFLECT_DATA TRUE -#define REFLECT_REMAINDER TRUE -#define CHECK_VALUE 0xCBF43926 - -#else - -#error "One of CRC_CCITT, CRC16, or CRC32 must be #define'd." - -#endif - - -void crcInit(void); -crc crcSlow(unsigned char const message[], int nBytes); -crc crcFast(unsigned char const message[], int nBytes); - - -#endif /* _crc_h */ diff --git a/software/sys_controller_bsp/drivers/src/ci_crc.c b/software/sys_controller_bsp/drivers/src/ci_crc.c deleted file mode 100644 index 7f9b0f0..0000000 --- a/software/sys_controller_bsp/drivers/src/ci_crc.c +++ /dev/null @@ -1,97 +0,0 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - - -/********************************************************************** - * - * Filename: ci_crc.c - * - * Description: Custom instruction implementations of the CRC. - * - * Notes: A macro is defined that is used to access the CRC custom - * instruction. - *********************************************************************/ - -#include "system.h" - -/*The n values and their corresponding operation are as follow: - * n = 0, Initialize the custom instruction to the initial remainder value - * n = 1, Write 8 bits data to custom instruction - * n = 2, Write 16 bits data to custom instruction - * n = 3, Write 32 bits data to custom instruction - * n = 4, Read 32 bits data from the custom instruction - * n = 5, Read 64 bits data from the custom instruction - * n = 6, Read 96 bits data from the custom instruction - * n = 7, Read 128 bits data from the custom instruction*/ -#define CRC_CI_MACRO(n, A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N + (n & 0x7), (A)) - -unsigned long crcCI(unsigned char * input_data, unsigned long input_data_length, int do_initialize) -{ - unsigned long index; - /* copy of the data buffer pointer so that it can advance by different widths */ - void * input_data_copy = (void *)input_data; - - /* The custom instruction CRC will initialize to the inital remainder value */ - if (do_initialize) - CRC_CI_MACRO(0,0); - - /* Write 32 bit data to the custom instruction. If the buffer does not end - * on a 32 bit boundary then the remaining data will be sent to the custom - * instruction in the 'if' statement below. - */ - for(index = 0; index < (input_data_length & 0xFFFFFFFC); index+=4) - { - CRC_CI_MACRO(3, *(unsigned long *)input_data_copy); - input_data_copy += 4; /* void pointer, must move by 4 for each word */ - } - - /* Write the remainder of the buffer if it does not end on a word boundary */ - if((input_data_length & 0x3) == 0x3) /* 3 bytes left */ - { - CRC_CI_MACRO(2, *(unsigned short *)input_data_copy); - input_data_copy += 2; - CRC_CI_MACRO(1, *(unsigned char *)input_data_copy); - } - else if((input_data_length & 0x3) == 0x2) /* 2 bytes left */ - { - CRC_CI_MACRO(2, *(unsigned short *)input_data_copy); - } - else if((input_data_length & 0x3) == 0x1) /* 1 byte left */ - { - CRC_CI_MACRO(1, *(unsigned char *)input_data_copy); - } - - /* There are 4 registers in the CRC custom instruction. Since - * this example uses CRC-32 only the first register must be read - * in order to receive the full result. - */ - return CRC_CI_MACRO(4, 0); -} diff --git a/software/sys_controller_bsp/drivers/src/crc.c b/software/sys_controller_bsp/drivers/src/crc.c deleted file mode 100644 index f00568d..0000000 --- a/software/sys_controller_bsp/drivers/src/crc.c +++ /dev/null @@ -1,265 +0,0 @@ -/****************************************************************************** -* * -* License Agreement * -* * -* Copyright (c) 2008 Altera Corporation, San Jose, California, USA. * -* All rights reserved. * -* * -* Permission is hereby granted, free of charge, to any person obtaining a * -* copy of this software and associated documentation files (the "Software"), * -* to deal in the Software without restriction, including without limitation * -* the rights to use, copy, modify, merge, publish, distribute, sublicense, * -* and/or sell copies of the Software, and to permit persons to whom the * -* Software is furnished to do so, subject to the following conditions: * -* * -* The above copyright notice and this permission notice shall be included in * -* all copies or substantial portions of the Software. * -* * -* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * -* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * -* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * -* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * -* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * -* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * -* DEALINGS IN THE SOFTWARE. * -* * -* This agreement shall be governed in all respects by the laws of the State * -* of California and by the laws of the United States of America. * -* Altera does not recommend, suggest or require that this reference design * -* file be used in conjunction or combination with any other product. * -******************************************************************************/ - - -/********************************************************************** - * - * Filename: crc.c - * - * Description: Slow and fast implementations of the CRC standards. - * - * Notes: The parameters for each supported CRC standard are - * defined in the header file crc.h. The implementations - * here should stand up to further additions to that list. - * - * - * Copyright (c) 2000 by Michael Barr. This software is placed into - * the public domain and may be used for any purpose. However, this - * notice must not be changed or removed and no warranty is either - * expressed or implied by its publication or distribution. - **********************************************************************/ - -#include "crc.h" - - -/* - * Derive parameters from the standard-specific parameters in crc.h. - */ -#define WIDTH (8 * sizeof(crc)) -#define TOPBIT (1 << (WIDTH - 1)) - -#if (REFLECT_DATA == TRUE) -#undef REFLECT_DATA -#define REFLECT_DATA(X) ((unsigned char) reflect((X), 8)) -#else -#undef REFLECT_DATA -#define REFLECT_DATA(X) (X) -#endif - -#if (REFLECT_REMAINDER == TRUE) -#undef REFLECT_REMAINDER -#define REFLECT_REMAINDER(X) ((crc) reflect((X), WIDTH)) -#else -#undef REFLECT_REMAINDER -#define REFLECT_REMAINDER(X) (X) -#endif - - -/********************************************************************* - * - * Function: reflect() - * - * Description: Reorder the bits of a binary sequence, by reflecting - * them about the middle position. - * - * Notes: No checking is done that nBits <= 32. - * - * Returns: The reflection of the original data. - * - *********************************************************************/ -static unsigned long -reflect(unsigned long data, unsigned char nBits) -{ - unsigned long reflection = 0x00000000; - unsigned char bit; - - /* - * Reflect the data about the center bit. - */ - for (bit = 0; bit < nBits; ++bit) - { - /* - * If the LSB bit is set, set the reflection of it. - */ - if (data & 0x01) - { - reflection |= (1 << ((nBits - 1) - bit)); - } - - data = (data >> 1); - } - - return (reflection); - -} /* reflect() */ - - -/********************************************************************* - * - * Function: crcSlow() - * - * Description: Compute the CRC of a given message. - * - * Notes: - * - * Returns: The CRC of the message. - * - *********************************************************************/ -crc -crcSlow(unsigned char const message[], int nBytes) -{ - crc remainder = INITIAL_REMAINDER; - int byte; - unsigned char bit; - - - /* - * Perform modulo-2 division, a byte at a time. - */ - for (byte = 0; byte < nBytes; ++byte) - { - /* - * Bring the next byte into the remainder. - */ - remainder ^= (REFLECT_DATA(message[byte]) << (WIDTH - 8)); - - /* - * Perform modulo-2 division, a bit at a time. - */ - for (bit = 8; bit > 0; --bit) - { - /* - * Try to divide the current data bit. - */ - if (remainder & TOPBIT) - { - remainder = (remainder << 1) ^ POLYNOMIAL; - } - else - { - remainder = (remainder << 1); - } - } - } - - /* - * The final remainder is the CRC result. - */ - return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); - -} /* crcSlow() */ - - -crc crcTable[256]; - - -/********************************************************************* - * - * Function: crcInit() - * - * Description: Populate the partial CRC lookup table. - * - * Notes: This function must be rerun any time the CRC standard - * is changed. If desired, it can be run "offline" and - * the table results stored in an embedded system's ROM. - * - * Returns: None defined. - * - *********************************************************************/ -void -crcInit(void) -{ - crc remainder; - int dividend; - unsigned char bit; - - - /* - * Compute the remainder of each possible dividend. - */ - for (dividend = 0; dividend < 256; ++dividend) - { - /* - * Start with the dividend followed by zeros. - */ - remainder = dividend << (WIDTH - 8); - - /* - * Perform modulo-2 division, a bit at a time. - */ - for (bit = 8; bit > 0; --bit) - { - /* - * Try to divide the current data bit. - */ - if (remainder & TOPBIT) - { - remainder = (remainder << 1) ^ POLYNOMIAL; - } - else - { - remainder = (remainder << 1); - } - } - - /* - * Store the result into the table. - */ - crcTable[dividend] = remainder; - } - -} /* crcInit() */ - - -/********************************************************************* - * - * Function: crcFast() - * - * Description: Compute the CRC of a given message. - * - * Notes: crcInit() must be called first. - * - * Returns: The CRC of the message. - * - *********************************************************************/ -crc -crcFast(unsigned char const message[], int nBytes) -{ - crc remainder = INITIAL_REMAINDER; - unsigned char data; - int byte; - - - /* - * Divide the message by the polynomial, a byte at a time. - */ - for (byte = 0; byte < nBytes; ++byte) - { - data = REFLECT_DATA(message[byte]) ^ (remainder >> (WIDTH - 8)); - remainder = crcTable[data] ^ (remainder << 8); - } - - /* - * The final remainder is the CRC. - */ - return (REFLECT_REMAINDER(remainder) ^ FINAL_XOR_VALUE); - -} /* crcFast() */ diff --git a/software/sys_controller_bsp/system.h b/software/sys_controller_bsp/system.h index 3f10d63..b0d4636 100644 --- a/software/sys_controller_bsp/system.h +++ b/software/sys_controller_bsp/system.h @@ -133,17 +133,13 @@ * */ -//#define ALT_CI_NIOS2_HW_CRC32_0(n,A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N+(n&ALT_CI_NIOS2_HW_CRC32_0_N_MASK),(A)) +/*#define ALT_CI_NIOS2_HW_CRC32_0(n,A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N+(n&ALT_CI_NIOS2_HW_CRC32_0_N_MASK),(A)) #define ALT_CI_NIOS2_HW_CRC32_0_N 0x0 #define ALT_CI_NIOS2_HW_CRC32_0_N_MASK ((1<<3)-1) -//#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N,(A)) +#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N,(A)) #define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N 0x9 -//#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N,(A)) -#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N 0x8 - -#define ALT_CI_NIOS2_HW_CRC32_0(n,A) n -#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) A -#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) A +#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N,(A)) +#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N 0x8*/ /* @@ -323,6 +319,13 @@ #define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2" #define ONCHIP_MEMORY2_0_WRITABLE 1 +/* + * hw_crc32_0 configuration + * + */ +#define ALT_MODULE_CLASS_hw_crc32_0 hw_crc32 +#define HW_CRC32_0_BASE 0x21000 + /* * pio_0 configuration diff --git a/sys.qsys b/sys.qsys index 39f9b68..673ccbe 100644 --- a/sys.qsys +++ b/sys.qsys @@ -51,7 +51,7 @@ type = "String"; } } - element i2c_opencores_0 + element hw_crc32_0 { datum _sortIndex { @@ -59,6 +59,27 @@ type = "int"; } } + element hw_crc32_0.avalon_slave + { + datum _lockedAddress + { + value = "1"; + type = "boolean"; + } + datum baseAddress + { + value = "135168"; + type = "String"; + } + } + element i2c_opencores_0 + { + datum _sortIndex + { + value = "8"; + type = "int"; + } + } element i2c_opencores_0.avalon_slave_0 { datum _lockedAddress @@ -76,7 +97,7 @@ { datum _sortIndex { - value = "8"; + value = "9"; type = "int"; } } @@ -160,7 +181,7 @@ { datum _sortIndex { - value = "9"; + value = "10"; type = "int"; } } @@ -181,7 +202,7 @@ { datum _sortIndex { - value = "10"; + value = "11"; type = "int"; } } @@ -202,7 +223,7 @@ { datum _sortIndex { - value = "11"; + value = "12"; type = "int"; } } @@ -223,7 +244,7 @@ { datum _sortIndex { - value = "12"; + value = "13"; type = "int"; } } @@ -244,7 +265,7 @@ { datum _sortIndex { - value = "13"; + value = "14"; type = "int"; } } @@ -265,7 +286,7 @@ { datum _sortIndex { - value = "14"; + value = "15"; type = "int"; } } @@ -286,7 +307,7 @@ { datum _sortIndex { - value = "15"; + value = "16"; type = "int"; } } @@ -307,7 +328,7 @@ { datum _sortIndex { - value = "16"; + value = "17"; type = "int"; } } @@ -328,7 +349,7 @@ { datum _sortIndex { - value = "17"; + value = "18"; type = "int"; } } @@ -489,6 +510,7 @@ ADDRESS_STALL 1 ADVANCED_INFO 0 ALLOWS_COMPILING_OTHER_FAMILY_IP 1 ANY_QFP 0 CELL_LEVEL_BACK_ANNOTATION_DISABLED 0 COMPILER_SUPPORT 1 DSP 0 DSP_SHIFTER_BLOCK 0 DUMP_ASM_LAB_BITS_FOR_POWER 1 EMUL 1 ENABLE_ADVANCED_IO_ANALYSIS_GUI_FEATURES 1 ENABLE_PIN_PLANNER 0 ENGINEERING_SAMPLE 0 EPCS 1 ESB 0 FAKE1 0 FAKE2 0 FAKE3 0 FAMILY_LEVEL_INSTALLATION_ONLY 1 FASTEST 0 FINAL_TIMING_MODEL 0 FITTER_USE_FALLING_EDGE_DELAY 0 FPP_COMPLETELY_PLACES_AND_ROUTES_PERIPHERY 0 GENERATE_DC_ON_CURRENT_WARNING_FOR_INTERNAL_CLAMPING_DIODE 0 HARDCOPY 0 HAS_18_BIT_MULTS 0 HAS_ACE_SUPPORT 1 HAS_ACTIVE_PARALLEL_FLASH_SUPPORT 0 HAS_ADJUSTABLE_OUTPUT_IO_TIMING_MEAS_POINT 0 HAS_ADVANCED_IO_INVERTED_CORNER 0 HAS_ADVANCED_IO_POWER_SUPPORT 1 HAS_ADVANCED_IO_TIMING_SUPPORT 1 HAS_ALM_SUPPORT 0 HAS_ATOM_AND_ROUTING_POWER_MODELED_TOGETHER 0 HAS_AUTO_DERIVE_CLOCK_UNCERTAINTY_SUPPORT 0 HAS_AUTO_FIT_SUPPORT 1 HAS_BALANCED_OPT_TECHNIQUE_SUPPORT 1 HAS_BENEFICIAL_SKEW_SUPPORT 1 HAS_BITLEVEL_DRIVE_STRENGTH_CONTROL 1 HAS_BSDL_FILE_GENERATION 1 HAS_CDB_RE_NETWORK_PRESERVATION_SUPPORT 0 HAS_CGA_SUPPORT 1 HAS_CHECK_NETLIST_SUPPORT 0 HAS_CLOCK_REGION_CHECKER_ENABLED 1 HAS_CORE_JUNCTION_TEMP_DERATING 0 HAS_CROSSTALK_SUPPORT 0 HAS_CUSTOM_REGION_SUPPORT 1 HAS_DAP_JTAG_FROM_HPS 0 HAS_DATA_DRIVEN_ACVQ_HSSI_SUPPORT 0 HAS_DDB_FDI_SUPPORT 0 HAS_DESIGN_ANALYZER_SUPPORT 1 HAS_DETAILED_IO_RAIL_POWER_MODEL 1 HAS_DETAILED_LEIM_STATIC_POWER_MODEL 1 HAS_DETAILED_LE_POWER_MODEL 1 HAS_DETAILED_ROUTING_MUX_STATIC_POWER_MODEL 1 HAS_DETAILED_THERMAL_CIRCUIT_PARAMETER_SUPPORT 1 HAS_DEVICE_MIGRATION_SUPPORT 1 HAS_DIAGONAL_MIGRATION_SUPPORT 0 HAS_EMIF_TOOLKIT_SUPPORT 0 HAS_ERROR_DETECTION_SUPPORT 0 HAS_FAMILY_VARIANT_MIGRATION_SUPPORT 0 HAS_FANOUT_FREE_NODE_SUPPORT 1 HAS_FAST_FIT_SUPPORT 1 HAS_FITTER_ECO_SUPPORT 1 HAS_FIT_NETLIST_OPT_RETIME_SUPPORT 1 HAS_FIT_NETLIST_OPT_SUPPORT 1 HAS_FORMAL_VERIFICATION_SUPPORT 1 HAS_FPGA_XCHANGE_SUPPORT 1 HAS_FSAC_LUTRAM_REGISTER_PACKING_SUPPORT 0 HAS_FULL_DAT_MIN_TIMING_SUPPORT 1 HAS_FULL_INCREMENTAL_DESIGN_SUPPORT 1 HAS_FUNCTIONAL_SIMULATION_SUPPORT 1 HAS_FUNCTIONAL_VERILOG_SIMULATION_SUPPORT 0 HAS_FUNCTIONAL_VHDL_SIMULATION_SUPPORT 0 HAS_GLITCH_FILTERING_SUPPORT 1 HAS_HARDCOPYII_SUPPORT 0 HAS_HC_READY_SUPPORT 0 HAS_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_HOLD_TIME_AVOIDANCE_ACROSS_CLOCK_SPINE_SUPPORT 1 HAS_HSPICE_WRITER_SUPPORT 1 HAS_HSSI_POWER_CALCULATOR 0 HAS_IBISO_WRITER_SUPPORT 0 HAS_ICD_DATA_IP 0 HAS_IDB_SUPPORT 1 HAS_INCREMENTAL_DAT_SUPPORT 1 HAS_INCREMENTAL_SYNTHESIS_SUPPORT 1 HAS_IO_ASSIGNMENT_ANALYSIS_SUPPORT 1 HAS_IO_DECODER 0 HAS_IO_PLACEMENT_OPTIMIZATION_SUPPORT 1 HAS_IO_PLACEMENT_USING_GEOMETRY_RULE 0 HAS_IO_PLACEMENT_USING_PHYSIC_RULE 0 HAS_IO_SMART_RECOMPILE_SUPPORT 0 HAS_JITTER_SUPPORT 1 HAS_JTAG_SLD_HUB_SUPPORT 1 HAS_LOGIC_LOCK_SUPPORT 1 HAS_MICROPROCESSOR 0 HAS_MIF_SMART_COMPILE_SUPPORT 1 HAS_MINMAX_TIMING_MODELING_SUPPORT 1 HAS_MIN_TIMING_ANALYSIS_SUPPORT 1 HAS_MUX_RESTRUCTURE_SUPPORT 1 HAS_NADDER_STYLE_CLOCKING 0 HAS_NADDER_STYLE_FF 0 HAS_NADDER_STYLE_LCELL_COMB 0 HAS_NEW_CDB_NAME_FOR_M20K_SCLR 0 HAS_NEW_HC_FLOW_SUPPORT 0 HAS_NEW_SERDES_MAX_RESOURCE_COUNT_REPORTING_SUPPORT 1 HAS_NEW_VPR_SUPPORT 1 HAS_NONSOCKET_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_NO_HARDBLOCK_PARTITION_SUPPORT 0 HAS_NO_JTAG_USERCODE_SUPPORT 0 HAS_OPERATING_SETTINGS_AND_CONDITIONS_REPORTING_SUPPORT 1 HAS_PAD_LOCATION_ASSIGNMENT_SUPPORT 0 HAS_PARTIAL_RECONFIG_SUPPORT 0 HAS_PASSIVE_PARALLEL_SUPPORT 0 HAS_PDN_MODEL_STATUS 0 HAS_PHYSICAL_DESIGN_PLANNER_SUPPORT 0 HAS_PHYSICAL_NETLIST_OUTPUT 0 HAS_PHYSICAL_ROUTING_SUPPORT 0 HAS_PIN_SPECIFIC_VOLTAGE_SUPPORT 1 HAS_PLDM_REF_SUPPORT 1 HAS_POWER_BINNING_LIMITS_DATA 0 HAS_POWER_ESTIMATION_SUPPORT 1 HAS_PRELIMINARY_CLOCK_UNCERTAINTY_NUMBERS 0 HAS_PRE_FITTER_FPP_SUPPORT 0 HAS_PRE_FITTER_LUTRAM_NETLIST_CHECKER_ENABLED 0 HAS_PVA_SUPPORT 1 HAS_QUARTUS_HIERARCHICAL_DESIGN_SUPPORT 0 HAS_RAPID_RECOMPILE_SUPPORT 0 HAS_RCF_SUPPORT 1 HAS_RCF_SUPPORT_FOR_DEBUGGING 0 HAS_RED_BLACK_SEPARATION_SUPPORT 0 HAS_RE_LEVEL_TIMING_GRAPH_SUPPORT 1 HAS_RISEFALL_DELAY_SUPPORT 1 HAS_SIGNAL_PROBE_SUPPORT 1 HAS_SIGNAL_TAP_SUPPORT 1 HAS_SIMULATOR_SUPPORT 0 HAS_SPLIT_IO_SUPPORT 1 HAS_SPLIT_LC_SUPPORT 1 HAS_STRICT_PRESERVATION_SUPPORT 1 HAS_SYNTHESIS_ON_ATOMS 0 HAS_SYNTH_FSYN_NETLIST_OPT_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_RETIME_SUPPORT 1 HAS_SYNTH_NETLIST_OPT_SUPPORT 1 HAS_TCL_FITTER_SUPPORT 0 HAS_TECHNOLOGY_MIGRATION_SUPPORT 0 HAS_TEMPLATED_REGISTER_PACKING_SUPPORT 1 HAS_TIME_BORROWING_SUPPORT 0 HAS_TIMING_DRIVEN_SYNTHESIS_SUPPORT 1 HAS_TIMING_INFO_SUPPORT 1 HAS_TIMING_OPERATING_CONDITIONS 1 HAS_TIMING_SIMULATION_SUPPORT 1 HAS_TITAN_BASED_MAC_REGISTER_PACKER_SUPPORT 0 HAS_U2B2_SUPPORT 0 HAS_USER_HIGH_SPEED_LOW_POWER_TILE_SUPPORT 0 HAS_USE_FITTER_INFO_SUPPORT 1 HAS_VCCPD_POWER_RAIL 0 HAS_VERTICAL_MIGRATION_SUPPORT 1 HAS_VIEWDRAW_SYMBOL_SUPPORT 0 HAS_VIO_SUPPORT 1 HAS_VIRTUAL_DEVICES 0 HAS_WYSIWYG_DFFEAS_SUPPORT 1 HAS_XIBISO2_WRITER_SUPPORT 0 HAS_XIBISO_WRITER_SUPPORT 1 IFP_USE_LEGACY_IO_CHECKER 0 INCREMENTAL_DESIGN_SUPPORTS_COMPATIBLE_CONSTRAINTS 1 INSTALLED 0 INTERNAL_POF_SUPPORT_ENABLED 0 INTERNAL_USE_ONLY 0 ISSUE_MILITARY_TEMPERATURE_WARNING 0 IS_BARE_DIE 0 IS_CONFIG_ROM 0 IS_DEFAULT_FAMILY 0 IS_FOR_INTERNAL_TESTING_ONLY 0 IS_HARDCOPY_FAMILY 0 IS_HBGA_PACKAGE 0 IS_HIGH_CURRENT_PART 0 IS_LOW_POWER_PART 0 IS_REVE_SILICON 0 IS_SDM_ONLY_PACKAGE 0 IS_SMI_PART 0 LOAD_BLK_TYPE_DATA_FROM_ATOM_WYS_INFO 0 LVDS_IO 1 M10K_MEMORY 0 M144K_MEMORY 0 M20K_MEMORY 0 M4K_MEMORY 0 M512_MEMORY 0 M9K_MEMORY 1 MLAB_MEMORY 0 MRAM_MEMORY 0 NOT_LISTED 0 NOT_MIGRATABLE 0 NO_FITTER_DELAY_CACHE_GENERATED 0 NO_PIN_OUT 0 NO_POF 0 NO_RPE_SUPPORT 0 NO_SUPPORT_FOR_LOGICLOCK_CONTENT_BACK_ANNOTATION 1 NO_SUPPORT_FOR_STA_CLOCK_UNCERTAINTY_CHECK 0 NO_TDC_SUPPORT 0 POSTFIT_BAK_DATABASE_EXPORT_ENABLED 1 POSTMAP_BAK_DATABASE_EXPORT_ENABLED 1 PROGRAMMER_ONLY 0 PROGRAMMER_SUPPORT 1 PVA_SUPPORTS_ONLY_SUBSET_OF_ATOMS 0 QFIT_IN_DEVELOPMENT 0 QMAP_IN_DEVELOPMENT 0 RAM_LOGICAL_NAME_CHECKING_IN_CUT_ENABLED 1 REPORTS_METASTABILITY_MTBF 1 REQUIRES_INSTALLATION_PATCH 0 REQUIRES_LIST_OF_TEMPERATURE_AND_VOLTAGE_OPERATING_CONDITIONS 1 REQUIRE_QUARTUS_HIERARCHICAL_DESIGN 0 REQUIRE_SPECIAL_HANDLING_FOR_LOCAL_LABLINE 1 RESERVES_SIGNAL_PROBE_PINS 0 RESOLVE_MAX_FANOUT_EARLY 1 RESOLVE_MAX_FANOUT_LATE 0 RESPECTS_FIXED_SIZED_LOCKED_LOCATION_LOGICLOCK 1 RESTRICTED_USER_SELECTION 0 RESTRICT_PARTIAL_RECONFIG 0 RISEFALL_SUPPORT_IS_HIDDEN 0 SHOW_HIDDEN_FAMILY_IN_PROGRAMMER 0 STRICT_TIMING_DB_CHECKS 0 SUPPORTS_ADDITIONAL_OPTIONS_FOR_UNUSED_IO 0 SUPPORTS_CRC 1 SUPPORTS_DIFFERENTIAL_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_DSP_BALANCING_BACK_ANNOTATION 0 SUPPORTS_GENERATION_OF_EARLY_POWER_ESTIMATOR_FILE 1 SUPPORTS_GLOBAL_SIGNAL_BACK_ANNOTATION 0 SUPPORTS_HIPI_RETIMING 0 SUPPORTS_LICENSE_FREE_PARTIAL_RECONFIG 0 SUPPORTS_MAC_CHAIN_OUT_ADDER 0 SUPPORTS_RAM_PACKING_BACK_ANNOTATION 0 SUPPORTS_REG_PACKING_BACK_ANNOTATION 0 SUPPORTS_SIGNALPROBE_REGISTER_PIPELINING 1 SUPPORTS_SINGLE_ENDED_AIOT_BOARD_TRACE_MODEL 1 SUPPORTS_USER_MANUAL_LOGIC_DUPLICATION 1 SUPPORTS_VID 0 SUPPORT_HIGH_SPEED_HPS 0 TMV_RUN_CUSTOMIZABLE_VIEWER 1 TMV_RUN_INTERNAL_DETAILS 1 TMV_RUN_INTERNAL_DETAILS_ON_IO 0 TMV_RUN_INTERNAL_DETAILS_ON_IOBUF 1 TMV_RUN_INTERNAL_DETAILS_ON_LCELL 0 TMV_RUN_INTERNAL_DETAILS_ON_LRAM 0 TRANSCEIVER_3G_BLOCK 0 TRANSCEIVER_6G_BLOCK 0 USES_ACV_FOR_FLED 1 USES_ADB_FOR_BACK_ANNOTATION 1 USES_ALTERA_LNSIM 0 USES_ASIC_ROUTING_POWER_CALCULATOR 0 USES_DATA_DRIVEN_PLL_COMPUTATION_UTIL 1 USES_DEV 1 USES_ICP_FOR_ECO_FITTER 0 USES_LIBERTY_TIMING 0 USES_NETWORK_ROUTING_POWER_CALCULATOR 0 USES_PART_INFO_FOR_DISPLAYING_CORE_VOLTAGE_VALUE 0 USES_POWER_SIGNAL_ACTIVITIES 1 USES_PVAFAM2 0 USES_SECOND_GENERATION_PART_INFO 0 USES_SECOND_GENERATION_POWER_ANALYZER 0 USES_THIRD_GENERATION_TIMING_MODELS_TIS 1 USES_U2B2_TIMING_MODELS 0 USES_XML_FORMAT_FOR_EMIF_PIN_MAP_FILE 0 USE_ADVANCED_IO_POWER_BY_DEFAULT 1 USE_ADVANCED_IO_TIMING_BY_DEFAULT 1 USE_BASE_FAMILY_DDB_PATH 0 USE_OCT_AUTO_CALIBRATION 1 USE_RELAX_IO_ASSIGNMENT_RULES 0 USE_RISEFALL_ONLY 1 USE_SEPARATE_LIST_FOR_TECH_MIGRATION 0 USE_SINGLE_COMPILER_PASS_PLL_MIF_FILE_WRITER 1 USE_TITAN_IO_BASED_IO_REGISTER_PACKER_UTIL 0 USING_28NM_OR_OLDER_TIMING_METHODOLOGY 1 WYSIWYG_BUS_WIDTH_CHECKING_IN_CUT_ENABLED 1 + + + + + + + + diff --git a/sys.sopcinfo b/sys.sopcinfo index 8f6d1fe..5548d6b 100644 --- a/sys.sopcinfo +++ b/sys.sopcinfo @@ -1,11 +1,11 @@ - + java.lang.Integer - 1538769758 + 1538869480 false true false @@ -414,6 +414,12 @@ parameters are a RESULT of the module parameters. --> clk_sink pulpino_0.clk_sink + + false + hw_crc32_0 + clk_sink + hw_crc32_0.clk_sink + false i2c_opencores_0 @@ -1636,6 +1642,493 @@ parameters are a RESULT of the module parameters. --> + + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + + + + boolean + false + false + true + false + true + + + java.lang.String + + false + true + false + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clock + false + + clk + Input + 1 + clk + + + + + + java.lang.String + clk_sink + false + true + true + true + + + com.altera.sopcmodel.reset.Reset$Edges + DEASSERT + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + reset + false + + reset + Input + 1 + reset + + + + + + embeddedsw.configuration.isFlash + 0 + + + embeddedsw.configuration.isMemoryDevice + 0 + + + embeddedsw.configuration.isNonVolatileStorage + 0 + + + embeddedsw.configuration.isPrintableDevice + 0 + + + com.altera.sopcmodel.avalon.AvalonConnectionPoint$AddressAlignment + DYNAMIC + false + true + false + true + + + int + 0 + false + true + false + true + + + java.math.BigInteger + 32 + true + true + false + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.lang.String + clk_sink + false + true + true + true + + + java.lang.String + reset_sink + false + true + true + true + + + int + 8 + false + true + true + true + + + java.math.BigInteger + + false + true + false + true + + + com.altera.entityinterfaces.IConnectionPoint + + false + true + false + true + + + boolean + false + false + true + true + true + + + com.altera.sopcmodel.avalon.EAddrBurstUnits + WORDS + false + true + true + true + + + boolean + false + false + true + false + true + + + java.math.BigInteger + 0 + false + true + true + true + + + int + 0 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + true + true + + + int + 0 + false + false + true + true + + + int + 0 + false + false + true + true + + + int + 1 + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 1 + false + true + true + true + + + int + 1 + false + true + false + true + + + int + 1 + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + true + true + + + com.altera.sopcmodel.avalon.TimingUnits + Cycles + false + true + true + true + + + boolean + false + false + true + false + true + + + boolean + false + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + false + true + + + int + 0 + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + avalon + false + + address + Input + 3 + address + + + readdata + Output + 32 + readdata + + + read + Input + 1 + read + + + chipselect + Input + 1 + chipselect + + + byteenable + Input + 4 + byteenable + + + write + Input + 1 + write + + + writedata + Input + 32 + writedata + + + 131104 8 + + false + hw_crc32_0 + avalon_slave + hw_crc32_0.avalon_slave + 135168 + 32 + false i2c_opencores_0 @@ -14732,6 +15233,57 @@ parameters are a RESULT of the module parameters. --> jtag_uart_0 avalon_jtag_slave + + + int + 1 + false + true + true + true + + + java.math.BigInteger + 0x00021000 + false + true + true + true + + + boolean + false + false + true + true + true + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + pulpino_0 + avalon_master_lsu + hw_crc32_0 + avalon_slave + pulpino_0 clk_sink + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk + hw_crc32_0 + clk_sink + pulpino_0 reset_sink + + + java.lang.String + UNKNOWN + false + true + true + true + + + boolean + false + false + true + true + true + + clk_27 + clk_reset + hw_crc32_0 + reset_sink + 1 clock_source @@ -16741,7 +17347,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 17 + 18 clock_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -16749,7 +17355,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 17 + 18 reset_sink com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -16757,7 +17363,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 18 + 19 avalon_slave com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IMutableConnectionPoint @@ -16772,6 +17378,14 @@ parameters are a RESULT of the module parameters. --> Interrupt Sender 17.1 + + 1 + hw_crc32 + com.altera.entityinterfaces.IElementClass + com.altera.entityinterfaces.IModule + hw_crc32 + 1.0 + 2 i2c_opencores @@ -16861,7 +17475,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 19 + 20 avalon com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -16869,7 +17483,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 17 + 18 clock com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection @@ -16885,7 +17499,7 @@ parameters are a RESULT of the module parameters. --> 17.1 - 17 + 18 reset com.altera.entityinterfaces.IElementClass com.altera.entityinterfaces.IConnection