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Merge branch 'paulb-nl-gbi' into rv-integration

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This commit is contained in:
marqs 2018-10-24 21:39:55 +03:00
commit f2405989e9
7 changed files with 99 additions and 41 deletions
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2
ossc.qsf
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@ -224,7 +224,7 @@ set_global_assignment -name ENABLE_SIGNALTAP OFF
set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp set_global_assignment -name USE_SIGNALTAP_FILE output_files/ossc_la.stp
set_global_assignment -name FITTER_EFFORT "AUTO FIT" set_global_assignment -name FITTER_EFFORT "AUTO FIT"
set_global_assignment -name SEED 3 set_global_assignment -name SEED 15

21
rtl/scanconverter.v
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@ -42,6 +42,7 @@
`define H_MULTMODE_FULLWIDTH 2'h0 `define H_MULTMODE_FULLWIDTH 2'h0
`define H_MULTMODE_ASPECTFIX 2'h1 `define H_MULTMODE_ASPECTFIX 2'h1
`define H_MULTMODE_OPTIMIZED 2'h2 `define H_MULTMODE_OPTIMIZED 2'h2
`define H_MULTMODE_OPTIMIZED_1X 2'h3
`define SCANLINES_OFF 2'h0 `define SCANLINES_OFF 2'h0
`define SCANLINES_H 2'h1 `define SCANLINES_H 2'h1
@ -187,6 +188,8 @@ reg [2:0] H_OPT_SCALE;
reg [2:0] H_OPT_SAMPLE_MULT; reg [2:0] H_OPT_SAMPLE_MULT;
reg [2:0] H_OPT_SAMPLE_SEL; reg [2:0] H_OPT_SAMPLE_SEL;
reg [9:0] H_L5BORDER; reg [9:0] H_L5BORDER;
reg [9:0] H_L3BORDER;
reg [6:0] H_L3_OPT_SAMPLE_COMP;
reg [3:0] X_MASK_BR; reg [3:0] X_MASK_BR;
reg X_SCANLINE_METHOD; reg X_SCANLINE_METHOD;
reg [4:0] X_SCANLINE_HYBRSTR; reg [4:0] X_SCANLINE_HYBRSTR;
@ -375,12 +378,18 @@ case (V_MULTMODE)
col_id_act = {2'b00, hcnt_2x[0]}; col_id_act = {2'b00, hcnt_2x[0]};
rlpf_trigger_act = 1'b1; rlpf_trigger_act = 1'b1;
end end
`H_MULTMODE_OPTIMIZED: begin `H_MULTMODE_OPTIMIZED_1X: begin
pclk_mux_sel = `PCLK_MUX_1X; //special case: pclk bypass to enable 2x native sampling pclk_mux_sel = `PCLK_MUX_1X; //special case: pclk bypass to enable 2x native sampling
linebuf_hoffset = hcnt_2x_opt; linebuf_hoffset = hcnt_2x_opt;
col_id_act = {2'b00, hcnt_2x[1]}; col_id_act = {2'b00, hcnt_2x[1]};
rlpf_trigger_act = (hcnt_2x_opt_ctr == 0); rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
end end
`H_MULTMODE_OPTIMIZED: begin
pclk_mux_sel = `PCLK_MUX_2X;
linebuf_hoffset = hcnt_2x_opt;
col_id_act = hcnt_2x_opt_ctr;
rlpf_trigger_act = (hcnt_2x_opt_ctr == 0);
end
endcase endcase
end end
`V_MULTMODE_3X: begin `V_MULTMODE_3X: begin
@ -870,6 +879,10 @@ begin
// H_L5BORDER <= h_info[29] ? (11'd1920-h_info[10:0])/2 : (11'd1600-h_info[10:0])/2; // H_L5BORDER <= h_info[29] ? (11'd1920-h_info[10:0])/2 : (11'd1600-h_info[10:0])/2;
H_L5BORDER <= h_info[29] ? H_L5BORDER_1920_tmp[10:1] : H_L5BORDER_1600_tmp[10:1]; H_L5BORDER <= h_info[29] ? H_L5BORDER_1920_tmp[10:1] : H_L5BORDER_1600_tmp[10:1];
// For Line3x 240x360
H_L3BORDER <= h_info[28] ? H_L5BORDER_1920_tmp[10:1] : 10'd0;
H_L3_OPT_SAMPLE_COMP <= h_info[28] ? 7'd90 : 7'd0;
H_OPT_SCALE <= h_info2[18:16]; H_OPT_SCALE <= h_info2[18:16];
H_OPT_SAMPLE_SEL <= h_info2[15:13]; H_OPT_SAMPLE_SEL <= h_info2[15:13];
@ -990,7 +1003,7 @@ begin
if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x if ((pclk_3x_cnt == 0) & (line_change | frame_change)) begin //aligned with posedge of pclk_1x
if (!(frame_change & (FID_cur == `FID_ODD))) begin if (!(frame_change & (FID_cur == `FID_ODD))) begin
hcnt_3x <= 0; hcnt_3x <= 0;
hcnt_3x_opt <= H_OPT_SAMPLE_SEL; hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
hcnt_3x_opt_ctr <= 0; hcnt_3x_opt_ctr <= 0;
line_out_idx_3x <= 0; line_out_idx_3x <= 0;
end end
@ -1001,7 +1014,7 @@ begin
end else if (hcnt_3x == hmax[~line_idx]) begin end else if (hcnt_3x == hmax[~line_idx]) begin
hcnt_3x <= 0; hcnt_3x <= 0;
line_out_idx_3x <= line_out_idx_3x + 1'b1; line_out_idx_3x <= line_out_idx_3x + 1'b1;
hcnt_3x_opt <= H_OPT_SAMPLE_SEL; hcnt_3x_opt <= H_OPT_SAMPLE_SEL + H_L3_OPT_SAMPLE_COMP;
hcnt_3x_opt_ctr <= 0; hcnt_3x_opt_ctr <= 0;
end else begin end else begin
hcnt_3x <= hcnt_3x + 1'b1; hcnt_3x <= hcnt_3x + 1'b1;
@ -1032,7 +1045,7 @@ begin
VSYNC_3x <= ~`VSYNC_POL; VSYNC_3x <= ~`VSYNC_POL;
end end
DE_3x <= ((hcnt_3x >= H_AVIDSTART) & (hcnt_3x < H_AVIDSTOP)) & ((vcnt_3x >= V_AVIDSTART) & (vcnt_3x < V_AVIDSTOP)); DE_3x <= ((hcnt_3x >= H_AVIDSTART-H_L3BORDER) & (hcnt_3x < H_AVIDSTOP+H_L3BORDER)) & ((vcnt_3x >= V_AVIDSTART) & (vcnt_3x < V_AVIDSTOP));
end end
end end

26
software/sys_controller/ossc/av_controller.c
View File

@ -365,7 +365,7 @@ status_t get_status(tvp_input_t input, video_format format)
} }
// h_info: [31:30] [29] [28] [27:20] [19:11] [10:0] // h_info: [31:30] [29] [28] [27:20] [19:11] [10:0]
// | H_MULTMODE[1:0] | H_L5FMT | | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] | // | H_MULTMODE[1:0] | H_L5FMT | H_L3_240x360 | H_SYNCLEN[7:0] | H_BACKPORCH[8:0] | H_ACTIVE[10:0] |
// //
// h_info2: [31:30] [29:19] [18:16] [15:13] [12:10] [9:0] // h_info2: [31:30] [29:19] [18:16] [15:13] [12:10] [9:0]
// | | H_MASK[10:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] | // | | H_MASK[10:0] | H_OPT_SCALE[2:0] | H_OPT_SAMPLE_SEL[2:0] | H_OPT_SAMPLE_MULT[2:0] | H_OPT_STARTOFF[9:0] |
@ -401,6 +401,7 @@ void set_videoinfo()
switch (cm.target_lm) { switch (cm.target_lm) {
case MODE_L2_320_COL: case MODE_L2_320_COL:
case MODE_L2_240x360:
h_opt_scale = 4; h_opt_scale = 4;
break; break;
case MODE_L2_256_COL: case MODE_L2_256_COL:
@ -412,36 +413,30 @@ void set_videoinfo()
case MODE_L3_256_COL: case MODE_L3_256_COL:
h_opt_scale = 4-cm.cc.ar_256col; h_opt_scale = 4-cm.cc.ar_256col;
break; break;
case MODE_L3_240x360:
h_opt_scale = 6;
break;
case MODE_L4_320_COL: case MODE_L4_320_COL:
h_opt_scale = 4; h_opt_scale = 4;
break; break;
case MODE_L4_256_COL: case MODE_L4_256_COL:
h_opt_scale = 5-cm.cc.ar_256col; h_opt_scale = 5-cm.cc.ar_256col;
break; break;
case MODE_L5_GEN_4_3:
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break;
case MODE_L5_320_COL: case MODE_L5_320_COL:
h_opt_scale = 5; h_opt_scale = 5;
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break; break;
case MODE_L5_256_COL: case MODE_L5_256_COL:
h_opt_scale = 6-cm.cc.ar_256col; h_opt_scale = 6-cm.cc.ar_256col;
if (cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
break; break;
default: default:
break; break;
} }
if (cm.target_lm >= MODE_L5_GEN_4_3 && cm.cc.l5_fmt == L5FMT_1920x1080) {
v_active -= 24;
v_backporch += 12;
}
// CEA-770.3 HDTV modes use tri-level syncs which have twice the width of bi-level syncs of corresponding CEA-861 modes // CEA-770.3 HDTV modes use tri-level syncs which have twice the width of bi-level syncs of corresponding CEA-861 modes
if (target_type == VIDEO_HDTV) if (target_type == VIDEO_HDTV)
h_synclen *= 2; h_synclen *= 2;
@ -459,6 +454,7 @@ void set_videoinfo()
IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (cm.fpga_hmultmode<<30) | IOWR_ALTERA_AVALON_PIO_DATA(PIO_3_BASE, (cm.fpga_hmultmode<<30) |
((cm.cc.l5_fmt!=L5FMT_1600x1200)<<29) | ((cm.cc.l5_fmt!=L5FMT_1600x1200)<<29) |
((cm.target_lm==MODE_L3_240x360)<<28) |
(((cm.sample_mult*h_synclen)&0xff)<<20) | (((cm.sample_mult*h_synclen)&0xff)<<20) |
(((cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch)&0x1ff)<<11) | (((cm.sample_mult*(alt_u16)video_modes[cm.id].h_backporch)&0x1ff)<<11) |
((cm.sample_mult*video_modes[cm.id].h_active)&0x7ff)); ((cm.sample_mult*video_modes[cm.id].h_active)&0x7ff));

1
software/sys_controller/ossc/av_controller.h
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@ -55,6 +55,7 @@
#define FPGA_H_MULTMODE_FULLWIDTH 0 #define FPGA_H_MULTMODE_FULLWIDTH 0
#define FPGA_H_MULTMODE_ASPECTFIX 1 #define FPGA_H_MULTMODE_ASPECTFIX 1
#define FPGA_H_MULTMODE_OPTIMIZED 2 #define FPGA_H_MULTMODE_OPTIMIZED 2
#define FPGA_H_MULTMODE_OPTIMIZED_1X 3
#define FPGA_SCANLINEMODE_OFF 0 #define FPGA_SCANLINEMODE_OFF 0
#define FPGA_SCANLINEMODE_H 1 #define FPGA_SCANLINEMODE_H 1

11
software/sys_controller/ossc/menu.c
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@ -51,12 +51,13 @@ static const char *video_lpf_desc[] = { LNG("Auto","ｵｰﾄ"), LNG("Off","ｵ
static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709" }; static const char *ypbpr_cs_desc[] = { "Rec. 601", "Rec. 709" };
static const char *s480p_mode_desc[] = { LNG("Auto","ｵｰﾄ"), "DTV 480p", "VESA 640x480@60" }; static const char *s480p_mode_desc[] = { LNG("Auto","ｵｰﾄ"), "DTV 480p", "VESA 640x480@60" };
static const char *sync_lpf_desc[] = { LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("Off","ｵﾌ") }; static const char *sync_lpf_desc[] = { LNG("2.5MHz (max)","2.5MHz (ｻｲﾀﾞｲ)"), LNG("10MHz (med)","10MHz (ﾁｭｳｲ)"), LNG("33MHz (min)","33MHz (ｻｲｼｮｳ)"), LNG("Off","ｵﾌ") };
static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") }; static const char *l3_mode_desc[] = { LNG("Generic 16:9","ｼﾞｪﾈﾘｯｸ 16:9"), LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") }; static const char *l2l4l5_mode_desc[] = { LNG("Generic 4:3","ｼﾞｪﾈﾘｯｸ 4:3"), LNG("512x240 optim.","512x240 ｻｲﾃｷｶ."), LNG("320x240 optim.","320x240 ｻｲﾃｷｶ."), LNG("256x240 optim.","256x240 ｻｲﾃｷｶ.") };
static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" }; static const char *l5_fmt_desc[] = { "1920x1080", "1600x1200", "1920x1200" };
static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" }; static const char *pm_240p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line3x", "Line4x", "Line5x" };
static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" }; static const char *pm_480i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)", "Line3x (laced)", "Line4x (bob)" };
static const char *pm_384p_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" }; static const char *pm_384p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x", "Line2x 240x360", "Line3x 240x360" };
static const char *pm_480p_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x" };
static const char *pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" }; static const char *pm_1080i_desc[] = { LNG("Passthru","ﾊﾟｽｽﾙｰ"), "Line2x (bob)" };
static const char *ar_256col_desc[] = { "4:3", "8:7" }; static const char *ar_256col_desc[] = { "4:3", "8:7" };
static const char *tx_mode_desc[] = { "HDMI", "DVI" }; static const char *tx_mode_desc[] = { "HDMI", "DVI" };
@ -132,9 +133,9 @@ MENU(menu_sync, P99_PROTECT({ \
MENU(menu_output, P99_PROTECT({ \ MENU(menu_output, P99_PROTECT({ \
{ LNG("240p/288p proc","240p/288pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p, OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } }, { LNG("240p/288p proc","240p/288pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_240p, OPT_WRAP, SETTING_ITEM(pm_240p_desc) } } },
{ LNG("384p proc","384pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_480p_desc) } } }, { LNG("384p proc","384pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_384p, OPT_WRAP, SETTING_ITEM(pm_384p_desc) } } },
{ LNG("480i/576i proc","480i/576iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } }, { LNG("480i/576i proc","480i/576iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480i, OPT_WRAP, SETTING_ITEM(pm_480i_desc) } } },
{ LNG("480p/576p proc","480p/576pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_384p_480p_desc) } } }, { LNG("480p/576p proc","480p/576pｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_480p, OPT_WRAP, SETTING_ITEM(pm_480p_desc) } } },
{ LNG("960i/1080i proc","960i/1080iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_1080i, OPT_WRAP, SETTING_ITEM(pm_1080i_desc) } } }, { LNG("960i/1080i proc","960i/1080iｼｮﾘ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.pm_1080i, OPT_WRAP, SETTING_ITEM(pm_1080i_desc) } } },
{ LNG("Line2x mode","Line2xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l2_mode, OPT_WRAP, SETTING_ITEM(l2l4l5_mode_desc) } } }, { LNG("Line2x mode","Line2xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l2_mode, OPT_WRAP, SETTING_ITEM(l2l4l5_mode_desc) } } },
{ LNG("Line3x mode","Line3xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } }, { LNG("Line3x mode","Line3xﾓｰﾄﾞ"), OPT_AVCONFIG_SELECTION, { .sel = { &tc.l3_mode, OPT_WRAP, SETTING_ITEM(l3_mode_desc) } } },

42
software/sys_controller/tvp7002/video_modes.c
View File

@ -49,7 +49,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
switch (video_modes[i].group) { switch (video_modes[i].group) {
case GROUP_NONE: case GROUP_NONE:
case GROUP_240P: case GROUP_240P:
break;
case GROUP_384P: case GROUP_384P:
//fixed Line2x/3x mode for 240x360p
valid_lm[2] = MODE_L2_240x360;
valid_lm[3] = MODE_L3_240x360;
break; break;
case GROUP_480I: case GROUP_480I:
//fixed Line3x/4x mode for 480i //fixed Line3x/4x mode for 480i
@ -107,7 +111,7 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X; cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
// Use native 2x sampling with low-res modes when possible to minimize jitter and generate min. 25MHz input pclk for FPGA PLL // Use native 2x sampling with low-res modes when possible to minimize jitter and generate min. 25MHz input pclk for FPGA PLL
if ((!cm.cc.vga_ilace_fix) && (video_modes[i].h_total < 1400) && ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_384P) || (video_modes[i].group == GROUP_480I))) { if ((!cm.cc.vga_ilace_fix) && (video_modes[i].h_total < 1400) && ((video_modes[i].group == GROUP_240P) || (video_modes[i].group == GROUP_384P) || (video_modes[i].group == GROUP_480I))) {
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED; cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 2; cm.sample_mult = 2;
} else { } else {
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH; cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@ -122,16 +126,26 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
} }
} }
break; break;
case MODE_L2_256_COL: case MODE_L2_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X; cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED; cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L2_256_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 6; cm.sample_mult = 6;
break; break;
case MODE_L2_320_COL: case MODE_L2_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X; cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED; cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED_1X;
cm.sample_mult = 4; cm.sample_mult = 4;
break; break;
case MODE_L2_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_2X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5;
break;
case MODE_L3_GEN_16_9: case MODE_L3_GEN_16_9:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X; cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH; cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@ -147,6 +161,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X; cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX; cm.fpga_hmultmode = FPGA_H_MULTMODE_ASPECTFIX;
break; break;
case MODE_L3_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L3_320_COL: case MODE_L3_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X; cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED; cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@ -157,6 +176,12 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED; cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 5; cm.sample_mult = 5;
break; break;
case MODE_L3_240x360:
cm.fpga_vmultmode = FPGA_V_MULTMODE_3X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 7;
cm.hsync_cut = 13;
break;
case MODE_L4_GEN_4_3: case MODE_L4_GEN_4_3:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X; cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH; cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
@ -168,6 +193,11 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.tx_pixelrep = TX_PIXELREP_2X; cm.tx_pixelrep = TX_PIXELREP_2X;
} }
break; break;
case MODE_L4_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 2;
break;
case MODE_L4_320_COL: case MODE_L4_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_4X; cm.fpga_vmultmode = FPGA_V_MULTMODE_4X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED; cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
@ -183,6 +213,12 @@ alt_8 get_mode_id(alt_u32 totlines, alt_u8 progressive, alt_u32 hz, video_type t
cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH; cm.fpga_hmultmode = FPGA_H_MULTMODE_FULLWIDTH;
cm.hsync_cut = 120; cm.hsync_cut = 120;
break; break;
case MODE_L5_512_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;
cm.sample_mult = 3;
cm.hsync_cut = 40;
break;
case MODE_L5_320_COL: case MODE_L5_320_COL:
cm.fpga_vmultmode = FPGA_V_MULTMODE_5X; cm.fpga_vmultmode = FPGA_V_MULTMODE_5X;
cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED; cm.fpga_hmultmode = FPGA_H_MULTMODE_OPTIMIZED;

35
software/sys_controller/tvp7002/video_modes.h
View File

@ -68,18 +68,24 @@ typedef enum {
//at least one of the flags below must be set for each mode //at least one of the flags below must be set for each mode
MODE_PT = (1<<2), MODE_PT = (1<<2),
MODE_L2 = (1<<3), MODE_L2 = (1<<3),
MODE_L2_320_COL = (1<<4), MODE_L2_512_COL = (1<<4),
MODE_L2_256_COL = (1<<5), MODE_L2_320_COL = (1<<5),
MODE_L3_GEN_16_9 = (1<<6), MODE_L2_256_COL = (1<<6),
MODE_L3_GEN_4_3 = (1<<7), MODE_L2_240x360 = (1<<7),
MODE_L3_320_COL = (1<<8), MODE_L3_GEN_16_9 = (1<<8),
MODE_L3_256_COL = (1<<9), MODE_L3_GEN_4_3 = (1<<9),
MODE_L4_GEN_4_3 = (1<<10), MODE_L3_512_COL = (1<<10),
MODE_L4_320_COL = (1<<11), MODE_L3_320_COL = (1<<11),
MODE_L4_256_COL = (1<<12), MODE_L3_256_COL = (1<<12),
MODE_L5_GEN_4_3 = (1<<13), MODE_L3_240x360 = (1<<13),
MODE_L5_320_COL = (1<<14), MODE_L4_GEN_4_3 = (1<<14),
MODE_L5_256_COL = (1<<15), MODE_L4_512_COL = (1<<15),
MODE_L4_320_COL = (1<<16),
MODE_L4_256_COL = (1<<17),
MODE_L5_GEN_4_3 = (1<<18),
MODE_L5_512_COL = (1<<19),
MODE_L5_320_COL = (1<<20),
MODE_L5_256_COL = (1<<21),
} mode_flags; } mode_flags;
typedef struct { typedef struct {
@ -103,6 +109,7 @@ typedef struct {
{ "1600x240", 1600, 240, 2046, 262, 202, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \ { "1600x240", 1600, 240, 2046, 262, 202, 15, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x240", 1280, 240, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \ { "1280x240", 1280, 240, 1560, 262, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x240", 960, 240, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \ { "960x240", 960, 240, 1170, 262, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240", 512, 240, 682, 262, 77, 14, 50, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "320x240", 320, 240, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \ { "320x240", 320, 240, 426, 262, 49, 14, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240", 256, 240, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \ { "256x240", 256, 240, 341, 262, 39, 14, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "240p", 720, 240, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ { "240p", 720, 240, 858, 262, 57, 15, 62, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
@ -110,9 +117,13 @@ typedef struct {
{ "1600x240L", 1600, 240, 2046, 312, 202, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \ { "1600x240L", 1600, 240, 2046, 312, 202, 41, 150, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L5_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "1280x288", 1280, 288, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \ { "1280x288", 1280, 288, 1560, 312, 170, 15, 72, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_16_9 | MODE_L4_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "960x288", 960, 288, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \ { "960x288", 960, 288, 1170, 312, 128, 15, 54, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L3_GEN_4_3 | MODE_PLLDIVBY2) }, \
{ "512x240LB", 512, 240, 682, 312, 77, 41, 50, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_512_COL | MODE_L3_512_COL | MODE_L4_512_COL | MODE_L5_512_COL) }, \
{ "320x240LB", 320, 240, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \ { "320x240LB", 320, 240, 426, 312, 49, 41, 31, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_320_COL | MODE_L3_320_COL | MODE_L4_320_COL | MODE_L5_320_COL) }, \
{ "256x240LB", 256, 240, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \ { "256x240LB", 256, 240, 341, 312, 39, 41, 25, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_L2_256_COL | MODE_L3_256_COL | MODE_L4_256_COL | MODE_L5_256_COL) }, \
{ "288p", 720, 288, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ { "288p", 720, 288, 864, 312, 69, 19, 63, 3, (VIDEO_SDTV | VIDEO_PC), GROUP_240P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 360p: GBI */ \
{ "480x360", 480, 360, 600, 375, 63, 10, 38, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
{ "240x360", 256, 360, 300, 375, 24, 10, 18, 3, (VIDEO_EDTV), GROUP_384P, (MODE_L2_240x360 | MODE_L3_240x360) }, \
/* 384p: Sega Model 2 */ \ /* 384p: Sega Model 2 */ \
{ "384p", 496, 384, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \ { "384p", 496, 384, 640, 423, 50, 29, 62, 3, (VIDEO_EDTV), GROUP_384P, (MODE_PT | MODE_L2 | MODE_PLLDIVBY2) }, \
/* 640x400, VGA Mode 13h */ \ /* 640x400, VGA Mode 13h */ \