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27 lines
982 B
Verilog
27 lines
982 B
Verilog
//
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// Copyright (C) 2017 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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`define LT_POS_NONE 2'b00
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`define LT_POS_TOPLEFT 2'b01
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`define LT_POS_CENTER 2'b10
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`define LT_POS_BOTTOMRIGHT 2'b11
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`define LT_WIDTH_DIV 8
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`define LT_HEIGHT_DIV 8
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