mirror of
https://github.com/marqs85/ossc.git
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222 lines
5.9 KiB
Verilog
222 lines
5.9 KiB
Verilog
//
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// Copyright (C) 2015-2016 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//`define DEBUG
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//`define INPUTLATCH
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`define VIDEOGEN
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module ossc (
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input clk27,
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input ir_rx,
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inout scl,
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inout sda,
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input [1:0] btn,
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input [7:0] R_in,
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input [7:0] G_in,
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input [7:0] B_in,
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input FID_in,
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input VSYNC_in,
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input HSYNC_in,
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input PCLK_in,
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output [7:0] HDMI_TX_RD,
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output [7:0] HDMI_TX_GD,
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output [7:0] HDMI_TX_BD,
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output HDMI_TX_DE,
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output HDMI_TX_HS,
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output HDMI_TX_VS,
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output HDMI_TX_PCLK,
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input HDMI_TX_INT_N,
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input HDMI_TX_MODE,
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output reset_n,
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output LED_G,
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output LED_R,
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output LCD_RS,
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output LCD_CS_N,
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output LCD_BL,
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output SD_CLK,
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inout SD_CMD,
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inout [3:0] SD_DAT
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);
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wire cpu_reset_n;
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wire [7:0] sys_ctrl;
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wire h_unstable;
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wire [2:0] pclk_lock;
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wire [2:0] pll_lock_lost;
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wire [31:0] h_info;
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wire [31:0] v_info;
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wire [10:0] lines_out;
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wire [1:0] fpga_vsyncgen;
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wire [15:0] ir_code;
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wire [7:0] ir_code_cnt;
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wire [7:0] R_out, G_out, B_out;
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wire HSYNC_out;
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wire VSYNC_out;
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wire PCLK_out;
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wire DATA_enable;
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wire [7:0] R_out_videogen, G_out_videogen, B_out_videogen;
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wire HSYNC_out_videogen;
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wire VSYNC_out_videogen;
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wire PCLK_out_videogen;
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wire DATA_enable_videogen;
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reg [3:0] reset_n_ctr;
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reg reset_n_reg = 1'b1;
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`ifdef INPUTLATCH
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reg HSYNC_in_l, VSYNC_in_l, FID_in_l;
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reg [7:0] R_in_l, G_in_l, B_in_l;
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always @(posedge PCLK_in)
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begin
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HSYNC_in_l <= HSYNC_in;
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VSYNC_in_l <= VSYNC_in;
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FID_in_l <= FID_in;
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R_in_l <= R_in;
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G_in_l <= G_in;
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B_in_l <= B_in;
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end
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`endif
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`ifdef DEBUG
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assign LED_R = HSYNC_in;
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assign LED_G = VSYNC_in;
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`else
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assign LED_R = videogen_sel ? 1'b0 : ((pll_lock_lost != 3'b000)|h_unstable);
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assign LED_G = (ir_code == 0);
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`endif
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assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
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assign LCD_CS_N = sys_ctrl[6];
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assign LCD_RS = sys_ctrl[5];
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assign LCD_BL = sys_ctrl[4]; //reset_n in v1.2 PCB
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assign reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
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`ifdef VIDEOGEN
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wire videogen_sel;
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assign videogen_sel = ~sys_ctrl[1];
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assign HDMI_TX_RD = videogen_sel ? R_out_videogen : R_out;
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assign HDMI_TX_GD = videogen_sel ? G_out_videogen : G_out;
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assign HDMI_TX_BD = videogen_sel ? B_out_videogen : B_out;
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assign HDMI_TX_HS = videogen_sel ? HSYNC_out_videogen : HSYNC_out;
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assign HDMI_TX_VS = videogen_sel ? VSYNC_out_videogen : VSYNC_out;
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assign HDMI_TX_PCLK = videogen_sel ? PCLK_out_videogen : PCLK_out;
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assign HDMI_TX_DE = videogen_sel ? DATA_enable_videogen : DATA_enable;
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`else
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assign HDMI_TX_RD = R_out;
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assign HDMI_TX_GD = G_out;
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assign HDMI_TX_BD = B_out;
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assign HDMI_TX_HS = HSYNC_out;
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assign HDMI_TX_VS = VSYNC_out;
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assign HDMI_TX_PCLK = PCLK_out;
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assign HDMI_TX_DE = DATA_enable;
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`endif
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always @(posedge clk27)
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begin
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if (reset_n_ctr == 4'b1000)
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reset_n_reg <= 1'b1;
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else
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begin
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reset_n_ctr <= reset_n_ctr + 1'b1;
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reset_n_reg <= 1'b0;
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end
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end
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assign cpu_reset_n = reset_n_reg;
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sys sys_inst(
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.clk_clk (clk27),
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.reset_reset_n (cpu_reset_n),
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.i2c_opencores_0_export_scl_pad_io (scl),
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.i2c_opencores_0_export_sda_pad_io (sda),
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.i2c_opencores_0_export_spi_miso_pad_i (1'b0),
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.i2c_opencores_1_export_scl_pad_io (SD_CLK),
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.i2c_opencores_1_export_sda_pad_io (SD_CMD),
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.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
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.pio_0_sys_ctrl_out_export (sys_ctrl),
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.pio_1_controls_in_export ({ir_code_cnt, 5'b00000, HDMI_TX_MODE, btn, ir_code}),
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.pio_2_horizontal_info_out_export (h_info),
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.pio_3_vertical_info_out_export (v_info),
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.pio_4_linecount_in_export ({VSYNC_out, 13'h0000, fpga_vsyncgen, 5'h00, lines_out})
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);
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scanconverter scanconverter_inst (
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.reset_n (reset_n),
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.PCLK_in (PCLK_in),
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`ifdef INPUTLATCH
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.HSYNC_in (HSYNC_in_l),
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.VSYNC_in (VSYNC_in_l),
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.FID_in (FID_in_l),
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.R_in (R_in_l),
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.G_in (G_in_l),
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.B_in (B_in_l),
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`else
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.HSYNC_in (HSYNC_in),
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.VSYNC_in (VSYNC_in),
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.FID_in (FID_in),
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.R_in (R_in),
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.G_in (G_in),
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.B_in (B_in),
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`endif
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.h_info (h_info),
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.v_info (v_info),
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.R_out (R_out),
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.G_out (G_out),
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.B_out (B_out),
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.HSYNC_out (HSYNC_out),
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.VSYNC_out (VSYNC_out),
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.PCLK_out (PCLK_out),
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.DATA_enable (DATA_enable),
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.h_unstable (h_unstable),
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.fpga_vsyncgen (fpga_vsyncgen),
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.pclk_lock (pclk_lock),
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.pll_lock_lost (pll_lock_lost),
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.lines_out (lines_out)
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);
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ir_rcv ir0 (
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.clk27 (clk27),
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.reset_n (reset_n_reg),
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.ir_rx (ir_rx),
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.ir_code (ir_code),
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.ir_code_ack (),
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.ir_code_cnt (ir_code_cnt)
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);
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`ifdef VIDEOGEN
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videogen vg0 (
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.clk27 (clk27),
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.reset_n (reset_n_reg & videogen_sel),
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.R_out (R_out_videogen),
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.G_out (G_out_videogen),
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.B_out (B_out_videogen),
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.HSYNC_out (HSYNC_out_videogen),
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.VSYNC_out (VSYNC_out_videogen),
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.PCLK_out (PCLK_out_videogen),
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.ENABLE_out (DATA_enable_videogen)
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);
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`endif
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endmodule
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