mirror of https://github.com/marqs85/ossc.git
412 lines
14 KiB
Verilog
412 lines
14 KiB
Verilog
//
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// Copyright (C) 2022-2023 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module tvp7002_frontend (
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input PCLK_i,
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input CLK_MEAS_i,
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input reset_n,
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input [7:0] R_i,
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input [7:0] G_i,
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input [7:0] B_i,
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input HS_i,
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input VS_i,
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input HSYNC_i,
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input VSYNC_i,
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input DE_i,
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input FID_i,
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input sogref_update_i,
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input vsync_i_type,
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input [31:0] hv_in_config,
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input [31:0] hv_in_config2,
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input [31:0] hv_in_config3,
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input [31:0] misc_config,
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output [7:0] R_o,
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output [7:0] G_o,
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output [7:0] B_o,
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output HSYNC_o,
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output VSYNC_o,
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output DE_o,
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output FID_o,
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output reg interlace_flag,
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output datavalid_o,
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output [10:0] xpos_o,
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output [10:0] ypos_o,
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output reg [10:0] vtotal,
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output reg frame_change,
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output reg sof_scaler,
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output reg [19:0] pcnt_frame,
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output reg [7:0] hsync_width,
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output reg sync_active
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);
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localparam FID_EVEN = 1'b0;
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localparam FID_ODD = 1'b1;
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localparam VSYNC_SEPARATED = 1'b0;
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localparam VSYNC_RAW = 1'b1;
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localparam PP_PL_START = 1;
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localparam PP_RLPF_START = PP_PL_START;
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localparam PP_RLPF_LENGTH = 3;
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localparam PP_RLPF_END = PP_RLPF_START + PP_RLPF_LENGTH;
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localparam PP_PL_END = PP_RLPF_END;
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reg [11:0] h_cnt, h_cnt_sogref;
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reg [10:0] v_cnt;
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reg [10:0] vmax_cnt;
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reg HS_i_prev, VS_i_np_prev;
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reg HSYNC_i_np_prev, VSYNC_i_np_prev;
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reg [1:0] fid_next_ctr;
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reg fid_next;
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reg [3:0] h_ctr;
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reg [7:0] R_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [7:0] G_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [7:0] B_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg HSYNC_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg VSYNC_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg FID_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg DE_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg datavalid_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [10:0] xpos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [10:0] ypos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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// Reverse LPF
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wire rlpf_trigger_act;
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reg signed [14:0] R_diff_s15_pre, G_diff_s15_pre, B_diff_s15_pre, R_diff_s15, G_diff_s15, B_diff_s15;
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reg [7:0] R_pp_prev_rlpf, G_pp_prev_rlpf, B_pp_prev_rlpf;
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// Measurement registers
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reg [20:0] pcnt_frame_ctr;
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reg [17:0] syncpol_det_ctr, hsync_hpol_ctr, vsync_hpol_ctr;
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reg [3:0] sync_inactive_ctr;
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reg [11:0] pcnt_line, pcnt_line_ctr, meas_h_cnt, meas_h_cnt_sogref;
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reg [7:0] hs_ctr;
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reg pcnt_line_stored;
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reg [10:0] meas_v_cnt;
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reg meas_hl_det, meas_fid;
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reg hsync_i_pol, vsync_i_pol;
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wire [11:0] H_TOTAL = hv_in_config[11:0];
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wire [11:0] H_ACTIVE = hv_in_config[23:12];
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wire [7:0] H_SYNCLEN = hv_in_config[31:24];
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wire [8:0] H_BACKPORCH = hv_in_config2[8:0];
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wire [10:0] V_ACTIVE = hv_in_config2[30:20];
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wire [3:0] V_SYNCLEN = hv_in_config3[3:0];
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wire [8:0] V_BACKPORCH = hv_in_config3[12:4];
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wire [5:0] MISC_REV_LPF_STR = (misc_config[11:7] + 6'd16);
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wire MISC_REV_LPF_ENABLE = (misc_config[11:7] != 5'h0);
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wire [11:0] h_cnt_ref = (vsync_i_type == VSYNC_SEPARATED) ? h_cnt_sogref : h_cnt;
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wire [11:0] even_min_thold = (H_TOTAL / 12'd4);
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wire [11:0] even_max_thold = (H_TOTAL / 12'd2) + (H_TOTAL / 12'd4);
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wire [11:0] meas_h_cnt_ref = (vsync_i_type == VSYNC_SEPARATED) ? meas_h_cnt_sogref : meas_h_cnt;
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wire [11:0] meas_even_min_thold = (pcnt_line / 12'd4);
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wire [11:0] meas_even_max_thold = (pcnt_line / 12'd2) + (pcnt_line / 12'd4);
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wire meas_vblank_region = (pcnt_frame_ctr < 8*pcnt_line) | (pcnt_frame_ctr > (({1'b0, pcnt_frame}<<interlace_flag) - 4*pcnt_line)) |
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(interlace_flag & (pcnt_frame_ctr < (pcnt_frame+8*pcnt_line)) & (pcnt_frame_ctr > (pcnt_frame - 4*pcnt_line)));
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wire [11:0] glitch_filt_thold = meas_vblank_region ? (pcnt_line/4) : (pcnt_line/8);
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// TODO: calculate H/V polarity independently
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wire VS_i_np = (VS_i ^ ~vsync_i_pol);
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wire VSYNC_i_np = (VSYNC_i ^ ~vsync_i_pol);
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wire HSYNC_i_np = (HSYNC_i ^ ~hsync_i_pol);
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// Sample skip for low-res optimized modes
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wire [3:0] H_SKIP = hv_in_config3[27:24];
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wire [3:0] H_SAMPLE_SEL = hv_in_config3[31:28];
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// SOF position for scaler
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wire [10:0] V_SOF_LINE = hv_in_config3[23:13];
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function [7:0] apply_reverse_lpf;
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input [7:0] data_prev;
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input signed [14:0] diff;
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reg signed [10:0] result;
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begin
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result = {3'b0,data_prev} + ~diff[14:4]; // allow for a small error to reduce adder length
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apply_reverse_lpf = result[10] ? 8'h00 : |result[9:8] ? 8'hFF : result[7:0];
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end
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endfunction
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always @(posedge PCLK_i) begin
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R_pp[1] <= R_i;
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G_pp[1] <= G_i;
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B_pp[1] <= B_i;
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DE_pp[1] <= (h_cnt >= H_SYNCLEN+H_BACKPORCH) & (h_cnt < H_SYNCLEN+H_BACKPORCH+H_ACTIVE) & (v_cnt >= V_SYNCLEN+V_BACKPORCH) & (v_cnt < V_SYNCLEN+V_BACKPORCH+V_ACTIVE);
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datavalid_pp[1] <= (h_ctr == H_SAMPLE_SEL);
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xpos_pp[1] <= (h_cnt-H_SYNCLEN-H_BACKPORCH);
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ypos_pp[1] <= (v_cnt-V_SYNCLEN-V_BACKPORCH);
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HS_i_prev <= HS_i;
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VS_i_np_prev <= VS_i_np;
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if (HS_i_prev & ~HS_i) begin
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h_cnt <= 0;
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h_ctr <= 0;
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HSYNC_pp[1] <= 1'b0;
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if (fid_next_ctr > 0)
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fid_next_ctr <= fid_next_ctr - 1'b1;
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if (fid_next_ctr == 2'h1) begin
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// regenerated output timings start lagging by one scanline due to vsync detection,
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// compensate by starting v_cnt from 1 (effectively reduces V_SYNCLEN by 1)
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v_cnt <= 1;
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if (~(interlace_flag & (fid_next == FID_EVEN))) begin
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vmax_cnt <= 0;
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//vtotal <= vmax_cnt + 1'b1;
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frame_change <= 1'b1;
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end else begin
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vmax_cnt <= vmax_cnt + 1'b1;
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end
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end else begin
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v_cnt <= v_cnt + 1'b1;
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vmax_cnt <= vmax_cnt + 1'b1;
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frame_change <= 1'b0;
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end
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sof_scaler <= (vmax_cnt == V_SOF_LINE);
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end else begin
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if (h_ctr == H_SKIP) begin
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h_cnt <= h_cnt + 1'b1;
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h_ctr <= 0;
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if (h_cnt == H_SYNCLEN-1)
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HSYNC_pp[1] <= 1'b1;
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end else begin
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h_ctr <= h_ctr + 1'b1;
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end
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end
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// vsync leading edge processing per quadrant
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if (VS_i_np_prev & ~VS_i_np) begin
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if (h_cnt_ref < even_min_thold) begin
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fid_next <= FID_ODD;
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fid_next_ctr <= 2'h1;
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end else if ((h_cnt_ref > even_max_thold) | ~interlace_flag) begin
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fid_next <= FID_ODD;
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fid_next_ctr <= 2'h2;
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end else begin
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fid_next <= FID_EVEN;
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fid_next_ctr <= 2'h2;
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end
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end
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// record starting position of csync leading edge for later FID detection
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if (sogref_update_i) begin
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h_cnt_sogref <= (h_cnt > even_max_thold) ? 0 : h_cnt;
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end
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if (((fid_next == FID_ODD) & (HS_i_prev & ~HS_i)) | ((fid_next == FID_EVEN) & (h_cnt == (H_TOTAL/2)-1'b1))) begin
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if (fid_next_ctr == 2'h1) begin
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VSYNC_pp[1] <= 1'b0;
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FID_pp[1] <= fid_next;
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//interlace_flag <= FID_pp[1] ^ fid_next;
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end else begin
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if (v_cnt == V_SYNCLEN-1)
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VSYNC_pp[1] <= 1'b1;
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end
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end
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end
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// Pipeline stages 2-
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integer pp_idx;
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always @(posedge PCLK_i) begin
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for(pp_idx = PP_PL_START+1; pp_idx <= PP_PL_END; pp_idx = pp_idx+1) begin
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R_pp[pp_idx] <= R_pp[pp_idx-1];
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G_pp[pp_idx] <= G_pp[pp_idx-1];
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B_pp[pp_idx] <= B_pp[pp_idx-1];
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HSYNC_pp[pp_idx] <= HSYNC_pp[pp_idx-1];
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VSYNC_pp[pp_idx] <= VSYNC_pp[pp_idx-1];
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FID_pp[pp_idx] <= FID_pp[pp_idx-1];
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DE_pp[pp_idx] <= DE_pp[pp_idx-1];
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datavalid_pp[pp_idx] <= datavalid_pp[pp_idx-1];
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xpos_pp[pp_idx] <= xpos_pp[pp_idx-1];
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ypos_pp[pp_idx] <= ypos_pp[pp_idx-1];
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end
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/* ---------- Reverse LPF (3 cycles) ---------- */
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// Store a copy of valid sample data
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if (datavalid_pp[PP_RLPF_START]) begin
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R_pp_prev_rlpf <= R_pp[PP_RLPF_START];
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G_pp_prev_rlpf <= G_pp[PP_RLPF_START];
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B_pp_prev_rlpf <= B_pp[PP_RLPF_START];
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end
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// Push previous valid data into pipeline when RLPF enabled
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if (MISC_REV_LPF_ENABLE) begin
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R_pp[PP_RLPF_START+1] <= R_pp_prev_rlpf;
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G_pp[PP_RLPF_START+1] <= G_pp_prev_rlpf;
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B_pp[PP_RLPF_START+1] <= B_pp_prev_rlpf;
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end
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// Calculate diff to previous valid data
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R_diff_s15_pre <= (R_pp_prev_rlpf - R_pp[PP_RLPF_START]);
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G_diff_s15_pre <= (G_pp_prev_rlpf - G_pp[PP_RLPF_START]);
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B_diff_s15_pre <= (B_pp_prev_rlpf - B_pp[PP_RLPF_START]);
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// Cycle 2
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R_diff_s15 <= (R_diff_s15_pre * MISC_REV_LPF_STR);
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G_diff_s15 <= (G_diff_s15_pre * MISC_REV_LPF_STR);
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B_diff_s15 <= (B_diff_s15_pre * MISC_REV_LPF_STR);
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// Cycle 3
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if (MISC_REV_LPF_ENABLE) begin
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R_pp[PP_RLPF_END] <= apply_reverse_lpf(R_pp[PP_RLPF_START+2], R_diff_s15);
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G_pp[PP_RLPF_END] <= apply_reverse_lpf(G_pp[PP_RLPF_START+2], G_diff_s15);
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B_pp[PP_RLPF_END] <= apply_reverse_lpf(B_pp[PP_RLPF_START+2], B_diff_s15);
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end
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end
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// Output
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assign R_o = R_pp[PP_PL_END];
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assign G_o = G_pp[PP_PL_END];
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assign B_o = B_pp[PP_PL_END];
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assign HSYNC_o = HSYNC_pp[PP_PL_END];
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assign VSYNC_o = VSYNC_pp[PP_PL_END];
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assign FID_o = FID_pp[PP_PL_END];
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assign DE_o = DE_pp[PP_PL_END];
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assign datavalid_o = datavalid_pp[PP_PL_END];
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assign xpos_o = xpos_pp[PP_PL_END];
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assign ypos_o = ypos_pp[PP_PL_END];
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// Calculate horizontal and vertical counts
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always @(posedge CLK_MEAS_i) begin
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if ((VSYNC_i_np_prev & ~VSYNC_i_np) & (~interlace_flag | (meas_fid == FID_EVEN))) begin
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pcnt_frame_ctr <= 1;
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pcnt_line_stored <= 1'b0;
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pcnt_frame <= interlace_flag ? (pcnt_frame_ctr>>1) : pcnt_frame_ctr[19:0];
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end else if (pcnt_frame_ctr < 21'h1fffff) begin
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pcnt_frame_ctr <= pcnt_frame_ctr + 1'b1;
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end
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if (HSYNC_i_np_prev & ~HSYNC_i_np) begin
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pcnt_line_ctr <= 1;
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hs_ctr <= 1;
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// store count 1ms after vsync
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if (~pcnt_line_stored & (pcnt_frame_ctr > 21'd27000)) begin
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pcnt_line <= pcnt_line_ctr;
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hsync_width <= hs_ctr;
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pcnt_line_stored <= 1'b1;
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end
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end else begin
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pcnt_line_ctr <= pcnt_line_ctr + 1'b1;
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if (~HSYNC_i_np)
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hs_ctr <= hs_ctr + 1'b1;
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end
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HSYNC_i_np_prev <= HSYNC_i_np;
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VSYNC_i_np_prev <= VSYNC_i_np;
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end
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// Detect sync polarities and activity
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always @(posedge CLK_MEAS_i) begin
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if (syncpol_det_ctr == 0) begin
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hsync_i_pol <= (hsync_hpol_ctr > 18'h1ffff);
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vsync_i_pol <= (vsync_hpol_ctr > 18'h1ffff);
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hsync_hpol_ctr <= 0;
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vsync_hpol_ctr <= 0;
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if ((vsync_hpol_ctr == '0) | (vsync_hpol_ctr == '1)) begin
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if (sync_inactive_ctr == '1)
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sync_active <= 1'b0;
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else
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sync_inactive_ctr <= sync_inactive_ctr + 1'b1;
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end else begin
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sync_inactive_ctr <= 0;
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sync_active <= 1'b1;
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end
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end else begin
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if (HSYNC_i)
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hsync_hpol_ctr <= hsync_hpol_ctr + 1'b1;
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if (VSYNC_i)
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vsync_hpol_ctr <= vsync_hpol_ctr + 1'b1;
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end
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syncpol_det_ctr <= syncpol_det_ctr + 1'b1;
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end
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// Detect interlace and line count
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always @(posedge CLK_MEAS_i) begin
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if ((HSYNC_i_np_prev & ~HSYNC_i_np) & (meas_h_cnt > glitch_filt_thold)) begin
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// detect half-line equalization pulses
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if ((meas_h_cnt > ((pcnt_line/2) - (pcnt_line/4))) && (meas_h_cnt < ((pcnt_line/2) + (pcnt_line/4)))) begin
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/*if (meas_hl_det) begin
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meas_hl_det <= 1'b0;
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meas_h_cnt <= 0;
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meas_v_cnt <= meas_v_cnt + 1'b1;
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end else begin*/
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meas_hl_det <= 1'b1;
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meas_h_cnt <= meas_h_cnt + 1'b1;
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//end
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end else begin
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meas_hl_det <= 1'b0;
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meas_h_cnt <= 0;
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meas_v_cnt <= meas_v_cnt + 1'b1;
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end
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meas_h_cnt_sogref <= meas_h_cnt;
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end else if (meas_vblank_region & (meas_h_cnt >= pcnt_line)) begin
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// hsync may be missing or irregular during vblank, force line change detect if pcnt_line is exceeded
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meas_hl_det <= 1'b0;
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meas_h_cnt <= 0;
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meas_v_cnt <= meas_v_cnt + 1'b1;
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end else begin
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meas_h_cnt <= meas_h_cnt + 1'b1;
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end
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if (VSYNC_i_np_prev & ~VSYNC_i_np) begin
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if ((meas_h_cnt_ref < meas_even_min_thold) | (meas_h_cnt_ref > meas_even_max_thold)) begin
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meas_fid <= FID_ODD;
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interlace_flag <= (meas_fid == FID_EVEN);
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if (vsync_i_type == VSYNC_RAW) begin
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// vsync leading edge may occur at hsync edge or either side of it
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if ((HSYNC_i_np_prev & ~HSYNC_i_np) | (meas_h_cnt >= pcnt_line)) begin
|
|
meas_v_cnt <= 1;
|
|
vtotal <= meas_v_cnt;
|
|
end else if (meas_h_cnt < meas_even_min_thold) begin
|
|
meas_v_cnt <= 1;
|
|
vtotal <= meas_v_cnt - 1'b1;
|
|
end else begin
|
|
meas_v_cnt <= 0;
|
|
vtotal <= meas_v_cnt;
|
|
end
|
|
end else begin
|
|
meas_v_cnt <= 0;
|
|
vtotal <= meas_v_cnt;
|
|
end
|
|
end else begin
|
|
meas_fid <= FID_EVEN;
|
|
interlace_flag <= (meas_fid == FID_ODD);
|
|
if (meas_fid == FID_EVEN) begin
|
|
meas_v_cnt <= 0;
|
|
vtotal <= meas_v_cnt;
|
|
end
|
|
end
|
|
end
|
|
end
|
|
|
|
endmodule
|