mirror of https://github.com/marqs85/ossc.git
177 lines
7.1 KiB
Verilog
177 lines
7.1 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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// megafunction wizard: %FIFO%
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// GENERATION: STANDARD
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// VERSION: WM1.0
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// MODULE: scfifo
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// ============================================================
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// File Name: altera_epcq_controller_fifo.v
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// Megafunction Name(s):
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// scfifo
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//
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// Simulation Library Files(s):
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// altera_mf
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// ============================================================
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// ************************************************************
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// THIS IS A WIZARD-GENERATED FILE. DO NOT EDIT THIS FILE!
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//
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// 14.1.0 Internal Build 64 05/14/2014 PN Full Version
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// ************************************************************
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//Copyright (C) 1991-2014 Altera Corporation. All rights reserved.
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//Your use of Altera Corporation's design tools, logic functions
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//and other software and tools, and its AMPP partner logic
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//functions, and any output files from any of the foregoing
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//(including device programming or simulation files), and any
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//associated documentation or information are expressly subject
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//to the terms and conditions of the Altera Program License
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//Subscription Agreement, the Altera Quartus II License Agreement,
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//the Altera MegaCore Function License Agreement, or other
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//applicable license agreement, including, without limitation,
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//that your use is for the sole purpose of programming logic
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//devices manufactured by Altera and sold by Altera or its
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//authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synopsys translate_off
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`timescale 1 ps / 1 ps
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// synopsys translate_on
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module altera_epcq_controller_fifo #(
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parameter DEVICE_FAMILY = "CYCLONE V",
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parameter MEMORY_TYPE = "RAM_BLOCK_TYPE=MLAB"
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)(
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clock,
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data,
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rdreq,
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wrreq,
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empty,
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full,
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q);
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input clock;
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input [35:0] data;
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input rdreq;
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input wrreq;
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output empty;
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output full;
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output [35:0] q;
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wire sub_wire0;
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wire sub_wire1;
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wire [35:0] sub_wire2;
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wire empty = sub_wire0;
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wire full = sub_wire1;
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wire [35:0] q = sub_wire2[35:0];
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scfifo scfifo_component (
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.clock (clock),
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.data (data),
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.rdreq (rdreq),
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.wrreq (wrreq),
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.empty (sub_wire0),
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.full (sub_wire1),
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.q (sub_wire2),
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.aclr (),
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.almost_empty (),
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.almost_full (),
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.sclr (),
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.usedw ());
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defparam
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scfifo_component.add_ram_output_register = "OFF",
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scfifo_component.intended_device_family = DEVICE_FAMILY,
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scfifo_component.lpm_hint = MEMORY_TYPE,
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scfifo_component.lpm_numwords = 1024,
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scfifo_component.lpm_showahead = "ON",
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scfifo_component.lpm_type = "scfifo",
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scfifo_component.lpm_width = 36,
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scfifo_component.lpm_widthu = 10,
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scfifo_component.overflow_checking = "ON",
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scfifo_component.underflow_checking = "ON",
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scfifo_component.use_eab = "ON";
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endmodule
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// ============================================================
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// CNX file retrieval info
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// ============================================================
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// Retrieval info: PRIVATE: AlmostEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostEmptyThr NUMERIC "-1"
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// Retrieval info: PRIVATE: AlmostFull NUMERIC "0"
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// Retrieval info: PRIVATE: AlmostFullThr NUMERIC "-1"
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// Retrieval info: PRIVATE: CLOCKS_ARE_SYNCHRONIZED NUMERIC "0"
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// Retrieval info: PRIVATE: Clock NUMERIC "0"
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// Retrieval info: PRIVATE: Depth NUMERIC "1024"
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// Retrieval info: PRIVATE: Empty NUMERIC "1"
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// Retrieval info: PRIVATE: Full NUMERIC "1"
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// Retrieval info: PRIVATE: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
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// Retrieval info: PRIVATE: LE_BasedFIFO NUMERIC "0"
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// Retrieval info: PRIVATE: LegacyRREQ NUMERIC "0"
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// Retrieval info: PRIVATE: MAX_DEPTH_BY_9 NUMERIC "0"
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// Retrieval info: PRIVATE: OVERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: Optimize NUMERIC "0"
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// Retrieval info: PRIVATE: RAM_BLOCK_TYPE NUMERIC "2"
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// Retrieval info: PRIVATE: SYNTH_WRAPPER_GEN_POSTFIX STRING "0"
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// Retrieval info: PRIVATE: UNDERFLOW_CHECKING NUMERIC "0"
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// Retrieval info: PRIVATE: UsedW NUMERIC "0"
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// Retrieval info: PRIVATE: Width NUMERIC "8"
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// Retrieval info: PRIVATE: dc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: diff_widths NUMERIC "0"
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// Retrieval info: PRIVATE: msb_usedw NUMERIC "0"
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// Retrieval info: PRIVATE: output_width NUMERIC "8"
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// Retrieval info: PRIVATE: rsEmpty NUMERIC "1"
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// Retrieval info: PRIVATE: rsFull NUMERIC "0"
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// Retrieval info: PRIVATE: rsUsedW NUMERIC "0"
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// Retrieval info: PRIVATE: sc_aclr NUMERIC "0"
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// Retrieval info: PRIVATE: sc_sclr NUMERIC "0"
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// Retrieval info: PRIVATE: wsEmpty NUMERIC "0"
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// Retrieval info: PRIVATE: wsFull NUMERIC "1"
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// Retrieval info: PRIVATE: wsUsedW NUMERIC "0"
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// Retrieval info: LIBRARY: altera_mf altera_mf.altera_mf_components.all
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// Retrieval info: CONSTANT: ADD_RAM_OUTPUT_REGISTER STRING "OFF"
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// Retrieval info: CONSTANT: INTENDED_DEVICE_FAMILY STRING "Cyclone IV GX"
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// Retrieval info: CONSTANT: LPM_HINT STRING "RAM_BLOCK_TYPE=M9K"
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// Retrieval info: CONSTANT: LPM_NUMWORDS NUMERIC "1024"
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// Retrieval info: CONSTANT: LPM_SHOWAHEAD STRING "ON"
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// Retrieval info: CONSTANT: LPM_TYPE STRING "scfifo"
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// Retrieval info: CONSTANT: LPM_WIDTH NUMERIC "8"
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// Retrieval info: CONSTANT: LPM_WIDTHU NUMERIC "10"
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// Retrieval info: CONSTANT: OVERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: UNDERFLOW_CHECKING STRING "ON"
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// Retrieval info: CONSTANT: USE_EAB STRING "ON"
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// Retrieval info: USED_PORT: clock 0 0 0 0 INPUT NODEFVAL "clock"
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// Retrieval info: USED_PORT: data 0 0 8 0 INPUT NODEFVAL "data[7..0]"
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// Retrieval info: USED_PORT: empty 0 0 0 0 OUTPUT NODEFVAL "empty"
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// Retrieval info: USED_PORT: full 0 0 0 0 OUTPUT NODEFVAL "full"
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// Retrieval info: USED_PORT: q 0 0 8 0 OUTPUT NODEFVAL "q[7..0]"
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// Retrieval info: USED_PORT: rdreq 0 0 0 0 INPUT NODEFVAL "rdreq"
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// Retrieval info: USED_PORT: wrreq 0 0 0 0 INPUT NODEFVAL "wrreq"
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// Retrieval info: CONNECT: @clock 0 0 0 0 clock 0 0 0 0
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// Retrieval info: CONNECT: @data 0 0 8 0 data 0 0 8 0
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// Retrieval info: CONNECT: @rdreq 0 0 0 0 rdreq 0 0 0 0
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// Retrieval info: CONNECT: @wrreq 0 0 0 0 wrreq 0 0 0 0
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// Retrieval info: CONNECT: empty 0 0 0 0 @empty 0 0 0 0
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// Retrieval info: CONNECT: full 0 0 0 0 @full 0 0 0 0
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// Retrieval info: CONNECT: q 0 0 8 0 @q 0 0 8 0
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.v TRUE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.inc FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.cmp FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo.bsf FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_inst.v FALSE
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// Retrieval info: GEN_FILE: TYPE_NORMAL fifo_bb.v FALSE
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// Retrieval info: LIB_FILE: altera_mf
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