mirror of https://github.com/marqs85/ossc.git
649 lines
25 KiB
Tcl
649 lines
25 KiB
Tcl
# (C) 2001-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License Subscription
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# Agreement, Altera MegaCore Function License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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package require -exact qsys 14.1
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package require -exact altera_terp 1.0
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#
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# module altera_trace_wrapper
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#
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set_module_property DESCRIPTION "This component is a serial flash controller which allows user to access Altera EPCQ devices"
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set_module_property NAME altera_epcq_controller_mod
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set_module_property VERSION 15.1
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set_module_property INTERNAL false
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set_module_property OPAQUE_ADDRESS_MAP true
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set_module_property GROUP "Basic Functions/Configuration and Programming"
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set_module_property AUTHOR "Altera Corporation"
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set_module_property DISPLAY_NAME "Altera Serial Flash Controller"
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property HIDE_FROM_QUARTUS true
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set_module_property EDITABLE true
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set_module_property ALLOW_GREYBOX_GENERATION false
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set_module_property REPORT_HIERARCHY false
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set_module_property ELABORATION_CALLBACK elaboration
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add_fileset QUARTUS_SYNTH QUARTUS_SYNTH add_topwrapper_fileset_proc
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set_fileset_property QUARTUS_SYNTH TOP_LEVEL altera_epcq_controller_wrapper
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set_fileset_property QUARTUS_SYNTH ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property QUARTUS_SYNTH ENABLE_FILE_OVERWRITE_MODE false
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add_fileset SIM_VERILOG SIM_VERILOG add_topwrapper_fileset_proc
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set_fileset_property SIM_VERILOG TOP_LEVEL altera_epcq_controller_wrapper
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set_fileset_property SIM_VERILOG ENABLE_RELATIVE_INCLUDE_PATHS false
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set_fileset_property SIM_VERILOG ENABLE_FILE_OVERWRITE_MODE true
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#
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# parameters
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#
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# +-----------------------------------
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# | device family info
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# +-----------------------------------
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set all_supported_device_families_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "Stratix IV" \
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"Cyclone IV GX" "Cyclone IV E" "Cyclone III GL" "Arria II GZ" "Arria II GX"}
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proc check_device_ini {device_families_list} {
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set enable_max10 [get_quartus_ini enable_max10_active_serial ENABLED]
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if {$enable_max10 == 1} {
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lappend device_families_list "MAX 10 FPGA"
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}
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return $device_families_list
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}
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set device_list [check_device_ini $all_supported_device_families_list]
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set_module_property SUPPORTED_DEVICE_FAMILIES $device_list
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add_parameter DEVICE_FAMILY STRING
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set_parameter_property DEVICE_FAMILY SYSTEM_INFO {DEVICE_FAMILY}
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set_parameter_property DEVICE_FAMILY VISIBLE false
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set_parameter_property DEVICE_FAMILY HDL_PARAMETER true
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add_parameter ASI_WIDTH INTEGER 1
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set_parameter_property ASI_WIDTH DEFAULT_VALUE 1
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set_parameter_property ASI_WIDTH DISPLAY_NAME ASI_WIDTH
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set_parameter_property ASI_WIDTH DERIVED true
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set_parameter_property ASI_WIDTH TYPE INTEGER
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set_parameter_property ASI_WIDTH VISIBLE false
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set_parameter_property ASI_WIDTH UNITS None
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set_parameter_property ASI_WIDTH ALLOWED_RANGES {1, 4}
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set_parameter_property ASI_WIDTH HDL_PARAMETER true
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add_parameter CS_WIDTH INTEGER 1
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set_parameter_property CS_WIDTH DEFAULT_VALUE 1
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set_parameter_property CS_WIDTH DISPLAY_NAME CS_WIDTH
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set_parameter_property CS_WIDTH DERIVED true
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set_parameter_property CS_WIDTH TYPE INTEGER
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set_parameter_property CS_WIDTH VISIBLE false
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set_parameter_property CS_WIDTH UNITS None
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set_parameter_property CS_WIDTH ALLOWED_RANGES {1, 3}
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set_parameter_property CS_WIDTH HDL_PARAMETER true
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add_parameter ADDR_WIDTH INTEGER 19
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set_parameter_property ADDR_WIDTH DEFAULT_VALUE 19
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set_parameter_property ADDR_WIDTH DISPLAY_NAME ADDR_WIDTH
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set_parameter_property ADDR_WIDTH DERIVED true
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set_parameter_property ADDR_WIDTH TYPE INTEGER
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set_parameter_property ADDR_WIDTH VISIBLE false
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set_parameter_property ADDR_WIDTH UNITS None
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# 16M-19bit, 32M-20bit, 64M-21bit, 128M-22bit, 256M-23bit, 512M-24bit, 1024M-25bit, 2048M-26bit...
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set_parameter_property ADDR_WIDTH ALLOWED_RANGES {19, 20, 21, 22, 23, 24, 25, 26, 27, 28}
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set_parameter_property ADDR_WIDTH HDL_PARAMETER true
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add_parameter ASMI_ADDR_WIDTH INTEGER 24
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set_parameter_property ASMI_ADDR_WIDTH DEFAULT_VALUE 24
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set_parameter_property ASMI_ADDR_WIDTH DISPLAY_NAME ASMI_ADDR_WIDTH
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set_parameter_property ASMI_ADDR_WIDTH DERIVED true
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set_parameter_property ASMI_ADDR_WIDTH TYPE INTEGER
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set_parameter_property ASMI_ADDR_WIDTH VISIBLE false
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set_parameter_property ASMI_ADDR_WIDTH UNITS None
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set_parameter_property ASMI_ADDR_WIDTH ALLOWED_RANGES {24, 32}
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set_parameter_property ASMI_ADDR_WIDTH HDL_PARAMETER true
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add_parameter ENABLE_4BYTE_ADDR INTEGER "0"
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set_parameter_property ENABLE_4BYTE_ADDR DISPLAY_NAME "Enable 4-byte addressing mode"
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set_parameter_property ENABLE_4BYTE_ADDR DESCRIPTION "Check to enable 4-byte addressing mode for device larger than 128Mbyte"
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set_parameter_property ENABLE_4BYTE_ADDR AFFECTS_GENERATION true
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set_parameter_property ENABLE_4BYTE_ADDR VISIBLE false
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set_parameter_property ENABLE_4BYTE_ADDR HDL_PARAMETER true
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set_parameter_property ENABLE_4BYTE_ADDR DERIVED true
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# +-----------------------------------
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# add system info parameter
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add_parameter deviceFeaturesSystemInfo STRING "None"
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set_parameter_property deviceFeaturesSystemInfo system_info "DEVICE_FEATURES"
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set_parameter_property deviceFeaturesSystemInfo VISIBLE false
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add_parameter DDASI INTEGER "0"
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set_parameter_property DDASI DISPLAY_NAME "Disable dedicated Active Serial interface"
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set_parameter_property DDASI DESCRIPTION "Check to route ASMIBLOCK signals to top level of design"
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set_parameter_property DDASI AFFECTS_GENERATION true
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set_parameter_property DDASI VISIBLE false
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set_parameter_property DDASI DERIVED false
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add_parameter clkFreq LONG
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set_parameter_property clkFreq DEFAULT_VALUE {0}
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set_parameter_property clkFreq DISPLAY_NAME {clkFreq}
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set_parameter_property clkFreq VISIBLE {0}
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set_parameter_property clkFreq AFFECTS_GENERATION {1}
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set_parameter_property clkFreq HDL_PARAMETER {0}
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set_parameter_property clkFreq SYSTEM_INFO {clock_rate clk}
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set_parameter_property clkFreq SYSTEM_INFO_TYPE {CLOCK_RATE}
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set_parameter_property clkFreq SYSTEM_INFO_ARG {clock_sink}
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#
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# connection point clock_sink
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#
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add_interface clock_sink clock end
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set_interface_property clock_sink clockRate 0
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set_interface_property clock_sink ENABLED true
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set_interface_property clock_sink EXPORT_OF ""
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set_interface_property clock_sink PORT_NAME_MAP ""
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set_interface_property clock_sink CMSIS_SVD_VARIABLES ""
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set_interface_property clock_sink SVD_ADDRESS_GROUP ""
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add_interface_port clock_sink clk clk Input 1
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#
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# connection point reset
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#
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add_interface reset reset end
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set_interface_property reset associatedClock clock_sink
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set_interface_property reset synchronousEdges DEASSERT
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set_interface_property reset ENABLED true
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set_interface_property reset EXPORT_OF ""
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set_interface_property reset PORT_NAME_MAP ""
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set_interface_property reset CMSIS_SVD_VARIABLES ""
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set_interface_property reset SVD_ADDRESS_GROUP ""
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add_interface_port reset reset_n reset_n Input 1
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#
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# connection point avl_csr
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#
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add_interface avl_csr avalon end
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set_interface_property avl_csr addressUnits WORDS
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set_interface_property avl_csr associatedClock clock_sink
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set_interface_property avl_csr associatedReset reset
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set_interface_property avl_csr bitsPerSymbol 8
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set_interface_property avl_csr burstOnBurstBoundariesOnly false
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set_interface_property avl_csr burstcountUnits WORDS
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set_interface_property avl_csr explicitAddressSpan 0
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set_interface_property avl_csr holdTime 0
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set_interface_property avl_csr linewrapBursts false
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set_interface_property avl_csr maximumPendingReadTransactions 1
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set_interface_property avl_csr maximumPendingWriteTransactions 0
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set_interface_property avl_csr readLatency 0
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set_interface_property avl_csr readWaitTime 0
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set_interface_property avl_csr setupTime 0
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set_interface_property avl_csr timingUnits Cycles
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set_interface_property avl_csr writeWaitTime 0
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set_interface_property avl_csr ENABLED true
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set_interface_property avl_csr EXPORT_OF ""
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set_interface_property avl_csr PORT_NAME_MAP ""
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set_interface_property avl_csr CMSIS_SVD_VARIABLES ""
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set_interface_property avl_csr SVD_ADDRESS_GROUP ""
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add_interface_port avl_csr avl_csr_read read Input 1
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add_interface_port avl_csr avl_csr_waitrequest waitrequest Output 1
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add_interface_port avl_csr avl_csr_write write Input 1
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add_interface_port avl_csr avl_csr_addr address Input 3
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add_interface_port avl_csr avl_csr_wrdata writedata Input 32
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add_interface_port avl_csr avl_csr_rddata readdata Output 32
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add_interface_port avl_csr avl_csr_rddata_valid readdatavalid Output 1
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#
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# connection point avl_mem
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#
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add_interface avl_mem avalon end
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set_interface_property avl_mem addressUnits WORDS
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set_interface_property avl_mem associatedClock clock_sink
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set_interface_property avl_mem associatedReset reset
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set_interface_property avl_mem bitsPerSymbol 8
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set_interface_property avl_mem burstOnBurstBoundariesOnly false
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set_interface_property avl_mem burstcountUnits WORDS
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set_interface_property avl_mem explicitAddressSpan 0
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set_interface_property avl_mem holdTime 0
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set_interface_property avl_mem linewrapBursts true
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set_interface_property avl_mem maximumPendingReadTransactions 1
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set_interface_property avl_mem maximumPendingWriteTransactions 0
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set_interface_property avl_mem constantBurstBehavior true
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set_interface_property avl_mem readLatency 0
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set_interface_property avl_mem readWaitTime 0
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set_interface_property avl_mem setupTime 0
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set_interface_property avl_mem timingUnits Cycles
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set_interface_property avl_mem writeWaitTime 0
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set_interface_property avl_mem ENABLED true
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set_interface_property avl_mem EXPORT_OF ""
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set_interface_property avl_mem PORT_NAME_MAP ""
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set_interface_property avl_mem CMSIS_SVD_VARIABLES ""
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set_interface_property avl_mem SVD_ADDRESS_GROUP ""
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add_interface_port avl_mem avl_mem_write write Input 1
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add_interface_port avl_mem avl_mem_burstcount burstcount Input 7
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add_interface_port avl_mem avl_mem_waitrequest waitrequest Output 1
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add_interface_port avl_mem avl_mem_read read Input 1
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add_interface_port avl_mem avl_mem_addr address Input ADDR_WIDTH
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add_interface_port avl_mem avl_mem_wrdata writedata Input 32
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add_interface_port avl_mem avl_mem_rddata readdata Output 32
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add_interface_port avl_mem avl_mem_rddata_valid readdatavalid Output 1
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add_interface_port avl_mem avl_mem_byteenable byteenable Input 4
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#
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# connection point interrupt_sender
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#
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add_interface interrupt_sender interrupt end
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set_interface_property interrupt_sender associatedAddressablePoint avl_csr
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set_interface_property interrupt_sender associatedClock clock_sink
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set_interface_property interrupt_sender associatedReset reset
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set_interface_property interrupt_sender bridgedReceiverOffset ""
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set_interface_property interrupt_sender bridgesToReceiver ""
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set_interface_property interrupt_sender ENABLED true
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set_interface_property interrupt_sender EXPORT_OF ""
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set_interface_property interrupt_sender PORT_NAME_MAP ""
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set_interface_property interrupt_sender CMSIS_SVD_VARIABLES ""
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set_interface_property interrupt_sender SVD_ADDRESS_GROUP ""
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add_interface_port interrupt_sender irq irq Output 1
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proc proc_get_derive_addr_width {flash_type} {
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switch $flash_type {
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"EPCS16" - "EPCQ16" {
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return 19
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}
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"EPCS64" - "EPCQ64" {
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return 21
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}
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"EPCS128" - "EPCQ128" {
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return 22
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}
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"EPCQ32" {
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return 20
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}
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"EPCQ256" - "EPCQL256" {
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return 23
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}
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"EPCQ512" - "EPCQL512" {
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return 24
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}
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"EPCQL1024" {
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return 25
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}
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default {
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# Should never enter this function
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send_message error "$flash_type is not a valid flash type"
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}
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}
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}
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set all_supported_SPI_list {"EPCS16" "EPCS64" "EPCS128" "EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" \
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"EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024"}
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# SPI device selection
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add_parameter FLASH_TYPE STRING "EPCQ16"
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set_parameter_property FLASH_TYPE DISPLAY_NAME "Configuration device type"
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set_parameter_property FLASH_TYPE ALLOWED_RANGES $all_supported_SPI_list
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set_parameter_property FLASH_TYPE DESCRIPTION "Select targeted EPCS/EPCQ devices"
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set_parameter_property FLASH_TYPE AFFECTS_GENERATION true
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set_parameter_property FLASH_TYPE VISIBLE true
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set_parameter_property FLASH_TYPE DERIVED false
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add_parameter IO_MODE STRING "STANDARD"
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set_parameter_property IO_MODE DISPLAY_NAME "Choose I/O mode"
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set_parameter_property IO_MODE ALLOWED_RANGES {"STANDARD" "QUAD"}
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set_parameter_property IO_MODE DESCRIPTION "Select extended data width when Fast Read operation is enabled"
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add_parameter CHIP_SELS INTEGER "1"
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set_parameter_property CHIP_SELS DISPLAY_NAME "Number of Chip Selects used"
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set_parameter_property CHIP_SELS ALLOWED_RANGES {1 2 3}
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set_parameter_property CHIP_SELS DESCRIPTION "Number of EPCQ(L) devices that are attached and need a CHIPSEL"
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set_parameter_property CHIP_SELS HDL_PARAMETER true
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set_parameter_property CHIP_SELS AFFECTS_GENERATION true
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#
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# Add instance
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#
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proc add_topwrapper_fileset_proc {altera_epcq_controller} {
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# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
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set supported_4byte_addr {"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
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set DDASI [ get_parameter_value DDASI ]
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set DEVICE_FAMILY [ get_parameter_value DEVICE_FAMILY ]
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set FLASH_TYPE [ get_parameter_value FLASH_TYPE ]
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set ADDR_WIDTH [ get_parameter_value ADDR_WIDTH ]
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set is_4byte_addr_support "false"
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# check whether devices supporting multiple flash - only for Arria 10
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if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
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set MULTICHIP 1
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} else {
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set MULTICHIP 0
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}
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if { $DDASI eq "1" } {
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set DDASI_ON 1
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} else {
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set DDASI_ON 0
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}
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if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
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set ENABLE_SID 1
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} else {
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set ENABLE_SID 0
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}
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if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
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set ENABLE_BULK_ERASE 0
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} else {
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set ENABLE_BULK_ERASE 1
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}
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# check whether SPI device support 4-byte addressing
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foreach re_spi_1 $supported_4byte_addr {
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if {$re_spi_1 eq $FLASH_TYPE} {
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set is_4byte_addr_support "true"
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break;
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}
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}
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if {$is_4byte_addr_support eq "true"} {
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set ENABLE_4BYTE_ADDR_CODE 1
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} else {
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set ENABLE_4BYTE_ADDR_CODE 0
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}
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# ---------------------------------
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# Terp for top level wrapper
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# ---------------------------------
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#Do Terp
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set template_file [ file join "./" "altera_epcq_controller_wrapper.sv.terp" ]
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set template [ read [ open $template_file r ] ]
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if {$DDASI_ON} {
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set params(DDASI_ON) "`define DDASI_ON"
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} else {
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set params(DDASI_ON) ""
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}
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if {$MULTICHIP} {
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set params(MULTICHIP) "`define MULTICHIP"
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} else {
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set params(MULTICHIP) ""
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}
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if {$ENABLE_SID} {
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set params(SID_EN) "`define ENABLE_SID"
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} else {
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set params(SID_EN) ""
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}
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if {$ENABLE_BULK_ERASE} {
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set params(BULK_ERASE_EN) "`define ENABLE_BULK_ERASE"
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} else {
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set params(BULK_ERASE_EN) ""
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}
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if {$ENABLE_4BYTE_ADDR_CODE} {
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set params(4BYTE_ADDR_EN) "`define ENABLE_4BYTE_ADDR_CODE"
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} else {
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set params(4BYTE_ADDR_EN) ""
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}
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set result [ altera_terp $template params ]
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#Add top wrapper file
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add_fileset_file ./altera_epcq_controller_wrapper.sv SYSTEM_VERILOG TEXT $result
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}
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# This proc is called by elaboration proc to set embeddedsw C Macros assignments
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# used by downstream tools
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proc set_cmacros {is_qspi flash_type} {
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if {$is_qspi eq "true"} {
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set_module_assignment embeddedsw.CMacro.IS_EPCS 0
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} else {
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set_module_assignment embeddedsw.CMacro.IS_EPCS 1
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}
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#string name of flash
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set_module_assignment embeddedsw.CMacro.FLASH_TYPE $flash_type
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#page size in bytes
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set_module_assignment embeddedsw.CMacro.PAGE_SIZE 256
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#sector and subsector size in bytes
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set_module_assignment embeddedsw.CMacro.SUBSECTOR_SIZE 4096
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set_module_assignment embeddedsw.CMacro.SECTOR_SIZE 65536
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#set number of sectors
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switch $flash_type {
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"EPCS16" - "EPCQ16" {
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set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 32
|
|
}
|
|
"EPCQ32" {
|
|
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 64
|
|
}
|
|
"EPCS64" - "EPCQ64" {
|
|
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 128
|
|
}
|
|
"EPCS128" - "EPCQ128" {
|
|
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 256
|
|
}
|
|
"EPCQ256" - "EPCQL256" {
|
|
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 512
|
|
}
|
|
"EPCQ512" - "EPCQL512" {
|
|
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 1024
|
|
}
|
|
"EPCQL1024" {
|
|
set_module_assignment embeddedsw.CMacro.NUMBER_OF_SECTORS 2048
|
|
}
|
|
default {
|
|
# Should never enter this function
|
|
send_message error "$flash_type is not a valid flash type"
|
|
}
|
|
}
|
|
}
|
|
|
|
proc elaboration {} {
|
|
# QSPI that supported for 4-byte addressing - en4b_addr, ex4b_addr
|
|
set supported_4byte_addr {"EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" "N25Q512"}
|
|
set DDASI_ON [ get_parameter_value DDASI ]
|
|
set FLASH_TYPE [ get_parameter_value FLASH_TYPE ]
|
|
set IO_MODE [ get_parameter_value IO_MODE ]
|
|
set DEVICE_FAMILY [ get_parameter_value DEVICE_FAMILY ]
|
|
set ASI_WIDTH [ get_parameter_value ASI_WIDTH ]
|
|
set CS_WIDTH [ get_parameter_value CS_WIDTH ]
|
|
set ASMI_ADDR_WIDTH [ get_parameter_value ASMI_ADDR_WIDTH ]
|
|
set CHIP_SELS [ get_parameter_value CHIP_SELS]
|
|
set temp_addr_width [ proc_get_derive_addr_width [ get_parameter_value FLASH_TYPE ] ]
|
|
set clkFreq [ get_parameter_value clkFreq ]
|
|
set is_4byte_addr_support "false"
|
|
set is_qspi "false"
|
|
|
|
# we're not using slow and expensive EPCS flash, thus higher frequency allowed
|
|
if { $clkFreq > 50000000 } {
|
|
send_message error "The maximum input clock frequency for Altera Serial Flash controller is 25Mhz."
|
|
}
|
|
|
|
# check whether SPI device support 4-byte addressing
|
|
foreach re_spi_1 $supported_4byte_addr {
|
|
if {$re_spi_1 eq $FLASH_TYPE} {
|
|
set is_4byte_addr_support "true"
|
|
break;
|
|
}
|
|
}
|
|
|
|
if {$is_4byte_addr_support eq "true"} {
|
|
set_parameter_value ENABLE_4BYTE_ADDR "1"
|
|
set_parameter_value ASMI_ADDR_WIDTH 32
|
|
} else {
|
|
set_parameter_value ENABLE_4BYTE_ADDR "0"
|
|
set_parameter_value ASMI_ADDR_WIDTH 24
|
|
}
|
|
|
|
# check whether devices supporting multiple flash - only for Arria 10
|
|
if {[check_device_family_equivalence $DEVICE_FAMILY "Arria 10"]} {
|
|
set is_multi_flash_support "true"
|
|
if {$CHIP_SELS eq 3 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 2]}
|
|
if {$CHIP_SELS eq 2 } {set_parameter_value ADDR_WIDTH [ expr $temp_addr_width + 1]}
|
|
if {$CHIP_SELS eq 1 } {set_parameter_value ADDR_WIDTH $temp_addr_width }
|
|
} else {
|
|
set is_multi_flash_support "false"
|
|
set_parameter_value ADDR_WIDTH $temp_addr_width
|
|
}
|
|
|
|
|
|
set_instance_parameter_value altera_epcq_controller_core DDASI $DDASI_ON
|
|
set_instance_parameter_value altera_epcq_controller_core FLASH_TYPE $FLASH_TYPE
|
|
set_instance_parameter_value altera_epcq_controller_core IO_MODE $IO_MODE
|
|
set_instance_parameter_value altera_epcq_controller_core ASI_WIDTH $ASI_WIDTH
|
|
set_instance_parameter_value altera_epcq_controller_core CS_WIDTH $CS_WIDTH
|
|
set_instance_parameter_value altera_epcq_controller_core CHIP_SELS $CHIP_SELS
|
|
set_instance_parameter_value altera_epcq_controller_core ASMI_ADDR_WIDTH [ get_parameter_value ASMI_ADDR_WIDTH ]
|
|
set_instance_parameter_value altera_epcq_controller_core ADDR_WIDTH [ get_parameter_value ADDR_WIDTH ]
|
|
set_instance_parameter_value altera_epcq_controller_core ENABLE_4BYTE_ADDR [ get_parameter_value ENABLE_4BYTE_ADDR ]
|
|
|
|
set QSPI_list {"EPCQ16" "EPCQ32" "EPCQ64" "EPCQ128" "EPCQ256" "EPCQ512" "EPCQL256" "EPCQL512" "EPCQL1024" \
|
|
"N25Q512" "S25FL127S"}
|
|
|
|
# devices that supported QSPI - Quad/Dual data width, asmi_dataout, asmi_sdoin, asmi_dataoe
|
|
set supported_QSPI_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V"}
|
|
|
|
# devices that supported simulation
|
|
set supported_sim_devices_list {"Arria 10" "Cyclone V" "Arria V GZ" "Arria V" "Stratix V" "MAX 10 FPGA"}
|
|
|
|
# check whether is QSPI devices
|
|
foreach re_spi_0 $QSPI_list {
|
|
if {$re_spi_0 eq $FLASH_TYPE} {
|
|
set is_qspi "true"
|
|
break;
|
|
}
|
|
}
|
|
|
|
if {[check_device_family_equivalence $DEVICE_FAMILY $supported_QSPI_devices_list]} {
|
|
set is_qspi_devices_list "true"
|
|
} else {
|
|
set is_qspi_devices_list "false"
|
|
}
|
|
|
|
if {[check_device_family_equivalence $DEVICE_FAMILY $supported_sim_devices_list]} {
|
|
set is_sim_devices_list "true"
|
|
} else {
|
|
set is_sim_devices_list "false"
|
|
}
|
|
|
|
if {$is_qspi_devices_list eq "true" && $is_qspi eq "true"} {
|
|
set_parameter_property IO_MODE ENABLED true
|
|
set_instance_parameter_value altera_asmi_parallel DATA_WIDTH $IO_MODE
|
|
set_parameter_value ASI_WIDTH 4
|
|
} else {
|
|
set_parameter_property IO_MODE ENABLED false
|
|
set_parameter_value ASI_WIDTH 1
|
|
}
|
|
|
|
if { $FLASH_TYPE eq "EPCQL512" || $FLASH_TYPE eq "EPCQL1024" } {
|
|
set_instance_parameter_value altera_asmi_parallel gui_bulk_erase false
|
|
set ENABLE_BULK_ERASE 0
|
|
} else {
|
|
set_instance_parameter_value altera_asmi_parallel gui_bulk_erase true
|
|
set ENABLE_BULK_ERASE 1
|
|
}
|
|
|
|
if { $is_multi_flash_support eq "true"} {
|
|
set_parameter_value CS_WIDTH 3
|
|
set_parameter_property CHIP_SELS ENABLED true
|
|
} else {
|
|
set_parameter_value CS_WIDTH 1
|
|
set_parameter_property CHIP_SELS ENABLED false
|
|
}
|
|
|
|
set_instance_parameter_value altera_asmi_parallel EPCS_TYPE $FLASH_TYPE
|
|
set_instance_parameter_value altera_asmi_parallel gui_fast_read true
|
|
set_instance_parameter_value altera_asmi_parallel gui_page_write true
|
|
|
|
if { $FLASH_TYPE eq "EPCS16" || $FLASH_TYPE eq "EPCS64" } {
|
|
set_instance_parameter_value altera_asmi_parallel gui_read_sid true
|
|
} else {
|
|
set_instance_parameter_value altera_asmi_parallel gui_read_sid false
|
|
}
|
|
|
|
set_instance_parameter_value altera_asmi_parallel gui_read_rdid true
|
|
set_instance_parameter_value altera_asmi_parallel gui_read_status true
|
|
set_instance_parameter_value altera_asmi_parallel gui_sector_erase true
|
|
set_instance_parameter_value altera_asmi_parallel gui_sector_protect true
|
|
set_instance_parameter_value altera_asmi_parallel gui_wren true
|
|
set_instance_parameter_value altera_asmi_parallel gui_write true
|
|
set_instance_parameter_value altera_asmi_parallel gui_read_dummyclk true
|
|
set_instance_parameter_value altera_asmi_parallel PAGE_SIZE 256
|
|
set_instance_parameter_value altera_asmi_parallel gui_use_asmiblock $DDASI_ON
|
|
|
|
if {$is_sim_devices_list eq "true"} {
|
|
set_instance_parameter_value altera_asmi_parallel ENABLE_SIM true
|
|
} else {
|
|
set_instance_parameter_value altera_asmi_parallel ENABLE_SIM false
|
|
}
|
|
|
|
set_cmacros $is_qspi $FLASH_TYPE
|
|
}
|
|
|
|
# add ASMI PARALLEL
|
|
add_hdl_instance altera_asmi_parallel altera_asmi_parallel
|
|
|
|
# add EPCQ CONTROLLER
|
|
add_hdl_instance altera_epcq_controller_core altera_epcq_controller_core
|
|
|
|
# +-------------------------------------
|
|
# | Add settings needed by Nios tools
|
|
# +-------------------------------------
|
|
# Tells us component is a flash
|
|
set_module_assignment embeddedsw.memoryInfo.IS_FLASH 1
|
|
|
|
# interface assignments for embedded software
|
|
set_interface_assignment avl_mem embeddedsw.configuration.isFlash 1
|
|
set_interface_assignment avl_mem embeddedsw.configuration.isMemoryDevice 1
|
|
set_interface_assignment avl_mem embeddedsw.configuration.isNonVolatileStorage 1
|
|
set_interface_assignment avl_mem embeddedsw.configuration.isPrintableDevice 0
|
|
|
|
# These assignments tells tools to create byte-addressed .hex files only
|
|
set_module_assignment embeddedsw.memoryInfo.GENERATE_HEX 1
|
|
set_module_assignment embeddedsw.memoryInfo.USE_BYTE_ADDRESSING_FOR_HEX 1
|
|
set_module_assignment embeddedsw.memoryInfo.GENERATE_DAT_SYM 0
|
|
set_module_assignment embeddedsw.memoryInfo.GENERATE_FLASH 0
|
|
|
|
# Width of memory
|
|
set_module_assignment embeddedsw.memoryInfo.MEM_INIT_DATA_WIDTH 32
|
|
|
|
# Output directories for programming files
|
|
#set_module_assignment embeddedsw.memoryInfo.DAT_SYM_INSTALL_DIR {SIM_DIR}
|
|
#set_module_assignment embeddedsw.memoryInfo.FLASH_INSTALL_DIR {APP_DIR}
|
|
set_module_assignment embeddedsw.memoryInfo.HEX_INSTALL_DIR {QPF_DIR}
|
|
|
|
# Module assignments related to names of simulation files
|
|
#set_module_assignment postgeneration.simulation.init_file.param_name {INIT_FILENAME}
|
|
#set_module_assignment postgeneration.simulation.init_file.type {MEM_INIT}
|
|
|
|
# +-------------------------------------
|
|
# | Add settings needed by DTG tools
|
|
# +-------------------------------------
|
|
# add device tree properties
|
|
set_module_assignment embeddedsw.dts.vendor "altr"
|
|
set_module_assignment embeddedsw.dts.name "epcq"
|
|
set_module_assignment embeddedsw.dts.group "epcq"
|
|
set_module_assignment embeddedsw.dts.compatible "altr,epcq-1.0"
|
|
|
|
## Add documentation links for user guide and/or release notes
|
|
add_documentation_link "User Guide" https://documentation.altera.com/#/link/sfo1400787952932/iga1431459459085
|
|
add_documentation_link "Release Notes" https://documentation.altera.com/#/link/hco1421698042087/hco1421697689300
|