mirror of https://github.com/marqs85/ossc.git
261 lines
9.9 KiB
C
261 lines
9.9 KiB
C
/******************************************************************************
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* *
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* License Agreement *
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* *
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* Copyright (c) 2014 Altera Corporation, San Jose, California, USA. *
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* All rights reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included in *
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* all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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* This agreement shall be governed in all respects by the laws of the State *
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* of California and by the laws of the United States of America. *
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* *
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******************************************************************************/
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#ifndef __ALTERA_EPCQ_CONTROLLER_REGS_H__
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#define __ALTERA_EPCQ_CONTROLLER_REGS_H__
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#include <io.h>
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/*
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* EPCQ_RD_STATUS register offset
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*
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* The EPCQ_RD_STATUS register contains information from the read status
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* register operation. A full description of the register can be found in the
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* data sheet,
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*
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*/
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#define ALTERA_EPCQ_CONTROLLER_STATUS_REG (0x0)
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/*
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* EPCQ_RD_STATUS register access macros
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*/
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#define IOADDR_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
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__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
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#define IORD_ALTERA_EPCQ_CONTROLLER_STATUS(base) \
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IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG)
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#define IOWR_ALTERA_EPCQ_CONTROLLER_STATUS(base, data) \
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IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_STATUS_REG, data)
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/*
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* EPCQ_RD_STATUS register description macros
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*/
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/** Write in progress bit */
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#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_MASK (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_AVAILABLE (0x00000000)
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#define ALTERA_EPCQ_CONTROLLER_STATUS_WIP_BUSY (0x00000001)
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/** When to time out a poll of the write in progress bit */
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/* 0.7 sec time out */
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#define ALTERA_EPCQ_CONTROLLER_1US_TIMEOUT_VALUE 700000
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/*
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* EPCQ_RD_SID register offset
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*
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* The EPCQ_RD_SID register contains the information from the read silicon ID
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* operation and can be used to determine what type of EPCS device we have.
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* Only support in EPCS16 and EPCS64.
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*
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* This register is valid only if the device is an EPCS.
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*
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*/
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#define ALTERA_EPCQ_CONTROLLER_SID_REG (0x4)
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/*
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* EPCQ_RD_SID register access macros
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*/
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#define IOADDR_ALTERA_EPCQ_CONTROLLER_SID(base) \
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__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
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#define IORD_ALTERA_EPCQ_CONTROLLER_SID(base) \
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IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG)
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#define IOWR_ALTERA_EPCQ_CONTROLLER_SID(base, data) \
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IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_SID_REG, data)
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/*
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* EPCQ_RD_SID register description macros
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*
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* Specific device values obtained from Table 14 of:
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* "Serial Configuration (EPCS) Devices Datasheet"
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*/
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#define ALTERA_EPCQ_CONTROLLER_SID_MASK (0x000000FF)
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#define ALTERA_EPCQ_CONTROLLER_SID_EPCS16 (0x00000014)
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#define ALTERA_EPCQ_CONTROLLER_SID_EPCS64 (0x00000016)
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#define ALTERA_EPCQ_CONTROLLER_SID_EPCS128 (0x00000018)
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/*
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* EPCQ_RD_RDID register offset
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*
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* The EPCQ_RD_RDID register contains the information from the read memory
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* capacity operation and can be used to determine what type of EPCQ device
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* we have.
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*
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* This register is only valid if the device is an EPCQ.
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*
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*/
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#define ALTERA_EPCQ_CONTROLLER_RDID_REG (0x8)
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/*
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* EPCQ_RD_RDID register access macros
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*/
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#define IOADDR_ALTERA_EPCQ_CONTROLLER_RDID(base) \
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__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
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#define IORD_ALTERA_EPCQ_CONTROLLER_RDID(base) \
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IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG)
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#define IOWR_ALTERA_EPCQ_CONTROLLER_RDID(base, data) \
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IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_RDID_REG, data)
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/*
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* EPCQ_RD_RDID register description macros
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*
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* Specific device values obtained from Table 28 of:
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* "Quad-Serial Configuration (EPCQ (www.altera.com/literature/hb/cfg/cfg_cf52012.pdf))
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* Devices Datasheet"
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*/
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#define ALTERA_EPCQ_CONTROLLER_RDID_MASK (0x000000FF)
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#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ16 (0x00000015)
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#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ32 (0x00000016)
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#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ64 (0x00000017)
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#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ128 (0x00000018)
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#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ256 (0x00000019)
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#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ512 (0x00000020)
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#define ALTERA_EPCQ_CONTROLLER_RDID_EPCQ1024 (0x00000021)
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/*
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* EPCQ_MEM_OP register offset
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*
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* The EPCQ_MEM_OP register is used to do memory protect and erase operations
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*
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*/
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#define ALTERA_EPCQ_CONTROLLER_MEM_OP_REG (0xC)
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/*
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* EPCQ_MEM_OP register access macros
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*/
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#define IOADDR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
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__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
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#define IORD_ALTERA_EPCQ_CONTROLLER_MEM_OP(base) \
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IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG)
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#define IOWR_ALTERA_EPCQ_CONTROLLER_MEM_OP(base, data) \
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IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_MEM_OP_REG, data)
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/*
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* EPCQ_MEM_OP register description macros
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*/
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#define ALTERA_EPCQ_CONTROLLER_MEM_OP_CMD_MASK (0x00000003)
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#define ALTERA_EPCQ_CONTROLLER_MEM_OP_BULK_ERASE_CMD (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_ERASE_CMD (0x00000002)
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#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_PROTECT_CMD (0x00000003)
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/** see datasheet for sector values */
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#define ALTERA_EPCQ_CONTROLLER_MEM_OP_SECTOR_VALUE_MASK (0x00FFFF00)
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/*
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* EPCQ_ISR register offset
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*
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* The EPCQ_ISR register is used to determine whether an invalid write or erase
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* operation triggered an interrupt
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*
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*/
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#define ALTERA_EPCQ_CONTROLLER_ISR_REG (0x10)
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/*
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* EPCQ_ISR register access macros
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*/
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#define IOADDR_ALTERA_EPCQ_CONTROLLER_ISR(base) \
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__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
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#define IORD_ALTERA_EPCQ_CONTROLLER_ISR(base) \
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IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG)
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#define IOWR_ALTERA_EPCQ_CONTROLLER_ISR(base, data) \
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IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_ISR_REG, data)
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/*
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* EPCQ_ISR register description macros
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*/
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#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_MASK (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_ERASE_ACTIVE (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_MASK (0x00000002)
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#define ALTERA_EPCQ_CONTROLLER_ISR_ILLEGAL_WRITE_ACTIVE (0x00000002)
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/*
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* EPCQ_IMR register offset
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*
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* The EPCQ_IMR register is used to mask the invalid erase or the invalid write
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* interrupts.
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*
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*/
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#define ALTERA_EPCQ_CONTROLLER_IMR_REG (0x14)
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/*
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* EPCQ_IMR register access macros
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*/
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#define IOADDR_ALTERA_EPCQ_CONTROLLER_IMR(base) \
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__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
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#define IORD_ALTERA_EPCQ_CONTROLLER_IMR(base) \
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IORD_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG)
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#define IOWR_ALTERA_EPCQ_CONTROLLER_IMR(base, data) \
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IOWR_32DIRECT(base, ALTERA_EPCQ_CONTROLLER_IMR_REG, data)
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/*
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* EPCQ_IMR register description macros
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*/
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#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_MASK (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_ERASE_ENABLED (0x00000001)
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#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_MASK (0x00000002)
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#define ALTERA_EPCQ_CONTROLLER_IMR_ILLEGAL_WRITE_ENABLED (0x00000002)
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/*
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* EPCQ_CHIP_SELECT register offset
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*
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* The EPCQ_CHIP_SELECT register is used to issue chip select
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*/
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#define ALTERA_EPCQ_CHIP_SELECT_REG (0x18)
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/*
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* EPCQ_CHIP_SELECT register access macros
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*/
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#define IOADDR_ALTERA_EPCQ_CHIP_SELECT(base) \
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__IO_CALC_ADDRESS_DYNAMIC(base, ALTERA_EPCQ_CHIP_SELECT_REG)
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#define IOWR_ALTERA_EPCQ_CHIP_SELECT(base, data) \
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IOWR_32DIRECT(base, ALTERA_EPCQ_CHIP_SELECT_REG, data)
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/*
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* EPCQ_CHIP_SELECT register description macros
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*/
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#define ALTERA_EPCQ_CHIP1_SELECT (0x00000001)
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#define ALTERA_EPCQ_CHIP2_SELECT (0x00000002)
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#define ALTERA_EPCQ_CHIP3_SELECT (0x00000003)
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#endif /* __ALTERA_EPCQ_CONTROLLER_REGS_H__ */
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