mirror of https://github.com/marqs85/ossc.git
80 lines
2.7 KiB
VHDL
80 lines
2.7 KiB
VHDL
-- (C) 2001-2015 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License Subscription
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-- Agreement, Altera MegaCore Function License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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----------------------------------------------------------------------------------------
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-- This generates the necessary 16-CRC for Command and Response
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-- Implementation: serial input/parallel output
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-- When input stream ends, the crcout output is the CRC checksum for them
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--
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-- NOTES/REVISIONS:
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----------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Altera_UP_SD_CRC16_Generator is
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port
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(
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i_clock : in std_logic;
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i_enable : in std_logic;
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i_reset_n : in std_logic;
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i_sync_reset : in std_logic;
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i_shift : in std_logic;
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i_datain : in std_logic;
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o_dataout : out std_logic;
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o_crcout : out std_logic_vector(15 downto 0)
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);
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end entity;
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architecture rtl of Altera_UP_SD_CRC16_Generator is
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-- Local wires
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-- REGISTERED
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signal shift_register : std_logic_vector(15 downto 0);
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begin
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process (i_clock, i_reset_n)
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begin
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if (i_reset_n = '0') then
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shift_register <= (OTHERS => '0');
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else
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if (rising_edge(i_clock)) then
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if (i_sync_reset = '1') then
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shift_register <= (OTHERS => '0');
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elsif (i_enable = '1') then
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if (i_shift = '0') then
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shift_register(0) <= i_datain XOR shift_register(15);
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shift_register(4 downto 1) <= shift_register(3 downto 0);
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shift_register(5) <= shift_register(4) XOR i_datain XOR shift_register(15);
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shift_register(11 downto 6) <= shift_register(10 downto 5);
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shift_register(12) <= shift_register(11) XOR i_datain XOR shift_register(15);
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shift_register(15 downto 13) <= shift_register(14 downto 12);
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else -- shift CRC out (no more calculation now)
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shift_register(15 downto 1) <= shift_register(14 downto 0);
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shift_register(0) <= '0';
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end if;
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end if;
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end if;
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end if;
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end process;
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o_dataout <= shift_register(15);
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o_crcout <= shift_register;
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end rtl;
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