mirror of https://github.com/marqs85/ossc.git
519 lines
20 KiB
VHDL
519 lines
20 KiB
VHDL
-- (C) 2001-2015 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License Subscription
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-- Agreement, Altera MegaCore Function License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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-------------------------------------------------------------------------------------
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-- This module is an interface to the Secure Data Card. This module is intended to be
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-- used with the DE2 board.
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--
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-- This version of the interface supports only a 1-bit serial data transfer. This
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-- allows the interface to support a MultiMedia card as well.
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--
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-- NOTES/REVISIONS:
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-------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Altera_UP_SD_Card_Interface is
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port
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(
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i_clock : in std_logic;
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i_reset_n : in std_logic;
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-- Command interface
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b_SD_cmd : inout std_logic;
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b_SD_dat : inout std_logic;
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b_SD_dat3 : inout std_logic;
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i_command_ID : in std_logic_vector(5 downto 0);
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i_argument : in std_logic_vector(31 downto 0);
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i_user_command_ready : in std_logic;
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o_SD_clock : out std_logic;
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o_card_connected : out std_logic;
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o_command_completed : out std_logic;
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o_command_valid : out std_logic;
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o_command_timed_out : out std_logic;
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o_command_crc_failed : out std_logic;
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-- Buffer access
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i_buffer_enable : in std_logic;
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i_buffer_address : in std_logic_vector(7 downto 0);
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i_buffer_write : in std_logic;
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i_buffer_data_in : in std_logic_vector(15 downto 0);
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o_buffer_data_out : out std_logic_vector(15 downto 0);
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-- Show SD Card registers as outputs
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o_SD_REG_card_identification_number : out std_logic_vector(127 downto 0);
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o_SD_REG_relative_card_address : out std_logic_vector(15 downto 0);
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o_SD_REG_operating_conditions_register : out std_logic_vector(31 downto 0);
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o_SD_REG_card_specific_data : out std_logic_vector(127 downto 0);
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o_SD_REG_status_register : out std_logic_vector(31 downto 0);
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o_SD_REG_response_R1 : out std_logic_vector(31 downto 0);
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o_SD_REG_status_register_valid : out std_logic
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);
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end entity;
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architecture rtl of Altera_UP_SD_Card_Interface is
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component Altera_UP_SD_Card_Clock
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port
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(
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i_clock : in std_logic;
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i_reset_n : in std_logic;
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i_enable : in std_logic;
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i_mode : in std_logic; -- 0 for card identification mode, 1 for data transfer mode.
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o_SD_clock : out std_logic;
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o_clock_mode : out std_logic;
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o_trigger_receive : out std_logic;
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o_trigger_send : out std_logic
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);
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end component;
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component Altera_UP_SD_CRC7_Generator
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port
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(
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i_clock : in std_logic;
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i_enable : in std_logic;
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i_reset_n : in std_logic;
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i_shift : in std_logic;
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i_datain : in std_logic;
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o_dataout : out std_logic;
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o_crcout : out std_logic_vector(6 downto 0)
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);
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end component;
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component Altera_UP_SD_CRC16_Generator
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port
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(
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i_clock : in std_logic;
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i_enable : in std_logic;
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i_reset_n : in std_logic;
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i_shift : in std_logic;
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i_datain : in std_logic;
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o_dataout : out std_logic;
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o_crcout : out std_logic_vector(15 downto 0)
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);
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end component;
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component Altera_UP_SD_Signal_Trigger
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port
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(
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i_clock : in std_logic;
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i_reset_n : in std_logic;
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i_signal : in std_logic;
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o_trigger : out std_logic
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);
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end component;
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component Altera_UP_SD_Card_48_bit_Command_Generator
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generic (
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-- Basic commands
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COMMAND_0_GO_IDLE : STD_LOGIC_VECTOR(5 downto 0) := "000000";
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COMMAND_2_ALL_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "000010";
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COMMAND_3_SEND_RCA : STD_LOGIC_VECTOR(5 downto 0) := "000011";
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COMMAND_4_SET_DSR : STD_LOGIC_VECTOR(5 downto 0) := "000100";
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COMMAND_6_SWITCH_FUNCTION : STD_LOGIC_VECTOR(5 downto 0) := "000110";
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COMMAND_7_SELECT_CARD : STD_LOGIC_VECTOR(5 downto 0) := "000111";
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COMMAND_9_SEND_CSD : STD_LOGIC_VECTOR(5 downto 0) := "001001";
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COMMAND_10_SEND_CID : STD_LOGIC_VECTOR(5 downto 0) := "001010";
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COMMAND_12_STOP_TRANSMISSION : STD_LOGIC_VECTOR(5 downto 0) := "001100";
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COMMAND_13_SEND_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
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COMMAND_15_GO_INACTIVE : STD_LOGIC_VECTOR(5 downto 0) := "001111";
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-- Block oriented read/write/lock commands
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COMMAND_16_SET_BLOCK_LENGTH : STD_LOGIC_VECTOR(5 downto 0) := "010000";
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-- Block oriented read commands
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COMMAND_17_READ_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "010001";
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COMMAND_18_READ_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010010";
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-- Block oriented write commands
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COMMAND_24_WRITE_BLOCK : STD_LOGIC_VECTOR(5 downto 0) := "011000";
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COMMAND_25_WRITE_MULTIPLE_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "011001";
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COMMAND_27_PROGRAM_CSD : STD_LOGIC_VECTOR(5 downto 0) := "011011";
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-- Block oriented write-protection commands
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COMMAND_28_SET_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011100";
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COMMAND_29_CLEAR_WRITE_PROTECT : STD_LOGIC_VECTOR(5 downto 0) := "011101";
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COMMAND_30_SEND_PROTECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "011110";
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-- Erase commands
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COMMAND_32_ERASE_BLOCK_START : STD_LOGIC_VECTOR(5 downto 0) := "100000";
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COMMAND_33_ERASE_BLOCK_END : STD_LOGIC_VECTOR(5 downto 0) := "100001";
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COMMAND_38_ERASE_SELECTED_GROUPS : STD_LOGIC_VECTOR(5 downto 0) := "100110";
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-- Block lock commands
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COMMAND_42_LOCK_UNLOCK : STD_LOGIC_VECTOR(5 downto 0) := "101010";
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-- Command Type Settings
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COMMAND_55_APP_CMD : STD_LOGIC_VECTOR(5 downto 0) := "110111";
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COMMAND_56_GEN_CMD : STD_LOGIC_VECTOR(5 downto 0) := "111000";
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-- Application Specific commands - must be preceeded with command 55.
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ACOMMAND_6_SET_BUS_WIDTH : STD_LOGIC_VECTOR(5 downto 0) := "000110";
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ACOMMAND_13_SD_STATUS : STD_LOGIC_VECTOR(5 downto 0) := "001101";
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ACOMMAND_22_SEND_NUM_WR_BLOCKS : STD_LOGIC_VECTOR(5 downto 0) := "010100";
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ACOMMAND_23_SET_BLK_ERASE_COUNT : STD_LOGIC_VECTOR(5 downto 0) := "010101";
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ACOMMAND_41_SEND_OP_CONDITION : STD_LOGIC_VECTOR(5 downto 0) := "101001";
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ACOMMAND_42_SET_CLR_CARD_DETECT : STD_LOGIC_VECTOR(5 downto 0) := "101010";
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ACOMMAND_51_SEND_SCR : STD_LOGIC_VECTOR(5 downto 0) := "110011";
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-- First custom_command
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FIRST_NON_PREDEFINED_COMMAND : STD_LOGIC_VECTOR(3 downto 0) := "1010"
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);
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port
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(
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i_clock : in std_logic;
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i_reset_n : in std_logic;
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i_message_bit_out : in std_logic;
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i_command_ID : in std_logic_vector(5 downto 0);
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i_argument : in std_logic_vector(31 downto 0);
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i_predefined_message : in std_logic_vector(3 downto 0);
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i_generate : in std_logic;
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i_DSR : in std_logic_vector(15 downto 0);
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i_OCR : in std_logic_vector(31 downto 0);
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i_RCA : in std_logic_vector(15 downto 0);
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o_dataout : out std_logic;
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o_message_done : out std_logic;
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o_valid : out std_logic;
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o_returning_ocr : out std_logic;
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o_returning_cid : out std_logic;
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o_returning_rca : out std_logic;
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o_returning_csd : out std_logic;
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o_returning_status : out std_logic;
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o_data_read : out std_logic;
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o_data_write : out std_logic;
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o_wait_cmd_busy : out std_logic;
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o_last_cmd_was_55 : out std_logic;
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o_response_type : out std_logic_vector(2 downto 0)
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);
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end component;
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component Altera_UP_SD_Card_Response_Receiver
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generic (
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TIMEOUT : std_logic_vector(7 downto 0) := "00111000";
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BUSY_WAIT : std_logic_vector(7 downto 0) := "00110000";
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PROCESSING_DELAY : std_logic_vector(7 downto 0) := "00001000"
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);
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port
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(
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i_clock : in std_logic;
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i_reset_n : in std_logic;
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i_begin : in std_logic;
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i_scan_pulse : in std_logic;
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i_datain : in std_logic;
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i_wait_cmd_busy : in std_logic;
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i_response_type : in std_logic_vector(2 downto 0);
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o_data : out std_logic_vector(127 downto 0);
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o_CRC_passed : out std_logic;
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o_timeout : out std_logic;
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o_done : out std_logic
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);
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end component;
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component Altera_UP_SD_Card_Control_FSM
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generic (
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PREDEFINED_COMMAND_GET_STATUS : STD_LOGIC_VECTOR(3 downto 0) := "1001"
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);
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port
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(
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-- Clock and Reset signals
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i_clock : in STD_LOGIC;
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i_reset_n : in STD_LOGIC;
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-- FSM Inputs
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i_user_command_ready : in std_logic;
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i_response_received : in STD_LOGIC;
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i_response_timed_out : in STD_LOGIC;
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i_response_crc_passed : in STD_LOGIC;
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i_command_sent : in STD_LOGIC;
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i_powerup_busy_n : in STD_LOGIC;
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i_clocking_pulse_enable : in std_logic;
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i_current_clock_mode : in std_logic;
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i_user_message_valid : in std_logic;
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i_last_cmd_was_55 : in std_logic;
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i_allow_partial_rw : in std_logic;
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-- FSM Outputs
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o_generate_command : out STD_LOGIC;
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o_predefined_command_ID : out STD_LOGIC_VECTOR(3 downto 0);
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o_receive_response : out STD_LOGIC;
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o_drive_CMD_line : out STD_LOGIC;
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o_SD_clock_mode : out STD_LOGIC; -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
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o_resetting : out std_logic;
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o_card_connected : out STD_LOGIC;
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o_command_completed : out std_logic;
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o_clear_response_register : out std_logic;
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o_enable_clock_generator : out std_logic
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);
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end component;
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component Altera_UP_SD_Card_Buffer
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generic (
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TIMEOUT : std_logic_vector(15 downto 0) := "1111111111111111";
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BUSY_WAIT : std_logic_vector(15 downto 0) := "0000001111110000"
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);
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port
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(
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i_clock : in std_logic;
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i_reset_n : in std_logic;
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-- 1 bit port to transmit and receive data on the data line.
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i_begin : in std_logic;
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i_sd_clock_pulse_trigger : in std_logic;
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i_transmit : in std_logic;
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i_1bit_data_in : in std_logic;
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o_1bit_data_out : out std_logic;
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o_operation_complete : out std_logic;
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o_crc_passed : out std_logic;
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o_timed_out : out std_logic;
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o_dat_direction : out std_logic; -- set to 1 to send data, set to 0 to receive it.
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-- 16 bit port to be accessed by a user circuit.
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i_enable_16bit_port : in std_logic;
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i_address_16bit_port : in std_logic_vector(7 downto 0);
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i_write_16bit : in std_logic;
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i_16bit_data_in : in std_logic_vector(15 downto 0);
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o_16bit_data_out : out std_logic_vector(15 downto 0)
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);
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end component;
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-- Local wires
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-- REGISTERED
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signal sd_mode : std_logic;
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-- SD Card Registers:
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signal SD_REG_card_identification_number : std_logic_vector(127 downto 0);
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signal SD_REG_response_R1 : std_logic_vector(31 downto 0);
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signal SD_REG_relative_card_address : std_logic_vector(15 downto 0);
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signal SD_REG_driver_stage_register : std_logic_vector(15 downto 0);
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signal SD_REG_card_specific_data : std_logic_vector(127 downto 0);
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signal SD_REG_operating_conditions_register : std_logic_vector(31 downto 0);
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signal SD_REG_status_register : std_logic_vector(31 downto 0);
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signal SD_REG_status_register_valid : std_logic;
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-- UNREGISTERED
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signal data_from_buffer : std_logic_vector(15 downto 0);
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signal clock_generator_mode, enable_generator, SD_clock, create_message : std_logic;
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signal send_next_bit, receive_next_bit : std_logic;
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signal timed_out, response_done, passed_crc, begin_reading_response, resetting : std_logic;
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signal returning_cid, returning_rca, returning_csd, returning_ocr : std_logic;
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signal response_type : std_logic_vector(2 downto 0);
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signal message_valid, messange_sent, data_to_CMD_line, CMD_tristate_buffer_enable, message_sent : std_logic;
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signal predef_message_ID : std_logic_vector(3 downto 0);
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signal receive_data_out : std_logic_vector(127 downto 0);
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signal data_line_done, data_line_crc, data_line_timeout, data_line_direction, data_line_out : std_logic;
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signal data_read, data_write, wait_cmd_busy, clear_response_register : std_logic;
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signal response_done_combined : std_logic;
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signal timeout_combined : std_logic;
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signal crc_combined, allow_partial_rw : std_logic;
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signal begin_data_line_operations, last_cmd_was_55, message_sent_trigger, returning_status : std_logic;
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signal data_line_sd_clock_pulse_trigger : std_logic;
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begin
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-- Glue logic
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SD_REG_driver_stage_register <= (OTHERS => '0');
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response_done_combined <= (response_done and (not data_read) and (not data_write)) or
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(response_done and (data_read or data_write) and data_line_done);
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timeout_combined <= (timed_out and (not data_read) and (not data_write)) or
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(timed_out and (data_read or data_write) and data_line_timeout);
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crc_combined <= (passed_crc and (not data_read) and (not data_write)) or
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(passed_crc and (data_read or data_write) and data_line_crc);
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begin_data_line_operations <= (data_read and message_sent) or (data_write and response_done);
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-- Partial read and write are only allowed when both bit 79 (partial read allowed) is high and
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-- bit 21 (partial write allowed) is high.
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allow_partial_rw <= SD_REG_card_specific_data(79) and SD_REG_card_specific_data(21);
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-- SD Card control registers
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control_regs: process (i_clock, i_reset_n)
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begin
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if (i_reset_n = '0') then
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SD_REG_operating_conditions_register <= (OTHERS => '0');
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SD_REG_card_identification_number <= (OTHERS => '0');
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SD_REG_relative_card_address <= (OTHERS => '0');
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SD_REG_card_specific_data <= (OTHERS => '0');
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SD_REG_status_register <= (OTHERS => '0');
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SD_REG_response_R1 <= (OTHERS => '1');
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SD_REG_status_register_valid <= '0';
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elsif (rising_edge(i_clock)) then
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if ((response_type = "001") and (response_done = '1') and (returning_status = '0') and (clear_response_register = '0')) then
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SD_REG_response_R1 <= receive_data_out(31 downto 0);
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elsif (clear_response_register = '1') then
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SD_REG_response_R1 <= (OTHERS => '1');
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end if;
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if (resetting = '1') then
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SD_REG_operating_conditions_register <= (OTHERS => '0');
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elsif ((returning_ocr = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
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SD_REG_operating_conditions_register <= receive_data_out(31 downto 0);
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end if;
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if ((returning_cid = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
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SD_REG_card_identification_number <= receive_data_out;
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end if;
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if ((returning_rca = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
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SD_REG_relative_card_address <= receive_data_out(31 downto 16);
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end if;
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if ((returning_csd = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
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SD_REG_card_specific_data <= receive_data_out;
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end if;
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if (message_sent_trigger = '1') then
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SD_REG_status_register_valid <= '0';
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elsif ((returning_status = '1') and (passed_crc = '1') and (response_done = '1') and (timed_out = '0')) then
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SD_REG_status_register <= receive_data_out(31 downto 0);
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SD_REG_status_register_valid <= '1';
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end if;
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end if;
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end process;
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-- Instantiated components
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command_generator: Altera_UP_SD_Card_48_bit_Command_Generator PORT MAP
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(
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i_clock => i_clock,
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i_reset_n => i_reset_n,
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i_message_bit_out => send_next_bit,
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i_command_ID => i_command_ID,
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i_argument => i_argument,
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i_predefined_message => predef_message_ID,
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i_generate => create_message,
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i_DSR => SD_REG_driver_stage_register,
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i_OCR => SD_REG_operating_conditions_register,
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i_RCA => SD_REG_relative_card_address,
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o_dataout => data_to_CMD_line,
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o_message_done => message_sent,
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o_valid => message_valid,
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o_returning_ocr => returning_ocr,
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o_returning_cid => returning_cid,
|
|
o_returning_rca => returning_rca,
|
|
o_returning_csd => returning_csd,
|
|
o_returning_status => returning_status,
|
|
o_data_read => data_read,
|
|
o_data_write => data_write,
|
|
o_wait_cmd_busy => wait_cmd_busy,
|
|
o_last_cmd_was_55 => last_cmd_was_55,
|
|
o_response_type => response_type
|
|
);
|
|
|
|
response_receiver: Altera_UP_SD_Card_Response_Receiver PORT MAP
|
|
(
|
|
i_clock => i_clock,
|
|
i_reset_n => i_reset_n,
|
|
i_begin => begin_reading_response,
|
|
i_scan_pulse => receive_next_bit,
|
|
i_datain => b_SD_cmd,
|
|
i_response_type => response_type,
|
|
i_wait_cmd_busy => wait_cmd_busy,
|
|
o_data => receive_data_out,
|
|
o_CRC_passed => passed_crc,
|
|
o_timeout => timed_out,
|
|
o_done => response_done
|
|
);
|
|
|
|
control_FSM: Altera_UP_SD_Card_Control_FSM PORT MAP
|
|
(
|
|
-- Clock and Reset signals
|
|
i_clock => i_clock,
|
|
i_reset_n => i_reset_n,
|
|
|
|
-- FSM Inputs
|
|
i_user_command_ready => i_user_command_ready,
|
|
i_clocking_pulse_enable => receive_next_bit,
|
|
i_response_received => response_done_combined,
|
|
i_response_timed_out => timeout_combined,
|
|
i_response_crc_passed => crc_combined,
|
|
i_command_sent => message_sent,
|
|
i_powerup_busy_n => SD_REG_operating_conditions_register(31),
|
|
i_current_clock_mode => clock_generator_mode,
|
|
i_user_message_valid => message_valid,
|
|
i_last_cmd_was_55 => last_cmd_was_55,
|
|
i_allow_partial_rw => allow_partial_rw,
|
|
|
|
-- FSM Outputs
|
|
o_generate_command => create_message,
|
|
o_predefined_command_ID => predef_message_ID,
|
|
o_receive_response => begin_reading_response,
|
|
o_drive_CMD_line => CMD_tristate_buffer_enable,
|
|
o_SD_clock_mode => sd_mode, -- 0 means slow clock for card identification, 1 means fast clock for transfer mode.
|
|
o_card_connected => o_card_connected,
|
|
o_command_completed => o_command_completed,
|
|
o_resetting => resetting,
|
|
o_clear_response_register => clear_response_register,
|
|
o_enable_clock_generator => enable_generator
|
|
);
|
|
|
|
clock_generator: Altera_UP_SD_Card_Clock PORT MAP
|
|
(
|
|
i_clock => i_clock,
|
|
i_reset_n => i_reset_n,
|
|
i_mode => sd_mode,
|
|
i_enable => enable_generator,
|
|
o_SD_clock => SD_clock,
|
|
o_clock_mode => clock_generator_mode,
|
|
o_trigger_receive => receive_next_bit,
|
|
o_trigger_send => send_next_bit
|
|
);
|
|
|
|
SD_clock_pulse_trigger: Altera_UP_SD_Signal_Trigger PORT MAP
|
|
(
|
|
i_clock => i_clock,
|
|
i_reset_n => i_reset_n,
|
|
i_signal => message_sent,
|
|
o_trigger => message_sent_trigger
|
|
);
|
|
|
|
data_line: Altera_UP_SD_Card_Buffer
|
|
port map
|
|
(
|
|
i_clock => i_clock,
|
|
i_reset_n => i_reset_n,
|
|
|
|
-- 1 bit port to transmit and receive data on the data line.
|
|
i_begin => begin_data_line_operations,
|
|
i_sd_clock_pulse_trigger => data_line_sd_clock_pulse_trigger,
|
|
i_transmit => data_write,
|
|
i_1bit_data_in => b_SD_dat,
|
|
o_1bit_data_out => data_line_out,
|
|
o_operation_complete => data_line_done,
|
|
o_crc_passed => data_line_crc,
|
|
o_timed_out => data_line_timeout,
|
|
o_dat_direction => data_line_direction,
|
|
|
|
-- 16 bit port to be accessed by a user circuit.
|
|
i_enable_16bit_port => i_buffer_enable,
|
|
i_address_16bit_port => i_buffer_address,
|
|
i_write_16bit => i_buffer_write,
|
|
i_16bit_data_in => i_buffer_data_in,
|
|
o_16bit_data_out => data_from_buffer
|
|
);
|
|
data_line_sd_clock_pulse_trigger <= (data_write and send_next_bit) or ((not data_write) and receive_next_bit);
|
|
|
|
-- Buffer output registers.
|
|
buff_regs: process(i_clock, i_reset_n, data_from_buffer)
|
|
begin
|
|
if (i_reset_n = '0') then
|
|
o_buffer_data_out <= (OTHERS=> '0');
|
|
elsif (rising_edge(i_clock)) then
|
|
o_buffer_data_out <= data_from_buffer;
|
|
end if;
|
|
end process;
|
|
|
|
-- Circuit outputs.
|
|
o_command_valid <= message_valid;
|
|
o_command_timed_out <= timeout_combined;
|
|
o_command_crc_failed <= not crc_combined;
|
|
o_SD_clock <= SD_clock;
|
|
b_SD_cmd <= data_to_CMD_line when (CMD_tristate_buffer_enable = '1') else 'Z';
|
|
b_SD_dat <= data_line_out when (data_line_direction = '1') else 'Z';
|
|
b_SD_dat3 <= 'Z'; -- Set SD card to SD mode.
|
|
-- SD card registers
|
|
o_SD_REG_card_identification_number <= SD_REG_card_identification_number;
|
|
o_SD_REG_relative_card_address <= SD_REG_relative_card_address;
|
|
o_SD_REG_operating_conditions_register <= SD_REG_operating_conditions_register;
|
|
o_SD_REG_card_specific_data <= SD_REG_card_specific_data;
|
|
o_SD_REG_status_register <= SD_REG_status_register;
|
|
o_SD_REG_response_R1 <= SD_REG_response_R1;
|
|
o_SD_REG_status_register_valid <= SD_REG_status_register_valid;
|
|
|
|
end rtl;
|