mirror of https://github.com/marqs85/ossc.git
57 lines
1.7 KiB
VHDL
57 lines
1.7 KiB
VHDL
-- (C) 2001-2015 Altera Corporation. All rights reserved.
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-- Your use of Altera Corporation's design tools, logic functions and other
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-- software and tools, and its AMPP partner logic functions, and any output
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-- files any of the foregoing (including device programming or simulation
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-- files), and any associated documentation or information are expressly subject
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-- to the terms and conditions of the Altera Program License Subscription
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-- Agreement, Altera MegaCore Function License Agreement, or other applicable
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-- license agreement, including, without limitation, that your use is for the
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-- sole purpose of programming logic devices manufactured by Altera and sold by
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-- Altera or its authorized distributors. Please refer to the applicable
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-- agreement for further details.
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---------------------------------------------------------------------------------------
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-- This module generates a trigger pulse every time it sees a transition
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-- from 0 to 1 on signal i_signal.
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--
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-- NOTES/REVISIONS:
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---------------------------------------------------------------------------------------
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.numeric_std.all;
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entity Altera_UP_SD_Signal_Trigger is
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port
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(
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i_clock : in std_logic;
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i_reset_n : in std_logic;
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i_signal : in std_logic;
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o_trigger : out std_logic
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);
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end entity;
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architecture rtl of Altera_UP_SD_Signal_Trigger is
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-- Local wires
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-- REGISTERED
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signal local_reg : std_logic;
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begin
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process (i_clock, i_reset_n)
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begin
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if (i_reset_n = '0') then
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local_reg <= '0';
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else
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if (rising_edge(i_clock)) then
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local_reg <= i_signal;
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end if;
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end if;
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end process;
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o_trigger <= '1' when ((local_reg = '0') and (i_signal = '1'))
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else '0';
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end rtl; |