mirror of https://github.com/marqs85/ossc.git
73 lines
1.9 KiB
Verilog
73 lines
1.9 KiB
Verilog
//
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// fixed for 9.1 jan 21 2010 cruben
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//
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`include "timescale.v"
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`include "i2c_master_defines.v"
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module i2c_opencores
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(
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wb_clk_i, wb_rst_i, wb_adr_i, wb_dat_i, wb_dat_o,
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wb_we_i, wb_stb_i, /*wb_cyc_i,*/ wb_ack_o, wb_inta_o,
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scl_pad_io, sda_pad_io
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);
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// Common bus signals
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input wb_clk_i; // WISHBONE clock
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input wb_rst_i; // WISHBONE reset
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// Slave signals
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input [2:0] wb_adr_i; // WISHBONE address input
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input [7:0] wb_dat_i; // WISHBONE data input
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output [7:0] wb_dat_o; // WISHBONE data output
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input wb_we_i; // WISHBONE write enable input
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input wb_stb_i; // WISHBONE strobe input
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//input wb_cyc_i; // WISHBONE cycle input
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output wb_ack_o; // WISHBONE acknowledge output
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output wb_inta_o; // WISHBONE interrupt output
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// I2C signals
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inout scl_pad_io; // I2C clock io
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inout sda_pad_io; // I2C data io
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wire wb_cyc_i; // WISHBONE cycle input
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// Wire tri-state scl/sda
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wire scl_pad_i;
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wire scl_pad_o;
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wire scl_pad_io;
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wire scl_padoen_o;
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assign wb_cyc_i = wb_stb_i;
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assign scl_pad_i = scl_pad_io;
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assign scl_pad_io = scl_padoen_o ? 1'bZ : scl_pad_o;
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wire sda_pad_i;
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wire sda_pad_o;
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wire sda_pad_io;
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wire sda_padoen_o;
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assign sda_pad_i = sda_pad_io;
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assign sda_pad_io = sda_padoen_o ? 1'bZ : sda_pad_o;
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// Avalon doesn't have an asynchronous reset
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// set it to be inactive and just use synchronous reset
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// reset level is a parameter, 0 is the default (active-low reset)
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wire arst_i;
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assign arst_i = 1'b1;
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// Connect the top level I2C core
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i2c_master_top i2c_master_top_inst
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(
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.wb_clk_i(wb_clk_i), .wb_rst_i(wb_rst_i), .arst_i(arst_i),
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.wb_adr_i(wb_adr_i), .wb_dat_i(wb_dat_i), .wb_dat_o(wb_dat_o),
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.wb_we_i(wb_we_i), .wb_stb_i(wb_stb_i), .wb_cyc_i(wb_cyc_i),
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.wb_ack_o(wb_ack_o), .wb_inta_o(wb_inta_o),
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.scl_pad_i(scl_pad_i), .scl_pad_o(scl_pad_o), .scl_padoen_o(scl_padoen_o),
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.sda_pad_i(sda_pad_i), .sda_pad_o(sda_pad_o), .sda_padoen_o(sda_padoen_o)
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);
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endmodule
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