mirror of https://github.com/marqs85/ossc.git
78 lines
3.2 KiB
C
78 lines
3.2 KiB
C
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#ifndef __I2C_OPENCORES_REGS_H__
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#define __I2C_OPENCORES_REGS_H__
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#include <io.h>
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/* prescal clock/(5*desired_SCL) */
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/* all registers are 8 bits wide but on 32 bit address boundaries.*/
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/* reg definitions take from i2c_specs.pdf in the docs folder */
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#define IOADDR_I2C_OPENCORES_PRERLO(base) __IO_CALC_ADDRESS_NATIVE(base, 0)
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#define IORD_I2C_OPENCORES_PRERLO(base) IORD(base, 0)
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#define IOWR_I2C_OPENCORES_PRERLO(base, data) IOWR(base, 0, data)
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#define IOADDR_I2C_OPENCORES_PRERHI(base) __IO_CALC_ADDRESS_NATIVE(base, 0)
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#define IORD_I2C_OPENCORES_PRERHI(base) IORD(base, 1)
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#define IOWR_I2C_OPENCORES_PRERHI(base, data) IOWR(base, 1, data)
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#define IOADDR_I2C_OPENCORES_CTR(base) __IO_CALC_ADDRESS_NATIVE(base, 2)
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#define IORD_I2C_OPENCORES_CTR(base) IORD(base, 2)
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#define IOWR_I2C_OPENCORES_CTR(base, data) IOWR(base, 2, data)
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/* bit definitions*/
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#define I2C_OPENCORES_CTR_EN_MSK (0x80)
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#define I2C_OPENCORES_CTR_EN_OFST (7)
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#define I2C_OPENCORES_CTR_IEN_MSK (0x40)
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#define I2C_OPENCORES_CTR_IEN_OFST (6)
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#define IOADDR_I2C_OPENCORES_TXR(base) __IO_CALC_ADDRESS_NATIVE(base, 3)
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#define IOWR_I2C_OPENCORES_TXR(base, data) IOWR(base, 3, data)
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/* bit definitions*/
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#define I2C_OPENCORES_TXR_RD_MSK (0x1)
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#define I2C_OPENCORES_TXR_RD_OFST (0)
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#define I2C_OPENCORES_TXR_WR_MSK (0x0)
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#define I2C_OPENCORES_TXR_WR_OFST (0)
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#define IOADDR_I2C_OPENCORES_RXR(base) __IO_CALC_ADDRESS_NATIVE(base, 3)
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#define IORD_I2C_OPENCORES_RXR(base) IORD(base, 3)
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#define IOADDR_I2C_OPENCORES_CR(base) __IO_CALC_ADDRESS_NATIVE(base, 4)
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#define IOWR_I2C_OPENCORES_CR(base, data) IOWR(base, 4, data)
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/* bit definitions*/
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#define I2C_OPENCORES_CR_STA_MSK (0x80)
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#define I2C_OPENCORES_CR_STA_OFST (7)
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#define I2C_OPENCORES_CR_STO_MSK (0x40)
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#define I2C_OPENCORES_CR_STO_OFST (6)
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#define I2C_OPENCORES_CR_RD_MSK (0x20)
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#define I2C_OPENCORES_CR_RD_OFST (5)
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#define I2C_OPENCORES_CR_WR_MSK (0x10)
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#define I2C_OPENCORES_CR_WR_OFST (4)
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#define I2C_OPENCORES_CR_NACK_MSK (0x8)
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#define I2C_OPENCORES_CR_NACK_OFST (3)
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#define I2C_OPENCORES_CR_SPIM_MSK (0x4)
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#define I2C_OPENCORES_CR_SPIM_OFST (2)
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#define I2C_OPENCORES_CR_IACK_MSK (0x1)
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#define I2C_OPENCORES_CR_IACK_OFST (0)
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#define IOADDR_I2C_OPENCORES_SR(base) __IO_CALC_ADDRESS_NATIVE(base, 4)
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#define IORD_I2C_OPENCORES_SR(base) IORD(base, 4)
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/* bit definitions*/
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#define I2C_OPENCORES_SR_RXNACK_MSK (0x80)
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#define I2C_OPENCORES_SR_RXNACK_OFST (7)
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#define I2C_OPENCORES_SR_BUSY_MSK (0x40)
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#define I2C_OPENCORES_SR_BUSY_OFST (6)
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#define I2C_OPENCORES_SR_AL_MSK (0x20)
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#define I2C_OPENCORES_SR_AL_OFST (5)
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#define I2C_OPENCORES_SR_TIP_MSK (0x2)
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#define I2C_OPENCORES_SR_TIP_OFST (1)
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#define I2C_OPENCORES_SR_IF_MSK (0x1)
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#define I2C_OPENCORES_SR_IF_OFST (0)
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#endif /* __I2C_OPENCORES_REGS_H__ */
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