mirror of https://github.com/marqs85/ossc.git
102 lines
3.6 KiB
Verilog
102 lines
3.6 KiB
Verilog
/*
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Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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use of Altera Corporation's design tools, logic functions and other
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software and tools, and its AMPP partner logic functions, and any
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output files any of the foregoing (including device programming or
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simulation files), and any associated documentation or information are
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expressly subject to the terms and conditions of the Altera Program
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License Subscription Agreement or other applicable license agreement,
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including, without limitation, that your use is for the sole purpose
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of programming logic devices manufactured by Altera and sold by Altera
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or its authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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/*
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This thin wrapper re-uses the CRC Avalon component as a Nios II
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custom instruction. The n port of custom instruction is used as
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control to the CRC Avalon component. Below are the values of n and
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the corresponding operations perform by the custom instruction:
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n = 0, Initialize the custom instruction to the initial remainder value
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n = 1, Write 8 bits data to custom instruction
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n = 2, Write 16 bits data to custom instruction
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n = 3, Write 32 bits data to custom instruction
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n = 4, Read 32 bits data from the custom instruction
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n = 5, Read 64 bits data from the custom instruction
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n = 6, Read 96 bits data from the custom instruction
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n = 7, Read 128 bits data from the custom instruction
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*/
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module CRC_Custom_Instruction(clk,
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reset,
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dataa,
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n,
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clk_en,
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start,
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done,
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result);
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/*
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See the Avalon CRC component for details on the meaning of each
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parameter listed below.
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*/
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parameter crc_width = 32;
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parameter polynomial_inital = 32'hFFFFFFFF;
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parameter polynomial = 32'h04C11DB7;
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parameter reflected_input = 1;
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parameter reflected_output = 1;
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parameter xor_output = 32'hFFFFFFFF;
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input clk;
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input reset;
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input [31:0] dataa;
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input [2:0] n;
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input clk_en;
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input start;
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output done;
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output [31:0] result;
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wire [2:0] address;
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wire [3:0] byteenable;
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wire write;
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wire read;
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reg done_delay;
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assign write = (n<4);
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assign read = (n>3);
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assign byteenable = (n==1)?4'b0001 : (n==2)?4'b0011 : (n==3)?4'b1111 : 4'b0000;
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assign address = (n==0)?3'b000 : ((n==1)|(n==2)|(n==3))?3'b001 : (n==4)?3'b100 : (n==5)?3'b101 : (n==6)?3'b110 : 3'b111;
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assign done = (n>3)? done_delay : start;
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always @ (posedge clk or posedge reset)
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begin
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if (reset)
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done_delay <= 0;
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else
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done_delay <= start;
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end
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/*
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Instantiating the Avalon CRC component and wiring it to be
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custom instruction compilant
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*/
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CRC_Component wrapper_wiring(.clk(clk),
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.reset(reset),
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.address(address),
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.writedata(dataa),
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.byteenable(byteenable),
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.write(write & start),
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.read(read),
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.chipselect(clk_en),
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.readdata(result));
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defparam wrapper_wiring.crc_width = crc_width;
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defparam wrapper_wiring.polynomial_inital = polynomial_inital;
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defparam wrapper_wiring.polynomial = polynomial;
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defparam wrapper_wiring.reflected_input = reflected_input;
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defparam wrapper_wiring.reflected_output = reflected_output;
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defparam wrapper_wiring.xor_output = xor_output;
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endmodule
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