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463 lines
18 KiB
Verilog
463 lines
18 KiB
Verilog
//
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// Copyright (C) 2019-2022 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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module scanconverter (
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input PCLK_CAP_i,
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input PCLK_OUT_i,
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input reset_n,
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input [7:0] R_i,
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input [7:0] G_i,
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input [7:0] B_i,
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input HSYNC_i,
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input VSYNC_i,
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input DE_i,
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input FID_i,
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input datavalid_i,
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input interlaced_in_i,
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input frame_change_i,
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input [10:0] xpos_i,
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input [10:0] ypos_i,
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input [11:0] h_in_active,
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input [31:0] hv_out_config,
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input [31:0] hv_out_config2,
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input [31:0] hv_out_config3,
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input [31:0] xy_out_config,
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input [31:0] xy_out_config2,
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input [31:0] misc_config,
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input [31:0] sl_config,
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input [31:0] sl_config2,
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input [31:0] sl_config3,
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input testpattern_enable,
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input lb_enable,
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input ext_sync_mode,
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input ext_frame_change_i,
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input [7:0] ext_R_i,
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input [7:0] ext_G_i,
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input [7:0] ext_B_i,
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output PCLK_o,
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output [7:0] R_o,
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output [7:0] G_o,
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output [7:0] B_o,
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output HSYNC_o,
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output VSYNC_o,
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output DE_o,
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output [11:0] xpos_o,
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output [10:0] ypos_o,
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output reg resync_strobe,
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input emif_br_clk,
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input emif_br_reset,
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output [27:0] emif_rd_addr,
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output emif_rd_read,
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input [255:0] emif_rd_rdata,
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input emif_rd_waitrequest,
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input emif_rd_readdatavalid,
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output [5:0] emif_rd_burstcount,
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output [27:0] emif_wr_addr,
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output emif_wr_write,
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output [255:0] emif_wr_wdata,
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input emif_wr_waitrequest,
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output [5:0] emif_wr_burstcount
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);
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parameter EMIF_ENABLE = 0;
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parameter NUM_LINE_BUFFERS = 32;
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localparam FID_EVEN = 1'b0;
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localparam FID_ODD = 1'b1;
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localparam PP_PL_START = 1;
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localparam PP_LINEBUF_START = PP_PL_START + 1;
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localparam PP_LINEBUF_LENGTH = 1;
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localparam PP_LINEBUF_END = PP_LINEBUF_START + PP_LINEBUF_LENGTH;
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localparam PP_SRCSEL_START = PP_LINEBUF_END;
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localparam PP_SRCSEL_LENGTH = 1;
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localparam PP_SRCSEL_END = PP_SRCSEL_START + PP_SRCSEL_LENGTH;
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localparam PP_SLGEN_START = PP_SRCSEL_START;
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localparam PP_SLGEN_LENGTH = 3;
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localparam PP_SLGEN_END = PP_SLGEN_START + PP_SLGEN_LENGTH;
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localparam PP_TP_START = PP_SLGEN_END;
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localparam PP_TP_LENGTH = 1;
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localparam PP_TP_END = PP_TP_START + PP_TP_LENGTH;
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localparam PP_PL_END = PP_TP_END;
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wire [11:0] H_TOTAL = hv_out_config[11:0];
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wire [11:0] H_ACTIVE = hv_out_config[23:12];
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wire [7:0] H_SYNCLEN = hv_out_config[31:24];
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wire [8:0] H_BACKPORCH = hv_out_config2[8:0];
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wire V_INTERLACED = hv_out_config2[31];
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wire [10:0] V_TOTAL = hv_out_config2[19:9] >> V_INTERLACED;
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wire [10:0] V_ACTIVE = hv_out_config2[30:20];
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wire [3:0] V_SYNCLEN = hv_out_config3[3:0];
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wire [8:0] V_BACKPORCH = hv_out_config3[12:4];
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wire [10:0] V_STARTLINE = hv_out_config3[23:13];
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wire [10:0] V_STARTLINE_PREV = (V_STARTLINE == 0) ? (V_TOTAL-1) : (V_STARTLINE-1);
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wire [11:0] X_SIZE = xy_out_config[11:0];
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wire [10:0] Y_SIZE = xy_out_config[22:12];
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wire signed [9:0] X_OFFSET = xy_out_config2[9:0];
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wire signed [8:0] Y_OFFSET = xy_out_config[31:23];
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wire [7:0] X_START_LB = xy_out_config2[17:10];
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wire signed [5:0] Y_START_LB = xy_out_config2[23:18];
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wire signed [3:0] X_RPT = xy_out_config2[27:24];
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wire signed [3:0] Y_RPT = xy_out_config2[31:28];
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wire Y_SKIP = (Y_RPT == 4'(-1));
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wire [1:0] Y_STEP = Y_SKIP+1'b1;
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wire [3:0] SL_L_STR[5:0] = '{sl_config[23:20], sl_config[19:16], sl_config[15:12], sl_config[11:8], sl_config[7:4], sl_config[3:0]};
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wire [3:0] SL_C_STR[9:0] = '{sl_config3[7:4], sl_config3[3:0], sl_config2[31:28], sl_config2[27:24], sl_config2[23:20], sl_config2[19:16], sl_config2[15:12], sl_config2[11:8], sl_config2[7:4], sl_config2[3:0]};
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wire [5:0] SL_L_OVERLAY = sl_config[29:24];
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wire SL_METHOD_PRE = sl_config[30];
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wire SL_BOB_ALTERN = sl_config[31];
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wire [9:0] SL_C_OVERLAY = sl_config3[17:8];
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wire [2:0] SL_IV_Y = sl_config3[20:18];
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wire [3:0] SL_IV_X = sl_config3[24:21];
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wire [3:0] MISC_MASK_BR = misc_config[3:0];
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wire [2:0] MISC_MASK_COLOR = misc_config[6:4];
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wire [5:0] MISC_REV_LPF_STR = (misc_config[11:7] + 6'd16);
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wire MISC_REV_LPF_ENABLE = (misc_config[11:7] != 5'h0);
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wire MISC_LM_DEINT_MODE = misc_config[12];
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wire MISC_NIR_EVEN_OFFSET = misc_config[13];
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wire [3:0] MISC_BFI_STR = misc_config[19:16];
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wire MISC_BFI_ENABLE = misc_config[20];
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wire [7:0] MASK_R = MISC_MASK_COLOR[2] ? {2{MISC_MASK_BR}} : 8'h00;
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wire [7:0] MASK_G = MISC_MASK_COLOR[1] ? {2{MISC_MASK_BR}} : 8'h00;
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wire [7:0] MASK_B = MISC_MASK_COLOR[0] ? {2{MISC_MASK_BR}} : 8'h00;
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reg frame_change_sync1_reg, frame_change_sync2_reg, frame_change_prev, frame_change_resync;
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wire frame_change = frame_change_sync2_reg;
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reg [11:0] h_cnt;
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reg [10:0] v_cnt;
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reg h_avidstart, v_avidstart;
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reg src_fid, dst_fid;
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reg [10:0] xpos_lb;
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wire [10:0] xpos_lb_start = (X_OFFSET < 10'sd0) ? 11'd0 : {1'b0, X_OFFSET};
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reg [10:0] ypos_lb, ypos_lb_next;
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reg [3:0] x_ctr;
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reg [3:0] y_ctr;
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reg line_id;
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reg ypos_pp_init;
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reg [7:0] sl_str;
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reg sl_method;
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wire bfi_frame;
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wire [7:0] R_sl_mult, G_sl_mult, B_sl_mult;
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wire [7:0] R_linebuf, G_linebuf, B_linebuf;
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// Pipeline registers
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reg [7:0] R_pp[PP_LINEBUF_END:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [7:0] G_pp[PP_LINEBUF_END:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [7:0] B_pp[PP_LINEBUF_END:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg HSYNC_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg VSYNC_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg DE_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [11:0] xpos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg [10:0] ypos_pp[PP_PL_START:PP_PL_END] /* synthesis ramstyle = "logic" */;
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reg mask_enable_pp[PP_LINEBUF_START:PP_TP_START] /* synthesis ramstyle = "logic" */;
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reg draw_sl_pp[(PP_SLGEN_START+1):(PP_SLGEN_END-1)] /* synthesis ramstyle = "logic" */;
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reg [3:0] x_ctr_sl_pp[PP_PL_START:PP_SLGEN_START] /* synthesis ramstyle = "logic" */;
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reg [2:0] y_ctr_sl_pp[PP_PL_START:PP_SLGEN_START] /* synthesis ramstyle = "logic" */;
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assign PCLK_o = PCLK_OUT_i;
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lpm_mult_4_sl R_sl_mult_u
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(
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.clock(PCLK_OUT_i),
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.dataa(R_pp[PP_SLGEN_START+1]),
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.datab(~sl_str),
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.result(R_sl_mult)
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);
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lpm_mult_4_sl G_sl_mult_u
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(
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.clock(PCLK_OUT_i),
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.dataa(G_pp[PP_SLGEN_START+1]),
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.datab(~sl_str),
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.result(G_sl_mult)
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);
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lpm_mult_4_sl B_sl_mult_u
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(
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.clock(PCLK_OUT_i),
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.dataa(B_pp[PP_SLGEN_START+1]),
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.datab(~sl_str),
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.result(B_sl_mult)
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);
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linebuf_top #(
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.EMIF_ENABLE(EMIF_ENABLE),
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.NUM_LINE_BUFFERS(NUM_LINE_BUFFERS)
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) linebuf_top_inst (
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.PCLK_CAP_i(PCLK_CAP_i),
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.PCLK_OUT_i(PCLK_OUT_i),
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.R_i(R_i),
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.G_i(G_i),
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.B_i(B_i),
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.DE_i(DE_i),
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.datavalid_i(datavalid_i),
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.h_in_active(h_in_active),
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.xpos_i(xpos_i),
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.ypos_i(ypos_i),
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.xpos_lb(xpos_lb),
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.ypos_lb(ypos_lb),
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.ypos_lb_next(ypos_lb_next),
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.line_id(line_id),
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.lb_enable(lb_enable),
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.R_linebuf(R_linebuf),
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.G_linebuf(G_linebuf),
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.B_linebuf(B_linebuf),
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.emif_br_clk(emif_br_clk),
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.emif_br_reset(emif_br_reset),
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.emif_rd_addr(emif_rd_addr),
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.emif_rd_read(emif_rd_read),
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.emif_rd_rdata(emif_rd_rdata),
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.emif_rd_waitrequest(emif_rd_waitrequest),
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.emif_rd_readdatavalid(emif_rd_readdatavalid),
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.emif_rd_burstcount(emif_rd_burstcount),
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.emif_wr_addr(emif_wr_addr),
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.emif_wr_write(emif_wr_write),
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.emif_wr_wdata(emif_wr_wdata),
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.emif_wr_waitrequest(emif_wr_waitrequest),
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.emif_wr_burstcount(emif_wr_burstcount)
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);
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// Frame change strobe synchronization
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always @(posedge PCLK_OUT_i) begin
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frame_change_sync1_reg <= frame_change_i;
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frame_change_sync2_reg <= frame_change_sync1_reg;
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frame_change_prev <= frame_change_sync2_reg;
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frame_change_resync <= ~frame_change_prev & frame_change & ((v_cnt != V_STARTLINE_PREV) & (v_cnt != V_STARTLINE));
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end
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// H/V counters
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always @(posedge PCLK_OUT_i) begin
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if (ext_sync_mode & ext_frame_change_i) begin
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h_cnt <= PP_SRCSEL_START; // compensate pipeline delays
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v_cnt <= 0;
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bfi_frame <= bfi_frame ^ 1'b1;
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end else if (~ext_sync_mode & frame_change_resync) begin
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h_cnt <= 0;
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v_cnt <= V_STARTLINE;
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bfi_frame <= 0;
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src_fid <= (~interlaced_in_i | (V_STARTLINE < (V_TOTAL/2))) ? FID_ODD : FID_EVEN;
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dst_fid <= (~V_INTERLACED | (V_STARTLINE < (V_TOTAL/2))) ? FID_ODD : FID_EVEN;
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resync_strobe <= 1'b1;
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end else begin
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if (h_cnt == H_TOTAL-1) begin
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if ((~V_INTERLACED & (v_cnt == V_TOTAL-1)) |
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(V_INTERLACED & (dst_fid == FID_ODD) & (v_cnt == V_TOTAL)) |
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(V_INTERLACED & (dst_fid == FID_EVEN) & (v_cnt == V_TOTAL-1)))
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begin
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v_cnt <= 0;
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v_avidstart <= (V_SYNCLEN+V_BACKPORCH-1'b1 == 0);
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src_fid <= interlaced_in_i ? (src_fid ^ 1'b1) : FID_ODD;
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dst_fid <= V_INTERLACED ? (dst_fid ^ 1'b1) : FID_ODD;
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resync_strobe <= 1'b0;
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end else begin
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v_cnt <= v_cnt + 1'b1;
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v_avidstart <= (v_cnt == V_SYNCLEN+V_BACKPORCH-2'h2);
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end
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h_cnt <= 0;
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h_avidstart <= 1'b0;
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end else begin
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h_cnt <= h_cnt + 1'b1;
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h_avidstart <= (h_cnt == H_SYNCLEN+H_BACKPORCH-1'b1);
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end
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end
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end
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// Postprocess pipeline structure
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// 1 2 3 4 5 6 7
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// |----------|----------|---------|---------|---------|---------|--------|
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// | SYNC/DE | | | | | | |
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// | X/Y POS | | | | | | |
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// | | MASK | | | | | |
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// | | LB_SETUP | LINEBUF | | | | |
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// | | | | SRCSEL | | | |
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// | | | | SLGEN | SLGEN | SLGEN | |
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// | | | | | | | TP |
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// Pipeline stage 1
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always @(posedge PCLK_OUT_i) begin
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HSYNC_pp[1] <= (h_cnt < H_SYNCLEN) ? 1'b0 : 1'b1;
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if (dst_fid == FID_ODD)
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VSYNC_pp[1] <= ((v_cnt < V_SYNCLEN) | ((v_cnt == V_TOTAL) & (h_cnt >= (H_TOTAL/2)))) ? 1'b0 : 1'b1;
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else
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VSYNC_pp[1] <= ((v_cnt < V_SYNCLEN-1) | ((v_cnt == V_SYNCLEN-1) & (h_cnt < (H_TOTAL/2)))) ? 1'b0 : 1'b1;
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DE_pp[1] <= (h_cnt >= H_SYNCLEN+H_BACKPORCH) & (h_cnt < H_SYNCLEN+H_BACKPORCH+H_ACTIVE) & (v_cnt >= V_SYNCLEN+V_BACKPORCH) & (v_cnt < V_SYNCLEN+V_BACKPORCH+V_ACTIVE);
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if (h_avidstart) begin
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// Start 1 line before active so that linebuffer can be filled from DRAM in time
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if (v_avidstart) begin
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ypos_pp[1] <= 11'(-1);
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ypos_pp_init <= 1'b1;
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// Bob deinterlace adjusts linebuf start position and y_ctr for even source fields if
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// output is progressive mode. Noninterlace restore as raw output mode is an exception
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// which ignores LM deinterlace mode setting.
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if (~ext_sync_mode & ~MISC_LM_DEINT_MODE & (Y_RPT > 0) & ~V_INTERLACED & (src_fid == FID_EVEN)) begin
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ypos_lb_next <= 11'(Y_START_LB) - 1'b1;
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y_ctr <= ((Y_RPT+1'b1) >> 1);
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y_ctr_sl_pp[1] <= SL_BOB_ALTERN ? ((Y_RPT+1'b1) >> 1) : 0;
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end else begin
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if (Y_SKIP & (dst_fid == FID_EVEN)) begin
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// Linedrop mode and output interlaced
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ypos_lb_next <= 11'(Y_START_LB) + 1'b1;
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end else if ((((Y_RPT == 0) & ~V_INTERLACED) | ((Y_RPT > 0) & MISC_LM_DEINT_MODE)) & (src_fid == FID_EVEN)) begin
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// Adjust even field Y-offset for noninterlace restore
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ypos_lb_next <= 11'(Y_START_LB) - MISC_NIR_EVEN_OFFSET;
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end else begin
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ypos_lb_next <= 11'(Y_START_LB);
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end
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y_ctr <= 0;
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y_ctr_sl_pp[1] <= 0;
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end
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line_id <= ~line_id;
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end else begin
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if (ypos_pp[1] != V_ACTIVE) begin
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ypos_pp[1] <= ypos_pp[1] + 1'b1;
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if (ypos_pp_init | (y_ctr == Y_RPT) | Y_SKIP) begin
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if ((ypos_lb_next >= NUM_LINE_BUFFERS-Y_STEP) & (ypos_lb_next < NUM_LINE_BUFFERS))
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ypos_lb_next <= ypos_lb_next + Y_STEP - NUM_LINE_BUFFERS;
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else
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ypos_lb_next <= ypos_lb_next + Y_STEP;
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ypos_lb <= ypos_lb_next;
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line_id <= ~line_id;
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ypos_pp_init <= 1'b0;
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if (!ypos_pp_init)
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y_ctr <= 0;
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end else begin
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y_ctr <= y_ctr + 1'b1;
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end
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if (!ypos_pp_init)
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y_ctr_sl_pp[1] <= (y_ctr_sl_pp[1] == SL_IV_Y) ? 0 : y_ctr_sl_pp[1] + 1'b1;
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end
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end
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xpos_pp[1] <= 0;
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xpos_lb <= X_START_LB;
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x_ctr <= 0;
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x_ctr_sl_pp[1] <= 0;
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end else begin
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if (xpos_pp[1] != H_ACTIVE) begin
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xpos_pp[1] <= xpos_pp[1] + 1'b1;
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end
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if (xpos_pp[1] >= xpos_lb_start) begin
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if (x_ctr == X_RPT) begin
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xpos_lb <= xpos_lb + 1'b1;
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x_ctr <= 0;
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end else begin
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x_ctr <= x_ctr + 1'b1;
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end
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x_ctr_sl_pp[1] <= (x_ctr_sl_pp[1] == SL_IV_X) ? 0 : x_ctr_sl_pp[1] + 1'b1;
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end
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end
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end
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// Pipeline stages 2-
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integer pp_idx;
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always @(posedge PCLK_OUT_i) begin
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for(pp_idx = PP_LINEBUF_START; pp_idx <= PP_PL_END; pp_idx = pp_idx+1) begin
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HSYNC_pp[pp_idx] <= HSYNC_pp[pp_idx-1];
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VSYNC_pp[pp_idx] <= VSYNC_pp[pp_idx-1];
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DE_pp[pp_idx] <= DE_pp[pp_idx-1];
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xpos_pp[pp_idx] <= xpos_pp[pp_idx-1];
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ypos_pp[pp_idx] <= ypos_pp[pp_idx-1];
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end
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for(pp_idx = PP_LINEBUF_START; pp_idx <= PP_SLGEN_START; pp_idx = pp_idx+1) begin
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x_ctr_sl_pp[pp_idx] <= x_ctr_sl_pp[pp_idx-1];
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y_ctr_sl_pp[pp_idx] <= y_ctr_sl_pp[pp_idx-1];
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end
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if (($signed({1'b0, xpos_pp[PP_LINEBUF_START-1]}) >= X_OFFSET) &
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($signed({1'b0, xpos_pp[PP_LINEBUF_START-1]}) < X_OFFSET+X_SIZE) &
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($signed({1'b0, ypos_pp[PP_LINEBUF_START-1]}) >= Y_OFFSET) &
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($signed({1'b0, ypos_pp[PP_LINEBUF_START-1]}) < Y_OFFSET+Y_SIZE))
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begin
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mask_enable_pp[PP_LINEBUF_START] <= 1'b0;
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end else begin
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mask_enable_pp[PP_LINEBUF_START] <= 1'b1;
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end
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for(pp_idx = PP_LINEBUF_START+1; pp_idx <= PP_TP_START; pp_idx = pp_idx+1) begin
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mask_enable_pp[pp_idx] <= mask_enable_pp[pp_idx-1];
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end
|
|
|
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R_pp[PP_SRCSEL_END] <= ext_sync_mode ? ext_R_i : R_linebuf;
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G_pp[PP_SRCSEL_END] <= ext_sync_mode ? ext_G_i : G_linebuf;
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B_pp[PP_SRCSEL_END] <= ext_sync_mode ? ext_B_i : B_linebuf;
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|
|
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// Scanlines (3 cycles)
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if (MISC_BFI_ENABLE & bfi_frame) begin
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sl_str <= ((MISC_BFI_STR+8'h01)<<4)-1'b1;
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sl_method <= 1'b1;
|
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draw_sl_pp[PP_SLGEN_START+1] <= 1'b1;
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end else if (|(SL_L_OVERLAY & (6'h1<<y_ctr_sl_pp[PP_SLGEN_START]))) begin
|
|
sl_str <= ((SL_L_STR[y_ctr_sl_pp[PP_SLGEN_START]]+8'h01)<<4)-1'b1;
|
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sl_method <= ~SL_METHOD_PRE;
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|
draw_sl_pp[PP_SLGEN_START+1] <= 1'b1;
|
|
end else if (|(SL_C_OVERLAY & (10'h1<<x_ctr_sl_pp[PP_SLGEN_START]))) begin
|
|
sl_str <= ((SL_C_STR[x_ctr_sl_pp[PP_SLGEN_START]]+8'h01)<<4)-1'b1;
|
|
sl_method <= ~SL_METHOD_PRE;
|
|
draw_sl_pp[PP_SLGEN_START+1] <= 1'b1;
|
|
end else begin
|
|
draw_sl_pp[PP_SLGEN_START+1] <= 1'b0;
|
|
end
|
|
for (pp_idx = PP_SLGEN_START+2; pp_idx <= PP_SLGEN_END-1; pp_idx = pp_idx+1) begin
|
|
draw_sl_pp[pp_idx] <= draw_sl_pp[pp_idx-1];
|
|
end
|
|
|
|
R_pp[PP_SLGEN_START+2] <= draw_sl_pp[PP_SLGEN_START+1] ? ((R_pp[PP_SLGEN_START+1] > sl_str) ? (R_pp[PP_SLGEN_START+1] - sl_str) : 8'h00) : R_pp[PP_SLGEN_START+1];
|
|
G_pp[PP_SLGEN_START+2] <= draw_sl_pp[PP_SLGEN_START+1] ? ((G_pp[PP_SLGEN_START+1] > sl_str) ? (G_pp[PP_SLGEN_START+1] - sl_str) : 8'h00) : G_pp[PP_SLGEN_START+1];
|
|
B_pp[PP_SLGEN_START+2] <= draw_sl_pp[PP_SLGEN_START+1] ? ((B_pp[PP_SLGEN_START+1] > sl_str) ? (B_pp[PP_SLGEN_START+1] - sl_str) : 8'h00) : B_pp[PP_SLGEN_START+1];
|
|
|
|
R_pp[PP_SLGEN_END] <= (draw_sl_pp[PP_SLGEN_START+2] & sl_method) ? R_sl_mult : R_pp[PP_SLGEN_START+2];
|
|
G_pp[PP_SLGEN_END] <= (draw_sl_pp[PP_SLGEN_START+2] & sl_method) ? G_sl_mult : G_pp[PP_SLGEN_START+2];
|
|
B_pp[PP_SLGEN_END] <= (draw_sl_pp[PP_SLGEN_START+2] & sl_method) ? B_sl_mult : B_pp[PP_SLGEN_START+2];
|
|
|
|
R_pp[PP_TP_END] <= testpattern_enable ? (xpos_pp[PP_TP_START] ^ ypos_pp[PP_TP_START]) : (mask_enable_pp[PP_TP_START] ? MASK_R : R_pp[PP_TP_START]);
|
|
G_pp[PP_TP_END] <= testpattern_enable ? (xpos_pp[PP_TP_START] ^ ypos_pp[PP_TP_START]) : (mask_enable_pp[PP_TP_START] ? MASK_G : G_pp[PP_TP_START]);
|
|
B_pp[PP_TP_END] <= testpattern_enable ? (xpos_pp[PP_TP_START] ^ ypos_pp[PP_TP_START]) : (mask_enable_pp[PP_TP_START] ? MASK_B : B_pp[PP_TP_START]);
|
|
end
|
|
|
|
// Output
|
|
assign R_o = R_pp[PP_PL_END];
|
|
assign G_o = G_pp[PP_PL_END];
|
|
assign B_o = B_pp[PP_PL_END];
|
|
assign HSYNC_o = HSYNC_pp[PP_PL_END];
|
|
assign VSYNC_o = VSYNC_pp[PP_PL_END];
|
|
assign DE_o = DE_pp[PP_PL_END];
|
|
assign xpos_o = xpos_pp[PP_PL_END];
|
|
assign ypos_o = ypos_pp[PP_PL_END];
|
|
|
|
endmodule
|