mirror of https://github.com/marqs85/ossc.git
203 lines
10 KiB
C
203 lines
10 KiB
C
/******************************************************************************
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* *
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* License Agreement *
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* *
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* Copyright (c) 2003 Altera Corporation, San Jose, California, USA. *
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* All rights reserved. *
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* *
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* Permission is hereby granted, free of charge, to any person obtaining a *
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* copy of this software and associated documentation files (the "Software"), *
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* to deal in the Software without restriction, including without limitation *
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* the rights to use, copy, modify, merge, publish, distribute, sublicense, *
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* and/or sell copies of the Software, and to permit persons to whom the *
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* Software is furnished to do so, subject to the following conditions: *
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* *
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* The above copyright notice and this permission notice shall be included in *
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* all copies or substantial portions of the Software. *
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* *
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR *
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, *
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE *
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER *
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING *
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER *
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* DEALINGS IN THE SOFTWARE. *
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* *
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* This agreement shall be governed in all respects by the laws of the State *
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* of California and by the laws of the United States of America. *
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* *
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******************************************************************************/
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#ifndef __ALTERA_AVALON_TIMER_REGS_H__
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#define __ALTERA_AVALON_TIMER_REGS_H__
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#include <io.h>
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/* STATUS register */
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#define ALTERA_AVALON_TIMER_STATUS_REG 0
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#define IOADDR_ALTERA_AVALON_TIMER_STATUS(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_STATUS_REG)
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#define IORD_ALTERA_AVALON_TIMER_STATUS(base) \
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IORD(base, ALTERA_AVALON_TIMER_STATUS_REG)
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#define IOWR_ALTERA_AVALON_TIMER_STATUS(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_STATUS_REG, data)
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#define ALTERA_AVALON_TIMER_STATUS_TO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_STATUS_TO_OFST (0)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_MSK (0x2)
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#define ALTERA_AVALON_TIMER_STATUS_RUN_OFST (1)
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/* CONTROL register */
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#define ALTERA_AVALON_TIMER_CONTROL_REG 1
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#define IOADDR_ALTERA_AVALON_TIMER_CONTROL(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_CONTROL_REG)
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#define IORD_ALTERA_AVALON_TIMER_CONTROL(base) \
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IORD(base, ALTERA_AVALON_TIMER_CONTROL_REG)
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#define IOWR_ALTERA_AVALON_TIMER_CONTROL(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_CONTROL_REG, data)
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_MSK (0x1)
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#define ALTERA_AVALON_TIMER_CONTROL_ITO_OFST (0)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_MSK (0x2)
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#define ALTERA_AVALON_TIMER_CONTROL_CONT_OFST (1)
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#define ALTERA_AVALON_TIMER_CONTROL_START_MSK (0x4)
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#define ALTERA_AVALON_TIMER_CONTROL_START_OFST (2)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_MSK (0x8)
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#define ALTERA_AVALON_TIMER_CONTROL_STOP_OFST (3)
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/* Period and SnapShot Register for COUNTER_SIZE = 32 */
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/*----------------------------------------------------*/
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/* PERIODL register */
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#define ALTERA_AVALON_TIMER_PERIODL_REG 2
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#define IOADDR_ALTERA_AVALON_TIMER_PERIODL(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODL_REG)
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#define IORD_ALTERA_AVALON_TIMER_PERIODL(base) \
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IORD(base, ALTERA_AVALON_TIMER_PERIODL_REG)
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#define IOWR_ALTERA_AVALON_TIMER_PERIODL(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_PERIODL_REG, data)
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#define ALTERA_AVALON_TIMER_PERIODL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODL_OFST (0)
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/* PERIODH register */
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#define ALTERA_AVALON_TIMER_PERIODH_REG 3
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#define IOADDR_ALTERA_AVALON_TIMER_PERIODH(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIODH_REG)
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#define IORD_ALTERA_AVALON_TIMER_PERIODH(base) \
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IORD(base, ALTERA_AVALON_TIMER_PERIODH_REG)
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#define IOWR_ALTERA_AVALON_TIMER_PERIODH(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_PERIODH_REG, data)
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#define ALTERA_AVALON_TIMER_PERIODH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIODH_OFST (0)
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/* SNAPL register */
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#define ALTERA_AVALON_TIMER_SNAPL_REG 4
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#define IOADDR_ALTERA_AVALON_TIMER_SNAPL(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPL_REG)
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#define IORD_ALTERA_AVALON_TIMER_SNAPL(base) \
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IORD(base, ALTERA_AVALON_TIMER_SNAPL_REG)
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#define IOWR_ALTERA_AVALON_TIMER_SNAPL(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_SNAPL_REG, data)
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#define ALTERA_AVALON_TIMER_SNAPL_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPL_OFST (0)
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/* SNAPH register */
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#define ALTERA_AVALON_TIMER_SNAPH_REG 5
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#define IOADDR_ALTERA_AVALON_TIMER_SNAPH(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAPH_REG)
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#define IORD_ALTERA_AVALON_TIMER_SNAPH(base) \
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IORD(base, ALTERA_AVALON_TIMER_SNAPH_REG)
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#define IOWR_ALTERA_AVALON_TIMER_SNAPH(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_SNAPH_REG, data)
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#define ALTERA_AVALON_TIMER_SNAPH_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAPH_OFST (0)
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/* Period and SnapShot Register for COUNTER_SIZE = 64 */
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/*----------------------------------------------------*/
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/* PERIOD_0 register */
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#define ALTERA_AVALON_TIMER_PERIOD_0_REG 2
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#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_0(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_0_REG)
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#define IORD_ALTERA_AVALON_TIMER_PERIOD_0(base) \
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IORD(base, ALTERA_AVALON_TIMER_PERIOD_0_REG)
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#define IOWR_ALTERA_AVALON_TIMER_PERIOD_0(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_PERIOD_0_REG, data)
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#define ALTERA_AVALON_TIMER_PERIOD_0_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIOD_0_OFST (0)
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/* PERIOD_1 register */
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#define ALTERA_AVALON_TIMER_PERIOD_1_REG 3
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#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_1(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_1_REG)
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#define IORD_ALTERA_AVALON_TIMER_PERIOD_1(base) \
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IORD(base, ALTERA_AVALON_TIMER_PERIOD_1_REG)
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#define IOWR_ALTERA_AVALON_TIMER_PERIOD_1(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_PERIOD_1_REG, data)
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#define ALTERA_AVALON_TIMER_PERIOD_1_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIOD_1_OFST (0)
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/* PERIOD_2 register */
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#define ALTERA_AVALON_TIMER_PERIOD_2_REG 4
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#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_2(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_2_REG)
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#define IORD_ALTERA_AVALON_TIMER_PERIOD_2(base) \
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IORD(base, ALTERA_AVALON_TIMER_PERIOD_2_REG)
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#define IOWR_ALTERA_AVALON_TIMER_PERIOD_2(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_PERIOD_2_REG, data)
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#define ALTERA_AVALON_TIMER_PERIOD_2_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIOD_2_OFST (0)
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/* PERIOD_3 register */
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#define ALTERA_AVALON_TIMER_PERIOD_3_REG 5
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#define IOADDR_ALTERA_AVALON_TIMER_PERIOD_3(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_PERIOD_3_REG)
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#define IORD_ALTERA_AVALON_TIMER_PERIOD_3(base) \
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IORD(base, ALTERA_AVALON_TIMER_PERIOD_3_REG)
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#define IOWR_ALTERA_AVALON_TIMER_PERIOD_3(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_PERIOD_3_REG, data)
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#define ALTERA_AVALON_TIMER_PERIOD_3_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_PERIOD_3_OFST (0)
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/* SNAP_0 register */
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#define ALTERA_AVALON_TIMER_SNAP_0_REG 6
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#define IOADDR_ALTERA_AVALON_TIMER_SNAP_0(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_0_REG)
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#define IORD_ALTERA_AVALON_TIMER_SNAP_0(base) \
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IORD(base, ALTERA_AVALON_TIMER_SNAP_0_REG)
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#define IOWR_ALTERA_AVALON_TIMER_SNAP_0(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_SNAP_0_REG, data)
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#define ALTERA_AVALON_TIMER_SNAP_0_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAP_0_OFST (0)
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/* SNAP_1 register */
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#define ALTERA_AVALON_TIMER_SNAP_1_REG 7
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#define IOADDR_ALTERA_AVALON_TIMER_SNAP_1(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_1_REG)
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#define IORD_ALTERA_AVALON_TIMER_SNAP_1(base) \
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IORD(base, ALTERA_AVALON_TIMER_SNAP_1_REG)
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#define IOWR_ALTERA_AVALON_TIMER_SNAP_1(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_SNAP_1_REG, data)
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#define ALTERA_AVALON_TIMER_SNAP_1_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAP_1_OFST (0)
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/* SNAP_2 register */
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#define ALTERA_AVALON_TIMER_SNAP_2_REG 8
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#define IOADDR_ALTERA_AVALON_TIMER_SNAP_2(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_2_REG)
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#define IORD_ALTERA_AVALON_TIMER_SNAP_2(base) \
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IORD(base, ALTERA_AVALON_TIMER_SNAP_2_REG)
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#define IOWR_ALTERA_AVALON_TIMER_SNAP_2(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_SNAP_2_REG, data)
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#define ALTERA_AVALON_TIMER_SNAP_2_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAP_2_OFST (0)
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/* SNAP_3 register */
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#define ALTERA_AVALON_TIMER_SNAP_3_REG 9
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#define IOADDR_ALTERA_AVALON_TIMER_SNAP_3(base) \
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__IO_CALC_ADDRESS_NATIVE(base, ALTERA_AVALON_TIMER_SNAP_3_REG)
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#define IORD_ALTERA_AVALON_TIMER_SNAP_3(base) \
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IORD(base, ALTERA_AVALON_TIMER_SNAP_3_REG)
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#define IOWR_ALTERA_AVALON_TIMER_SNAP_3(base, data) \
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IOWR(base, ALTERA_AVALON_TIMER_SNAP_3_REG, data)
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#define ALTERA_AVALON_TIMER_SNAP_3_MSK (0xFFFF)
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#define ALTERA_AVALON_TIMER_SNAP_3_OFST (0)
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#endif /* __ALTERA_AVALON_TIMER_REGS_H__ */
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