mirror of https://github.com/marqs85/ossc.git
596 lines
17 KiB
C
596 lines
17 KiB
C
/*
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* system.h - SOPC Builder system and BSP software package information
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*
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* Machine generated for CPU 'nios2_qsys_0' in SOPC Builder design 'sys'
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* SOPC Builder design path: ../../sys.sopcinfo
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*
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* Generated: Fri Oct 05 19:59:02 EEST 2018
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*/
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/*
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* DO NOT MODIFY THIS FILE
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*
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* Changing this file will have subtle consequences
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* which will almost certainly lead to a nonfunctioning
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* system. If you do modify this file, be aware that your
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* changes will be overwritten and lost when this file
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* is generated again.
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*
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* DO NOT MODIFY THIS FILE
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*/
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/*
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* License Agreement
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*
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* Copyright (c) 2008
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* Altera Corporation, San Jose, California, USA.
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* All rights reserved.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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* AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* This agreement shall be governed in all respects by the laws of the State
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* of California and by the laws of the United States of America.
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*/
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#ifndef __SYSTEM_H_
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#define __SYSTEM_H_
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/* Include definitions from linker script generator */
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#include "linker.h"
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/*
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* CPU configuration
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*
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*/
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#define ALT_CPU_ARCHITECTURE "altera_nios2_gen2"
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#define ALT_CPU_BIG_ENDIAN 0
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#define ALT_CPU_BREAK_ADDR 0x00000820
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#define ALT_CPU_CPU_ARCH_NIOS2_R1
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#define ALT_CPU_CPU_FREQ 27000000u
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#define ALT_CPU_CPU_ID_SIZE 1
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#define ALT_CPU_CPU_ID_VALUE 0x00000000
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#define ALT_CPU_CPU_IMPLEMENTATION "tiny"
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#define ALT_CPU_DATA_ADDR_WIDTH 0x18
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#define ALT_CPU_DCACHE_LINE_SIZE 0
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#define ALT_CPU_DCACHE_LINE_SIZE_LOG2 0
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#define ALT_CPU_DCACHE_SIZE 0
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#define ALT_CPU_EXCEPTION_ADDR 0x00010020
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#define ALT_CPU_FLASH_ACCELERATOR_LINES 0
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#define ALT_CPU_FLASH_ACCELERATOR_LINE_SIZE 0
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#define ALT_CPU_FLUSHDA_SUPPORTED
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#define ALT_CPU_FREQ 27000000
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#define ALT_CPU_HARDWARE_DIVIDE_PRESENT 0
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#define ALT_CPU_HARDWARE_MULTIPLY_PRESENT 0
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#define ALT_CPU_HARDWARE_MULX_PRESENT 0
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#define ALT_CPU_HAS_DEBUG_CORE 1
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#define ALT_CPU_HAS_DEBUG_STUB
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#define ALT_CPU_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
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#define ALT_CPU_HAS_JMPI_INSTRUCTION
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#define ALT_CPU_ICACHE_LINE_SIZE 0
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#define ALT_CPU_ICACHE_LINE_SIZE_LOG2 0
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#define ALT_CPU_ICACHE_SIZE 0
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#define ALT_CPU_INST_ADDR_WIDTH 0x11
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#define ALT_CPU_NAME "nios2_qsys_0"
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#define ALT_CPU_OCI_VERSION 1
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#define ALT_CPU_RESET_ADDR 0x00010000
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/*
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* CPU configuration (with legacy prefix - don't use these anymore)
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*
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*/
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#define NIOS2_BIG_ENDIAN 0
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#define NIOS2_BREAK_ADDR 0x00000820
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#define NIOS2_CPU_ARCH_NIOS2_R1
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#define NIOS2_CPU_FREQ 27000000u
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#define NIOS2_CPU_ID_SIZE 1
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#define NIOS2_CPU_ID_VALUE 0x00000000
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#define NIOS2_CPU_IMPLEMENTATION "tiny"
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#define NIOS2_DATA_ADDR_WIDTH 0x18
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#define NIOS2_DCACHE_LINE_SIZE 0
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#define NIOS2_DCACHE_LINE_SIZE_LOG2 0
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#define NIOS2_DCACHE_SIZE 0
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#define NIOS2_EXCEPTION_ADDR 0x00010020
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#define NIOS2_FLASH_ACCELERATOR_LINES 0
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#define NIOS2_FLASH_ACCELERATOR_LINE_SIZE 0
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#define NIOS2_FLUSHDA_SUPPORTED
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#define NIOS2_HARDWARE_DIVIDE_PRESENT 0
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#define NIOS2_HARDWARE_MULTIPLY_PRESENT 0
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#define NIOS2_HARDWARE_MULX_PRESENT 0
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#define NIOS2_HAS_DEBUG_CORE 1
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#define NIOS2_HAS_DEBUG_STUB
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#define NIOS2_HAS_ILLEGAL_INSTRUCTION_EXCEPTION
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#define NIOS2_HAS_JMPI_INSTRUCTION
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#define NIOS2_ICACHE_LINE_SIZE 0
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#define NIOS2_ICACHE_LINE_SIZE_LOG2 0
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#define NIOS2_ICACHE_SIZE 0
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#define NIOS2_INST_ADDR_WIDTH 0x11
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#define NIOS2_OCI_VERSION 1
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#define NIOS2_RESET_ADDR 0x00010000
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/*
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* Custom instruction macros
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*
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*/
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//#define ALT_CI_NIOS2_HW_CRC32_0(n,A) __builtin_custom_ini(ALT_CI_NIOS2_HW_CRC32_0_N+(n&ALT_CI_NIOS2_HW_CRC32_0_N_MASK),(A))
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#define ALT_CI_NIOS2_HW_CRC32_0_N 0x0
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#define ALT_CI_NIOS2_HW_CRC32_0_N_MASK ((1<<3)-1)
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//#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N,(A))
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#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0_N 0x9
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//#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) __builtin_custom_ini(ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N,(A))
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#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0_N 0x8
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#define ALT_CI_NIOS2_HW_CRC32_0(n,A) n
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#define ALT_CI_NIOS_CUSTOM_INSTR_BITSWAP_0(A) A
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#define ALT_CI_NIOS_CUSTOM_INSTR_ENDIANCONVERTER_0(A) A
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/*
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* Define for each module class mastered by the CPU
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*
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*/
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#define __ALTERA_AVALON_JTAG_UART
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#define __ALTERA_AVALON_ONCHIP_MEMORY2
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#define __ALTERA_AVALON_PIO
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#define __ALTERA_AVALON_TIMER
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#define __ALTERA_EPCQ_CONTROLLER_MOD
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#define __ALTERA_NIOS2_GEN2
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#define __ALTERA_NIOS_CUSTOM_INSTR_BITSWAP
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#define __ALTERA_NIOS_CUSTOM_INSTR_ENDIANCONVERTER
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#define __I2C_OPENCORES
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#define __NIOS2_HW_CRC32
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/*
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* System configuration
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*
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*/
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#define ALT_DEVICE_FAMILY "Cyclone IV E"
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#define ALT_ENHANCED_INTERRUPT_API_PRESENT
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#define ALT_IRQ_BASE NULL
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#define ALT_LOG_PORT "/dev/null"
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#define ALT_LOG_PORT_BASE 0x0
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#define ALT_LOG_PORT_DEV null
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#define ALT_LOG_PORT_TYPE ""
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#define ALT_NUM_EXTERNAL_INTERRUPT_CONTROLLERS 0
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#define ALT_NUM_INTERNAL_INTERRUPT_CONTROLLERS 1
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#define ALT_NUM_INTERRUPT_CONTROLLERS 1
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#define ALT_STDERR "/dev/jtag_uart_0"
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#define ALT_STDERR_BASE 0x20020
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#define ALT_STDERR_DEV jtag_uart_0
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#define ALT_STDERR_IS_JTAG_UART
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#define ALT_STDERR_PRESENT
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#define ALT_STDERR_TYPE "altera_avalon_jtag_uart"
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#define ALT_STDIN "/dev/jtag_uart_0"
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#define ALT_STDIN_BASE 0x20020
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#define ALT_STDIN_DEV jtag_uart_0
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#define ALT_STDIN_IS_JTAG_UART
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#define ALT_STDIN_PRESENT
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#define ALT_STDIN_TYPE "altera_avalon_jtag_uart"
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#define ALT_STDOUT "/dev/jtag_uart_0"
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#define ALT_STDOUT_BASE 0x20020
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#define ALT_STDOUT_DEV jtag_uart_0
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#define ALT_STDOUT_IS_JTAG_UART
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#define ALT_STDOUT_PRESENT
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#define ALT_STDOUT_TYPE "altera_avalon_jtag_uart"
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#define ALT_SYSTEM_NAME "sys"
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/*
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* epcq_controller_0_avl_csr configuration
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*
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*/
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#define ALT_MODULE_CLASS_epcq_controller_0_avl_csr altera_epcq_controller_mod
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#define EPCQ_CONTROLLER_0_AVL_CSR_BASE 0x20100
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#define EPCQ_CONTROLLER_0_AVL_CSR_FLASH_TYPE "EPCS64"
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#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ 2
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#define EPCQ_CONTROLLER_0_AVL_CSR_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define EPCQ_CONTROLLER_0_AVL_CSR_IS_EPCS 1
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#define EPCQ_CONTROLLER_0_AVL_CSR_NAME "/dev/epcq_controller_0_avl_csr"
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#define EPCQ_CONTROLLER_0_AVL_CSR_NUMBER_OF_SECTORS 128
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#define EPCQ_CONTROLLER_0_AVL_CSR_PAGE_SIZE 256
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#define EPCQ_CONTROLLER_0_AVL_CSR_SECTOR_SIZE 65536
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#define EPCQ_CONTROLLER_0_AVL_CSR_SPAN 32
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#define EPCQ_CONTROLLER_0_AVL_CSR_SUBSECTOR_SIZE 4096
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#define EPCQ_CONTROLLER_0_AVL_CSR_TYPE "altera_epcq_controller_mod"
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/*
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* epcq_controller_0_avl_mem configuration
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*
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*/
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#define ALT_MODULE_CLASS_epcq_controller_0_avl_mem altera_epcq_controller_mod
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#define EPCQ_CONTROLLER_0_AVL_MEM_BASE 0x800000
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#define EPCQ_CONTROLLER_0_AVL_MEM_FLASH_TYPE "EPCS64"
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#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ -1
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#define EPCQ_CONTROLLER_0_AVL_MEM_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define EPCQ_CONTROLLER_0_AVL_MEM_IS_EPCS 1
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#define EPCQ_CONTROLLER_0_AVL_MEM_NAME "/dev/epcq_controller_0_avl_mem"
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#define EPCQ_CONTROLLER_0_AVL_MEM_NUMBER_OF_SECTORS 128
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#define EPCQ_CONTROLLER_0_AVL_MEM_PAGE_SIZE 256
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#define EPCQ_CONTROLLER_0_AVL_MEM_SECTOR_SIZE 65536
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#define EPCQ_CONTROLLER_0_AVL_MEM_SPAN 8388608
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#define EPCQ_CONTROLLER_0_AVL_MEM_SUBSECTOR_SIZE 4096
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#define EPCQ_CONTROLLER_0_AVL_MEM_TYPE "altera_epcq_controller_mod"
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/*
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* hal configuration
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*
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*/
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#define ALT_MAX_FD 32
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#define ALT_SYS_CLK none
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#define ALT_TIMESTAMP_CLK TIMER_0
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/*
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* i2c_opencores_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_i2c_opencores_0 i2c_opencores
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#define I2C_OPENCORES_0_BASE 0x21040
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#define I2C_OPENCORES_0_IRQ 3
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#define I2C_OPENCORES_0_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define I2C_OPENCORES_0_NAME "/dev/i2c_opencores_0"
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#define I2C_OPENCORES_0_SPAN 32
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#define I2C_OPENCORES_0_TYPE "i2c_opencores"
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/*
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* i2c_opencores_1 configuration
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*
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*/
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#define ALT_MODULE_CLASS_i2c_opencores_1 i2c_opencores
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#define I2C_OPENCORES_1_BASE 0x21020
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#define I2C_OPENCORES_1_IRQ 4
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#define I2C_OPENCORES_1_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define I2C_OPENCORES_1_NAME "/dev/i2c_opencores_1"
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#define I2C_OPENCORES_1_SPAN 32
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#define I2C_OPENCORES_1_TYPE "i2c_opencores"
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/*
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* jtag_uart_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_jtag_uart_0 altera_avalon_jtag_uart
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#define JTAG_UART_0_BASE 0x20020
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#define JTAG_UART_0_IRQ 1
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#define JTAG_UART_0_IRQ_INTERRUPT_CONTROLLER_ID 0
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#define JTAG_UART_0_NAME "/dev/jtag_uart_0"
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#define JTAG_UART_0_READ_DEPTH 64
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#define JTAG_UART_0_READ_THRESHOLD 8
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#define JTAG_UART_0_SPAN 8
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#define JTAG_UART_0_TYPE "altera_avalon_jtag_uart"
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#define JTAG_UART_0_WRITE_DEPTH 64
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#define JTAG_UART_0_WRITE_THRESHOLD 8
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/*
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* onchip_memory2_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_onchip_memory2_0 altera_avalon_onchip_memory2
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#define ONCHIP_MEMORY2_0_ALLOW_IN_SYSTEM_MEMORY_CONTENT_EDITOR 0
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#define ONCHIP_MEMORY2_0_ALLOW_MRAM_SIM_CONTENTS_ONLY_FILE 0
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#define ONCHIP_MEMORY2_0_BASE 0x10000
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#define ONCHIP_MEMORY2_0_CONTENTS_INFO ""
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#define ONCHIP_MEMORY2_0_DUAL_PORT 0
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#define ONCHIP_MEMORY2_0_GUI_RAM_BLOCK_TYPE "AUTO"
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#define ONCHIP_MEMORY2_0_INIT_CONTENTS_FILE "sys_onchip_memory2_0"
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#define ONCHIP_MEMORY2_0_INIT_MEM_CONTENT 1
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#define ONCHIP_MEMORY2_0_INSTANCE_ID "NONE"
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#define ONCHIP_MEMORY2_0_IRQ -1
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#define ONCHIP_MEMORY2_0_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define ONCHIP_MEMORY2_0_NAME "/dev/onchip_memory2_0"
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#define ONCHIP_MEMORY2_0_NON_DEFAULT_INIT_FILE_ENABLED 0
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#define ONCHIP_MEMORY2_0_RAM_BLOCK_TYPE "AUTO"
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#define ONCHIP_MEMORY2_0_READ_DURING_WRITE_MODE "DONT_CARE"
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#define ONCHIP_MEMORY2_0_SINGLE_CLOCK_OP 0
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#define ONCHIP_MEMORY2_0_SIZE_MULTIPLE 1
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#define ONCHIP_MEMORY2_0_SIZE_VALUE 40960
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#define ONCHIP_MEMORY2_0_SPAN 40960
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#define ONCHIP_MEMORY2_0_TYPE "altera_avalon_onchip_memory2"
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#define ONCHIP_MEMORY2_0_WRITABLE 1
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/*
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* pio_0 configuration
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*
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*/
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#define ALT_MODULE_CLASS_pio_0 altera_avalon_pio
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#define PIO_0_BASE 0x210e0
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#define PIO_0_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_0_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_0_CAPTURE 0
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#define PIO_0_DATA_WIDTH 16
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#define PIO_0_DO_TEST_BENCH_WIRING 0
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#define PIO_0_DRIVEN_SIM_VALUE 0
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#define PIO_0_EDGE_TYPE "NONE"
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#define PIO_0_FREQ 27000000
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#define PIO_0_HAS_IN 0
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#define PIO_0_HAS_OUT 1
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#define PIO_0_HAS_TRI 0
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#define PIO_0_IRQ -1
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#define PIO_0_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define PIO_0_IRQ_TYPE "NONE"
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#define PIO_0_NAME "/dev/pio_0"
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#define PIO_0_RESET_VALUE 0
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#define PIO_0_SPAN 16
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#define PIO_0_TYPE "altera_avalon_pio"
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/*
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* pio_1 configuration
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*
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*/
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#define ALT_MODULE_CLASS_pio_1 altera_avalon_pio
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#define PIO_1_BASE 0x210d0
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#define PIO_1_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_1_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_1_CAPTURE 0
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#define PIO_1_DATA_WIDTH 32
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#define PIO_1_DO_TEST_BENCH_WIRING 0
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#define PIO_1_DRIVEN_SIM_VALUE 0
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#define PIO_1_EDGE_TYPE "NONE"
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#define PIO_1_FREQ 27000000
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#define PIO_1_HAS_IN 1
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#define PIO_1_HAS_OUT 0
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#define PIO_1_HAS_TRI 0
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#define PIO_1_IRQ -1
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#define PIO_1_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define PIO_1_IRQ_TYPE "NONE"
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#define PIO_1_NAME "/dev/pio_1"
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#define PIO_1_RESET_VALUE 0
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#define PIO_1_SPAN 16
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#define PIO_1_TYPE "altera_avalon_pio"
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/*
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* pio_2 configuration
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*
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*/
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#define ALT_MODULE_CLASS_pio_2 altera_avalon_pio
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#define PIO_2_BASE 0x210c0
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#define PIO_2_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_2_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_2_CAPTURE 0
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#define PIO_2_DATA_WIDTH 32
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#define PIO_2_DO_TEST_BENCH_WIRING 0
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#define PIO_2_DRIVEN_SIM_VALUE 0
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#define PIO_2_EDGE_TYPE "NONE"
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#define PIO_2_FREQ 27000000
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#define PIO_2_HAS_IN 1
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#define PIO_2_HAS_OUT 0
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#define PIO_2_HAS_TRI 0
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#define PIO_2_IRQ -1
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#define PIO_2_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define PIO_2_IRQ_TYPE "NONE"
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#define PIO_2_NAME "/dev/pio_2"
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#define PIO_2_RESET_VALUE 0
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#define PIO_2_SPAN 16
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#define PIO_2_TYPE "altera_avalon_pio"
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/*
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* pio_3 configuration
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*
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*/
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#define ALT_MODULE_CLASS_pio_3 altera_avalon_pio
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#define PIO_3_BASE 0x210b0
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#define PIO_3_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_3_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_3_CAPTURE 0
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#define PIO_3_DATA_WIDTH 32
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#define PIO_3_DO_TEST_BENCH_WIRING 0
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#define PIO_3_DRIVEN_SIM_VALUE 0
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#define PIO_3_EDGE_TYPE "NONE"
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#define PIO_3_FREQ 27000000
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#define PIO_3_HAS_IN 0
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#define PIO_3_HAS_OUT 1
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#define PIO_3_HAS_TRI 0
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#define PIO_3_IRQ -1
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#define PIO_3_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define PIO_3_IRQ_TYPE "NONE"
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#define PIO_3_NAME "/dev/pio_3"
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#define PIO_3_RESET_VALUE 0
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#define PIO_3_SPAN 16
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#define PIO_3_TYPE "altera_avalon_pio"
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/*
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* pio_4 configuration
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*
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*/
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#define ALT_MODULE_CLASS_pio_4 altera_avalon_pio
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#define PIO_4_BASE 0x210a0
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#define PIO_4_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_4_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_4_CAPTURE 0
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#define PIO_4_DATA_WIDTH 32
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#define PIO_4_DO_TEST_BENCH_WIRING 0
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#define PIO_4_DRIVEN_SIM_VALUE 0
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#define PIO_4_EDGE_TYPE "NONE"
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#define PIO_4_FREQ 27000000
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#define PIO_4_HAS_IN 0
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#define PIO_4_HAS_OUT 1
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#define PIO_4_HAS_TRI 0
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#define PIO_4_IRQ -1
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#define PIO_4_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define PIO_4_IRQ_TYPE "NONE"
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#define PIO_4_NAME "/dev/pio_4"
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#define PIO_4_RESET_VALUE 0
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#define PIO_4_SPAN 16
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#define PIO_4_TYPE "altera_avalon_pio"
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/*
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* pio_5 configuration
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*
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*/
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#define ALT_MODULE_CLASS_pio_5 altera_avalon_pio
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#define PIO_5_BASE 0x21090
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#define PIO_5_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_5_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_5_CAPTURE 0
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#define PIO_5_DATA_WIDTH 32
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#define PIO_5_DO_TEST_BENCH_WIRING 0
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#define PIO_5_DRIVEN_SIM_VALUE 0
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#define PIO_5_EDGE_TYPE "NONE"
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#define PIO_5_FREQ 27000000
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#define PIO_5_HAS_IN 0
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#define PIO_5_HAS_OUT 1
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#define PIO_5_HAS_TRI 0
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#define PIO_5_IRQ -1
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#define PIO_5_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define PIO_5_IRQ_TYPE "NONE"
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#define PIO_5_NAME "/dev/pio_5"
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#define PIO_5_RESET_VALUE 0
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#define PIO_5_SPAN 16
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#define PIO_5_TYPE "altera_avalon_pio"
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/*
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* pio_6 configuration
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|
*
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*/
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#define ALT_MODULE_CLASS_pio_6 altera_avalon_pio
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#define PIO_6_BASE 0x21080
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#define PIO_6_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_6_BIT_MODIFYING_OUTPUT_REGISTER 0
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#define PIO_6_CAPTURE 0
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#define PIO_6_DATA_WIDTH 32
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#define PIO_6_DO_TEST_BENCH_WIRING 0
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#define PIO_6_DRIVEN_SIM_VALUE 0
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#define PIO_6_EDGE_TYPE "NONE"
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#define PIO_6_FREQ 27000000
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#define PIO_6_HAS_IN 0
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#define PIO_6_HAS_OUT 1
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#define PIO_6_HAS_TRI 0
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#define PIO_6_IRQ -1
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#define PIO_6_IRQ_INTERRUPT_CONTROLLER_ID -1
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#define PIO_6_IRQ_TYPE "NONE"
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#define PIO_6_NAME "/dev/pio_6"
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#define PIO_6_RESET_VALUE 0
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#define PIO_6_SPAN 16
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#define PIO_6_TYPE "altera_avalon_pio"
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/*
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* pio_7 configuration
|
|
*
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|
*/
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#define ALT_MODULE_CLASS_pio_7 altera_avalon_pio
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#define PIO_7_BASE 0x21070
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#define PIO_7_BIT_CLEARING_EDGE_REGISTER 0
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#define PIO_7_BIT_MODIFYING_OUTPUT_REGISTER 0
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|
#define PIO_7_CAPTURE 0
|
|
#define PIO_7_DATA_WIDTH 32
|
|
#define PIO_7_DO_TEST_BENCH_WIRING 0
|
|
#define PIO_7_DRIVEN_SIM_VALUE 0
|
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#define PIO_7_EDGE_TYPE "NONE"
|
|
#define PIO_7_FREQ 27000000
|
|
#define PIO_7_HAS_IN 1
|
|
#define PIO_7_HAS_OUT 0
|
|
#define PIO_7_HAS_TRI 0
|
|
#define PIO_7_IRQ -1
|
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#define PIO_7_IRQ_INTERRUPT_CONTROLLER_ID -1
|
|
#define PIO_7_IRQ_TYPE "NONE"
|
|
#define PIO_7_NAME "/dev/pio_7"
|
|
#define PIO_7_RESET_VALUE 0
|
|
#define PIO_7_SPAN 16
|
|
#define PIO_7_TYPE "altera_avalon_pio"
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|
|
|
|
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/*
|
|
* pio_8 configuration
|
|
*
|
|
*/
|
|
|
|
#define ALT_MODULE_CLASS_pio_8 altera_avalon_pio
|
|
#define PIO_8_BASE 0x21060
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|
#define PIO_8_BIT_CLEARING_EDGE_REGISTER 0
|
|
#define PIO_8_BIT_MODIFYING_OUTPUT_REGISTER 0
|
|
#define PIO_8_CAPTURE 0
|
|
#define PIO_8_DATA_WIDTH 32
|
|
#define PIO_8_DO_TEST_BENCH_WIRING 0
|
|
#define PIO_8_DRIVEN_SIM_VALUE 0
|
|
#define PIO_8_EDGE_TYPE "NONE"
|
|
#define PIO_8_FREQ 27000000
|
|
#define PIO_8_HAS_IN 1
|
|
#define PIO_8_HAS_OUT 0
|
|
#define PIO_8_HAS_TRI 0
|
|
#define PIO_8_IRQ -1
|
|
#define PIO_8_IRQ_INTERRUPT_CONTROLLER_ID -1
|
|
#define PIO_8_IRQ_TYPE "NONE"
|
|
#define PIO_8_NAME "/dev/pio_8"
|
|
#define PIO_8_RESET_VALUE 0
|
|
#define PIO_8_SPAN 16
|
|
#define PIO_8_TYPE "altera_avalon_pio"
|
|
|
|
|
|
/*
|
|
* timer_0 configuration
|
|
*
|
|
*/
|
|
|
|
#define ALT_MODULE_CLASS_timer_0 altera_avalon_timer
|
|
#define TIMER_0_ALWAYS_RUN 0
|
|
#define TIMER_0_BASE 0x20000
|
|
#define TIMER_0_COUNTER_SIZE 32
|
|
#define TIMER_0_FIXED_PERIOD 0
|
|
#define TIMER_0_FREQ 27000000
|
|
#define TIMER_0_IRQ 0
|
|
#define TIMER_0_IRQ_INTERRUPT_CONTROLLER_ID 0
|
|
#define TIMER_0_LOAD_VALUE 26
|
|
#define TIMER_0_MULT 1.0E-6
|
|
#define TIMER_0_NAME "/dev/timer_0"
|
|
#define TIMER_0_PERIOD 1
|
|
#define TIMER_0_PERIOD_UNITS "us"
|
|
#define TIMER_0_RESET_OUTPUT 0
|
|
#define TIMER_0_SNAPSHOT 1
|
|
#define TIMER_0_SPAN 32
|
|
#define TIMER_0_TICKS_PER_SEC 1000000
|
|
#define TIMER_0_TIMEOUT_PULSE_OUTPUT 0
|
|
#define TIMER_0_TYPE "altera_avalon_timer"
|
|
|
|
#endif /* __SYSTEM_H_ */
|