mirror of https://github.com/marqs85/ossc.git
496 lines
15 KiB
Verilog
496 lines
15 KiB
Verilog
//
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// Copyright (C) 2015-2019 Markus Hiienkari <mhiienka@niksula.hut.fi>
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//
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// This file is part of Open Source Scan Converter project.
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//
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// This program is free software: you can redistribute it and/or modify
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// it under the terms of the GNU General Public License as published by
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// the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// This program is distributed in the hope that it will be useful,
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// but WITHOUT ANY WARRANTY; without even the implied warranty of
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// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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// GNU General Public License for more details.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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//
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//`define DEBUG
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`define PO_RESET_WIDTH 27 //1us
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module ossc (
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input clk27,
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inout scl,
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inout sda,
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input ir_rx,
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input [1:0] btn,
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input [1:0] cfg,
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input TVP_PCLK_i,
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input [7:0] TVP_R_i,
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input [7:0] TVP_G_i,
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input [7:0] TVP_B_i,
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input TVP_HS_i,
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input TVP_SOG_i,
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input TVP_VSYNC_i,
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output HDMI_TX_PCLK,
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output reg [7:0] HDMI_TX_RD,
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output reg [7:0] HDMI_TX_GD,
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output reg [7:0] HDMI_TX_BD,
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output reg HDMI_TX_DE,
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output reg HDMI_TX_HS,
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output reg HDMI_TX_VS,
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input HDMI_TX_INT_N,
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output hw_reset_n,
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output LED_G,
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inout LED_R,
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output LCD_RS,
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output LCD_CS_N,
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output LCD_BL,
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output SD_CLK,
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inout SD_CMD,
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inout [3:0] SD_DAT
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);
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wire [31:0] sys_ctrl;
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wire lt_active = sys_ctrl[15];
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wire lt_armed = sys_ctrl[14];
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wire [1:0] lt_mode = sys_ctrl[13:12];
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wire tvp_vsync_type = sys_ctrl[10];
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wire pll_bypass = sys_ctrl[9];
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wire remote_event = sys_ctrl[8];
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assign SD_DAT[3] = sys_ctrl[7]; //SD_SPI_SS_N
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assign LCD_CS_N = sys_ctrl[6];
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assign LCD_RS = sys_ctrl[5];
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wire lcd_bl_on = sys_ctrl[4]; //hw_reset_n in v1.2 PCB
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wire [1:0] lcd_bl_time = sys_ctrl[3:2];
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wire enable_sc = sys_ctrl[1];
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assign hw_reset_n = sys_ctrl[0]; //HDMI_TX_RST_N in v1.2 PCB
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wire [31:0] hv_in_config, hv_in_config2, hv_in_config3, hv_out_config, hv_out_config2, hv_out_config3, xy_out_config, xy_out_config2;
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wire [31:0] misc_config, sl_config, sl_config2, sl_config3;
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wire pll_clkout, pll_clkswitch, pll_locked;
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wire clkmux_clkout;
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wire [15:0] ir_code;
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wire [7:0] ir_code_cnt;
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wire [7:0] R_sc, G_sc, B_sc;
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wire HSYNC_sc, VSYNC_sc, DE_sc;
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wire pll_areset, pll_scanclk, pll_scanclkena, pll_configupdate, pll_scandata, pll_scandone, pll_activeclock;
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wire PCLK_sc;
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wire pclk_out = PCLK_sc;
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reg [7:0] po_reset_ctr = 0;
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reg po_reset_n = 1'b0;
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wire jtagm_reset_req;
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wire sys_reset_n = (po_reset_n & ~jtagm_reset_req);
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reg [7:0] TVP_R, TVP_G, TVP_B;
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reg TVP_HS, TVP_VS, TVP_FID;
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reg TVP_VS_sync1_reg, TVP_VS_sync2_reg;
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reg TVP_SOG_sync1_reg, TVP_SOG_sync2_reg, TVP_SOG_prev;
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reg TVP_HSYNC_sync1_reg, TVP_HSYNC_sync2_reg;
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reg TVP_VSYNC_sync1_reg, TVP_VSYNC_sync2_reg;
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reg [1:0] btn_L, btn_LL;
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reg ir_rx_L, ir_rx_LL, HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL;
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reg vsync_flag_sync1_reg, vsync_flag_sync2_reg;
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reg [1:0] cfg_reg;
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reg cfg_stored;
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wire TVP_SOG_ALT_i;
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wire TVP_HSYNC_i = cfg_reg[1] ? TVP_SOG_i : TVP_SOG_ALT_i;
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reg [23:0] resync_led_ctr, warn_pll_lock_lost;
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reg resync_strobe_sync1_reg, resync_strobe_sync2_reg, resync_strobe_prev;
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wire resync_strobe_i;
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wire resync_strobe = resync_strobe_sync2_reg;
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wire [31:0] controls = {ir_code_cnt, 3'b000, vsync_flag_sync2_reg, pll_activeclock, cfg_reg[0], btn_LL, ir_code};
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wire lt_sensor = btn_LL[1];
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wire lt_trigger = DE_sc & G_sc[0];
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wire [1:0] lt_mode_synced;
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wire [15:0] lt_lat_result;
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wire [11:0] lt_stb_result;
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wire lt_trig_waiting;
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wire lt_finished;
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reg remove_event_prev;
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reg [14:0] to_ctr, to_ctr_ms;
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wire lcd_bl_timeout;
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wire [1:0] osd_color;
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wire osd_enable_pre;
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wire osd_enable = osd_enable_pre & ~lt_active;
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wire [10:0] xpos_sc;
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wire [10:0] ypos_sc;
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wire resync_indicator = (warn_pll_lock_lost != 0) | (resync_led_ctr != 0);
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wire LED_R_i = lt_active ? lt_trig_waiting : resync_indicator;
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assign LED_G = lt_active ? ~lt_sensor : (ir_code == 0) & (~resync_indicator | cfg_reg[1]);
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assign LCD_BL = lcd_bl_on ? (~lcd_bl_timeout | lt_active) : 1'b0;
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assign HDMI_TX_PCLK = pclk_out;
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// TVP7002 RGB digitizer
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always @(posedge TVP_PCLK_i) begin
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TVP_R <= TVP_R_i;
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TVP_G <= TVP_G_i;
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TVP_B <= TVP_B_i;
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TVP_HS <= TVP_HS_i;
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TVP_VS <= TVP_VSYNC_i;
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// sync to pclk
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TVP_SOG_sync1_reg <= TVP_HSYNC_i;
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TVP_SOG_sync2_reg <= TVP_SOG_sync1_reg;
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TVP_SOG_prev <= TVP_SOG_sync2_reg;
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TVP_VS_sync1_reg <= TVP_VSYNC_i;
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TVP_VS_sync2_reg <= TVP_VS_sync1_reg;
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end
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always @(posedge clk27) begin
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// sync to always-running fixed meas clk
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TVP_HSYNC_sync1_reg <= TVP_HSYNC_i;
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TVP_HSYNC_sync2_reg <= TVP_HSYNC_sync1_reg;
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TVP_VSYNC_sync1_reg <= TVP_VSYNC_i;
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TVP_VSYNC_sync2_reg <= TVP_VSYNC_sync1_reg;
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end
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wire [7:0] TVP_R_post, TVP_G_post, TVP_B_post;
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wire TVP_HSYNC_post, TVP_VSYNC_post, TVP_DE_post, TVP_FID_post, TVP_datavalid_post;
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wire TVP_fe_interlace, TVP_fe_frame_change, TVP_sof_scaler, TVP_sync_active;
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wire [19:0] TVP_fe_pcnt_frame;
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wire [7:0] TVP_hsync_width;
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wire [10:0] TVP_fe_vtotal, TVP_fe_xpos, TVP_fe_ypos;
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tvp7002_frontend u_tvp_frontend (
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.PCLK_i(TVP_PCLK_i),
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.CLK_MEAS_i(clk27),
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.reset_n(sys_reset_n),
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.R_i(TVP_R),
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.G_i(TVP_G),
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.B_i(TVP_B),
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.HS_i(TVP_HS),
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.VS_i(TVP_VS_sync2_reg),
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.HSYNC_i(TVP_HSYNC_sync2_reg),
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.VSYNC_i(TVP_VSYNC_sync2_reg),
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.DE_i(1'b0),
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.FID_i(1'b0),
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.sogref_update_i(TVP_SOG_prev & ~TVP_SOG_sync2_reg),
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.vsync_i_type(tvp_vsync_type),
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.hv_in_config(hv_in_config),
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.hv_in_config2(hv_in_config2),
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.hv_in_config3(hv_in_config3),
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.misc_config(misc_config),
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.R_o(TVP_R_post),
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.G_o(TVP_G_post),
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.B_o(TVP_B_post),
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.HSYNC_o(TVP_HSYNC_post),
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.VSYNC_o(TVP_VSYNC_post),
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.DE_o(TVP_DE_post),
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.FID_o(TVP_FID_post),
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.interlace_flag(TVP_fe_interlace),
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.datavalid_o(TVP_datavalid_post),
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.xpos_o(TVP_fe_xpos),
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.ypos_o(TVP_fe_ypos),
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.vtotal(TVP_fe_vtotal),
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.frame_change(TVP_fe_frame_change),
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.sof_scaler(TVP_sof_scaler),
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.pcnt_frame(TVP_fe_pcnt_frame),
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.hsync_width(TVP_hsync_width),
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.sync_active(TVP_sync_active)
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);
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// Insert synchronizers to async inputs (synchronize to CPU clock)
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always @(posedge clk27 or negedge po_reset_n)
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begin
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if (!po_reset_n) begin
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{btn_L, btn_LL} <= '0;
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{ir_rx_L, ir_rx_LL} <= '0;
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{HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL} <= '0;
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{cfg_stored, cfg_reg} <= '0;
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end else begin
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{btn_L, btn_LL} <= {btn, btn_L};
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{ir_rx_L, ir_rx_LL} <= {ir_rx, ir_rx_L};
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{HDMI_TX_INT_N_L, HDMI_TX_INT_N_LL} <= {HDMI_TX_INT_N, HDMI_TX_INT_N_L};
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if (!cfg_stored)
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cfg_reg <= cfg;
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cfg_stored <= 1'b1;
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end
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end
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// Power-on reset pulse generation (not strictly necessary)
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always @(posedge clk27)
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begin
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if (po_reset_ctr == `PO_RESET_WIDTH)
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po_reset_n <= 1'b1;
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else
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po_reset_ctr <= po_reset_ctr + 1'b1;
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end
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// Sync vsync flag to CPU clock
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always @(posedge clk27) begin
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{vsync_flag_sync1_reg, vsync_flag_sync2_reg} <= {~VSYNC_sc, vsync_flag_sync1_reg};
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end
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// LCD backlight timeout counters
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always @(posedge clk27)
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begin
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if (remote_event != remove_event_prev) begin
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to_ctr <= 15'd0;
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to_ctr_ms <= 15'd0;
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end else begin
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if (to_ctr == 27000-1) begin
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to_ctr <= 0;
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if (to_ctr_ms < 15'h7fff)
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to_ctr_ms <= to_ctr_ms + 1'b1;
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end else begin
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to_ctr <= to_ctr + 1'b1;
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end
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end
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case (lcd_bl_time)
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default: lcd_bl_timeout <= 0; //off
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2'b01: lcd_bl_timeout <= (to_ctr_ms >= 3000); //3s
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2'b10: lcd_bl_timeout <= (to_ctr_ms >= 10000); //10s
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2'b11: lcd_bl_timeout <= (to_ctr_ms >= 30000); //30s
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endcase
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remove_event_prev <= remote_event;
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end
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// Generate a warning signal from sync lock loss
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always @(posedge clk27) begin
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if (enable_sc) begin
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if (~resync_strobe_prev & resync_strobe) begin
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resync_led_ctr <= {24{1'b1}};
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end else if (resync_led_ctr > 0) begin
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resync_led_ctr <= resync_led_ctr - 1'b1;
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end
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end
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resync_strobe_sync1_reg <= resync_strobe_i;
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resync_strobe_sync2_reg <= resync_strobe_sync1_reg;
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resync_strobe_prev <= resync_strobe_sync2_reg;
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end
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// Generate a warning signal from PLL lock loss
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always @(posedge clk27 or negedge sys_reset_n)
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begin
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if (!sys_reset_n) begin
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warn_pll_lock_lost <= 1'b0;
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end else begin
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if (~pll_areset & ~pll_locked)
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warn_pll_lock_lost <= 1;
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else if (warn_pll_lock_lost != 0)
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warn_pll_lock_lost <= warn_pll_lock_lost + 1'b1;
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end
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end
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// Control PLL reference clock switchover
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always @(posedge clk27)
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begin
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pll_clkswitch <= (pll_activeclock != enable_sc);
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end
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// Output registers
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always @(posedge pclk_out) begin
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if (osd_enable) begin
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if (osd_color == 2'h0) begin
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{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h000000;
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end else if (osd_color == 2'h1) begin
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{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'h0000ff;
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end else if (osd_color == 2'h2) begin
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{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffff00;
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end else begin
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{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= 24'hffffff;
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end
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end else begin
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{HDMI_TX_RD, HDMI_TX_GD, HDMI_TX_BD} <= {R_sc, G_sc, B_sc};
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end
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HDMI_TX_HS <= HSYNC_sc;
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HDMI_TX_VS <= VSYNC_sc;
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HDMI_TX_DE <= DE_sc;
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end
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// A modified <= v1.7 board uses LED_R for TVP_HSYNC input
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ALT_IOBUF led_r_iobuf (.i(LED_R_i), .oe(cfg_reg[1]), .o(TVP_SOG_ALT_i), .io(LED_R));
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pll_2x pll_pclk (
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.areset(pll_areset),
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.clkswitch(pll_clkswitch),
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.configupdate(pll_configupdate),
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.inclk0(clk27), // set videogen clock to primary (power-on default) since both reference clocks must be running during switchover
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.inclk1(TVP_PCLK_i), // is the secondary input clock fully compensated?
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.scanclk(pll_scanclk),
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.scanclkena(pll_scanclkena),
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.scandata(pll_scandata),
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.activeclock(pll_activeclock),
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.c0(pll_clkout),
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.locked(pll_locked),
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.scandataout(),
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.scandone(pll_scandone)
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);
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cycloneive_clkctrl clkctrl1 (
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.clkselect(pll_bypass ? 2'h0 : 2'h2),
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.ena(1'b1),
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.inclk({1'b0, pll_clkout, 1'b0, TVP_PCLK_i}), // fitter forbids using both clk27 and pclk_1x here since they're on opposite sides
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.outclk(clkmux_clkout)
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// synopsys translate_off
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,
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.devclrn(1'b1),
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.devpor(1'b1)
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// synopsys translate_on
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);
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defparam
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clkctrl1.clock_type = "Global Clock",
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clkctrl1.ena_register_mode = "falling edge",
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clkctrl1.lpm_type = "cycloneive_clkctrl";
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sys sys_inst(
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.clk_clk (clk27),
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.reset_reset_n (sys_reset_n),
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.pulpino_0_config_testmode_i (1'b0),
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.pulpino_0_config_fetch_enable_i (1'b1),
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.pulpino_0_config_clock_gating_i (1'b0),
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.pulpino_0_config_boot_addr_i (32'h00010000),
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.master_0_master_reset_reset (jtagm_reset_req),
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.i2c_opencores_0_export_scl_pad_io (scl),
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.i2c_opencores_0_export_sda_pad_io (sda),
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.i2c_opencores_0_export_spi_miso_pad_i (1'b0),
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.i2c_opencores_1_export_scl_pad_io (SD_CLK),
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.i2c_opencores_1_export_sda_pad_io (SD_CMD),
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.i2c_opencores_1_export_spi_miso_pad_i (SD_DAT[0]),
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.pio_0_sys_ctrl_out_export (sys_ctrl),
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.pio_1_controls_in_export (controls),
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.sc_config_0_sc_if_fe_status_i ({19'h0, TVP_sync_active, TVP_fe_interlace, TVP_fe_vtotal}),
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.sc_config_0_sc_if_fe_status2_i ({4'h0, TVP_hsync_width, TVP_fe_pcnt_frame}),
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.sc_config_0_sc_if_lt_status_i (32'h00000000),
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.sc_config_0_sc_if_hv_in_config_o (hv_in_config),
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.sc_config_0_sc_if_hv_in_config2_o (hv_in_config2),
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.sc_config_0_sc_if_hv_in_config3_o (hv_in_config3),
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.sc_config_0_sc_if_hv_out_config_o (hv_out_config),
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.sc_config_0_sc_if_hv_out_config2_o (hv_out_config2),
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.sc_config_0_sc_if_hv_out_config3_o (hv_out_config3),
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.sc_config_0_sc_if_xy_out_config_o (xy_out_config),
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.sc_config_0_sc_if_xy_out_config2_o (xy_out_config2),
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.sc_config_0_sc_if_misc_config_o (misc_config),
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.sc_config_0_sc_if_sl_config_o (sl_config),
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.sc_config_0_sc_if_sl_config2_o (sl_config2),
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.sc_config_0_sc_if_sl_config3_o (sl_config3),
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.osd_generator_0_osd_if_vclk (PCLK_sc),
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.osd_generator_0_osd_if_xpos (xpos_sc),
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.osd_generator_0_osd_if_ypos (ypos_sc),
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.osd_generator_0_osd_if_osd_enable (osd_enable_pre),
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.osd_generator_0_osd_if_osd_color (osd_color),
|
|
.pll_reconfig_0_pll_reconfig_if_areset (pll_areset),
|
|
.pll_reconfig_0_pll_reconfig_if_scanclk (pll_scanclk),
|
|
.pll_reconfig_0_pll_reconfig_if_scanclkena (pll_scanclkena),
|
|
.pll_reconfig_0_pll_reconfig_if_configupdate (pll_configupdate),
|
|
.pll_reconfig_0_pll_reconfig_if_scandata (pll_scandata),
|
|
.pll_reconfig_0_pll_reconfig_if_scandone (pll_scandone)
|
|
);
|
|
|
|
scanconverter #(
|
|
.EMIF_ENABLE(0),
|
|
.NUM_LINE_BUFFERS(2)
|
|
) scanconverter_inst (
|
|
.PCLK_CAP_i(TVP_PCLK_i),
|
|
.PCLK_OUT_i(clkmux_clkout),
|
|
.reset_n(hw_reset_n), //TODO: sync to pclk_capture
|
|
.R_i(TVP_R_post),
|
|
.G_i(TVP_G_post),
|
|
.B_i(TVP_B_post),
|
|
.HSYNC_i(TVP_HSYNC_post),
|
|
.VSYNC_i(TVP_VSYNC_post),
|
|
.DE_i(TVP_DE_post),
|
|
.FID_i(TVP_FID_post),
|
|
.datavalid_i(TVP_datavalid_post),
|
|
.interlaced_in_i(TVP_fe_interlace),
|
|
.frame_change_i(TVP_fe_frame_change),
|
|
.xpos_i(TVP_fe_xpos),
|
|
.ypos_i(TVP_fe_ypos),
|
|
.h_in_active(hv_in_config[23:12]),
|
|
.hv_out_config(hv_out_config),
|
|
.hv_out_config2(hv_out_config2),
|
|
.hv_out_config3(hv_out_config3),
|
|
.xy_out_config(xy_out_config),
|
|
.xy_out_config2(xy_out_config2),
|
|
.misc_config(misc_config),
|
|
.sl_config(sl_config),
|
|
.sl_config2(sl_config2),
|
|
.sl_config3(sl_config3),
|
|
.testpattern_enable(~enable_sc),
|
|
.lb_enable(enable_sc),
|
|
.ext_sync_mode(1'b0),
|
|
.ext_frame_change_i(1'b0),
|
|
.ext_R_i(8'h00),
|
|
.ext_G_i(8'h00),
|
|
.ext_B_i(8'h00),
|
|
.PCLK_o(PCLK_sc),
|
|
.R_o(R_sc),
|
|
.G_o(G_sc),
|
|
.B_o(B_sc),
|
|
.HSYNC_o(HSYNC_sc),
|
|
.VSYNC_o(VSYNC_sc),
|
|
.DE_o(DE_sc),
|
|
.xpos_o(xpos_sc),
|
|
.ypos_o(ypos_sc),
|
|
.resync_strobe(resync_strobe_i),
|
|
.emif_br_clk(1'b0),
|
|
.emif_br_reset(1'b0),
|
|
.emif_rd_addr(),
|
|
.emif_rd_read(),
|
|
.emif_rd_rdata(0),
|
|
.emif_rd_waitrequest(0),
|
|
.emif_rd_readdatavalid(0),
|
|
.emif_rd_burstcount(),
|
|
.emif_wr_addr(),
|
|
.emif_wr_write(),
|
|
.emif_wr_wdata(),
|
|
.emif_wr_waitrequest(0),
|
|
.emif_wr_burstcount()
|
|
);
|
|
|
|
ir_rcv ir0 (
|
|
.clk27 (clk27),
|
|
.reset_n (po_reset_n),
|
|
.ir_rx (ir_rx_LL),
|
|
.ir_code (ir_code),
|
|
.ir_code_ack (),
|
|
.ir_code_cnt (ir_code_cnt)
|
|
);
|
|
|
|
/*lat_tester lt0 (
|
|
.clk27 (clk27),
|
|
.pclk (PCLK_sc),
|
|
.active (lt_active),
|
|
.armed (lt_armed),
|
|
.sensor (lt_sensor),
|
|
.trigger (lt_trigger),
|
|
.VSYNC_in (VSYNC_sc),
|
|
.mode_in (lt_mode),
|
|
.mode_synced (lt_mode_synced),
|
|
.lat_result (lt_lat_result),
|
|
.stb_result (lt_stb_result),
|
|
.trig_waiting (lt_trig_waiting),
|
|
.finished (lt_finished)
|
|
);*/
|
|
|
|
endmodule
|