mirror of https://github.com/marqs85/ossc.git
57 lines
2.3 KiB
Verilog
57 lines
2.3 KiB
Verilog
// (C) 2001-2015 Altera Corporation. All rights reserved.
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// Your use of Altera Corporation's design tools, logic functions and other
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// software and tools, and its AMPP partner logic functions, and any output
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// files any of the foregoing (including device programming or simulation
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// files), and any associated documentation or information are expressly subject
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// to the terms and conditions of the Altera Program License Subscription
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// Agreement, Altera MegaCore Function License Agreement, or other applicable
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// license agreement, including, without limitation, that your use is for the
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// sole purpose of programming logic devices manufactured by Altera and sold by
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// Altera or its authorized distributors. Please refer to the applicable
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// agreement for further details.
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//Legal Notice: (C)2010 Altera Corporation. All rights reserved. Your
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//use of Altera Corporation's design tools, logic functions and other
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//software and tools, and its AMPP partner logic functions, and any
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//output files any of the foregoing (including device programming or
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//simulation files), and any associated documentation or information are
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//expressly subject to the terms and conditions of the Altera Program
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//License Subscription Agreement or other applicable license agreement,
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//including, without limitation, that your use is for the sole purpose
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//of programming logic devices manufactured by Altera and sold by Altera
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//or its authorized distributors. Please refer to the applicable
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//agreement for further details.
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// synthesis translate_off
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`timescale 1ns / 1ps
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// synthesis translate_on
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// turn off superfluous verilog processor warnings
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// altera message_level Level1
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// altera message_off 10034 10035 10036 10037 10230 10240 10030
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module endianconverter_qsys (
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// inputs:
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dataa,
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datab,
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// outputs:
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result
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)
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;
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output [ 31: 0] result;
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input [ 31: 0] dataa;
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input [ 31: 0] datab;
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wire [ 31: 0] result;
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//s1, which is an e_custom_instruction_slave
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assign result[7 : 0] = dataa[31 : 24];
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assign result[15 : 8] = dataa[23 : 16];
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assign result[23 : 16] = dataa[15 : 8];
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assign result[31 : 24] = dataa[7 : 0];
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endmodule
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