mirror of https://github.com/marqs85/ossc.git
85 lines
2.6 KiB
Tcl
85 lines
2.6 KiB
Tcl
# (C) 2001-2015 Altera Corporation. All rights reserved.
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# Your use of Altera Corporation's design tools, logic functions and other
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# software and tools, and its AMPP partner logic functions, and any output
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# files any of the foregoing (including device programming or simulation
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# files), and any associated documentation or information are expressly subject
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# to the terms and conditions of the Altera Program License Subscription
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# Agreement, Altera MegaCore Function License Agreement, or other applicable
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# license agreement, including, without limitation, that your use is for the
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# sole purpose of programming logic devices manufactured by Altera and sold by
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# Altera or its authorized distributors. Please refer to the applicable
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# agreement for further details.
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# TCL File Generated by Component Editor 10.1
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# Tue Aug 17 15:04:48 MYT 2010
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# DO NOT MODIFY
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# +-----------------------------------
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# |
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# |
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# | ./converter_0.v syn, sim
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | request TCL package from ACDS 10.1
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# |
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package require -exact sopc 10.1
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | module altera_nios_custom_instr_endian_converter
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# |
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set_module_property NAME altera_nios_custom_instr_endianconverter
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set_module_property VERSION 17.1
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set_module_property INTERNAL false
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set_module_property GROUP "Custom Instruction Modules"
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set_module_property AUTHOR "Altera Corporation"
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set_module_property DISPLAY_NAME "Endian Converter"
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set_module_property HIDE_FROM_SOPC true
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set_module_property TOP_LEVEL_HDL_FILE endianconverter_qsys.v
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set_module_property TOP_LEVEL_HDL_MODULE endianconverter_qsys
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set_module_property INSTANTIATE_IN_SYSTEM_MODULE true
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set_module_property SIMULATION_MODEL_IN_VHDL true
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set_module_property EDITABLE false
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set_module_property ANALYZE_HDL FALSE
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | files
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# |
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add_file endianconverter_qsys.v {SYNTHESIS SIMULATION}
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | parameters
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# |
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | display items
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# |
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# |
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# +-----------------------------------
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# +-----------------------------------
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# | connection point s1
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# |
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add_interface s1 nios_custom_instruction end
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set_interface_property s1 clockCycle 1
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set_interface_property s1 operands 1
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set_interface_property s1 ENABLED true
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add_interface_port s1 dataa dataa Input 32
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add_interface_port s1 datab datab Input 32
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add_interface_port s1 result result Output 32
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# |
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# +-----------------------------------
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