mirror of https://github.com/marqs85/ossc.git
315 lines
12 KiB
Verilog
315 lines
12 KiB
Verilog
/*
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Legal Notice: (C)2006 Altera Corporation. All rights reserved. Your
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use of Altera Corporation's design tools, logic functions and other
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software and tools, and its AMPP partner logic functions, and any
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output files any of the foregoing (including device programming or
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simulation files), and any associated documentation or information are
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expressly subject to the terms and conditions of the Altera Program
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License Subscription Agreement or other applicable license agreement,
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including, without limitation, that your use is for the sole purpose
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of programming logic devices manufactured by Altera and sold by Altera
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or its authorized distributors. Please refer to the applicable
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agreement for further details.
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*/
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/*
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This component supports 8, 16, 24, and 32 bit little endian data
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and any CRC standard between 1 to 128 bits. Through parameterization
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you can change the CRC standard which will take effect after you
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regenerate your system in SOPC Builder.
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Register Map:
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000 -> reset the CRC peripheral to the inital value (data and byte enables ignored)
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001 -> data write between 1-32 bits
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010 -> reserved
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011 -> reserved
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100 -> read bits 1-32 of the crc result
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101 -> read bits 33-64 of the crc result (where applicable)
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110 -> read bits 65-96 of the crc result (where applicable)
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111 -> read bits 97-128 of the crc result (where applicable)
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Write latency = 0
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Read latency = 1
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Note: This component uses four blocks of eight bits of data in cascade.
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To improve the timing of logic you can create seperate cascades
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for 8, 16, 24, and 32 bit data which will allow for smaller area
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and a shorter combinational depth. Since CRC logic consumes power
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even when not in use you can also add a logic disable feature using
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the chipselect signal. Even though the registered CRC value is
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held constant when the circuit is not in use the input data will
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change during this time and cause the CRC cascade logic to react.
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*/
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module CRC_Component (clk,
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reset,
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address,
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writedata,
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byteenable,
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write,
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read,
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chipselect,
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readdata);
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/*
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Using these parameters you can create any CRC ranging from one bit (parity checker)
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up to 128 bits. The following list describes the function of each parameter:
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crc_width:
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The width of the registered CRC result, this value is typically apart of
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the name of the standard (CRC32 is 32 bits wide). Adjusting this value
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will impact the logic resource usage.
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polynomial_initial:
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The initial value set for the CRC result register. By writing any data to address 0
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this value will be stored in the result register thereby clearing any previously existing
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value. This value must be the same width as 'crc_width'
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polynomial:
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This is the divisor value used on the input data. Typically shown in polynomial format
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the value symbolizes the placement of xor operation on the input data. In synthesis, the
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polynomial bits that are '1' will create a not gate, whereas the bits that are '0' will
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simply create a wire. Even with 32 stages of these operations cascaded, the simple logic
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will not become a significant factor on logic utilization or fmax. This value must be the
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same width as 'crc_width'
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reflected_input:
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Some CRC standards require that all the input bits be reflected around the center point.
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This option is enabled with '1' and disabled with '0'. Typically this option is enabled
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or disabled with 'reflected_output'.
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reflected_output:
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Some CRC standards require that all the output bits be reflected around the center point.
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This operation occurs before the final optional xor output step. This option is enabled
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with '1' and disabled with '0'. Typically this option is enabled or disabled with
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'reflected_input' (to undo the input reversal typically).
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xor_output:
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This is the value used to bitwise xor the CRC result. Most standards use either all zeros
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or all ones for this value. When zeros are used the CRC result is passed directly and when
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ones are used the CRC result is inverted. Since it's no mandatory that this value be all
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ones or zeros, this operation occurs before the output reflection when applicable.
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*/
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parameter crc_width = 32;
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parameter polynomial_inital = 32'hFFFFFFFF;
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parameter polynomial = 32'h04C11DB7;
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parameter reflected_input = 1;
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parameter reflected_output = 1;
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parameter xor_output = 32'hFFFFFFFF;
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input clk;
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input reset;
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input [2:0] address;
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input [31:0] writedata;
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input [3:0] byteenable;
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input write;
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input read;
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input chipselect;
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output [31:0] readdata;
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reg [crc_width-1:0] crc_value;
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wire [crc_width-1:0] poly = polynomial;
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wire [crc_width-1:0] cascade [3:0];
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wire [7:0] block0_data, block1_data, block2_data, block3_data;
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wire [crc_width-1:0] result, result_xored;
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wire [31:0] mux_result;
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reg [31:0] readdata;
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/*
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Some standards like CRC16 and CRC32 require this bitreversal for serial
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devices like ethernet, uarts, usb, etc...
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*/
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genvar index;
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generate if (reflected_input == 1)
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begin
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for(index = 0; index < 8; index = index + 1)
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begin: input_reflection
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assign block0_data[index] = writedata[7-index];
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assign block1_data[index] = writedata[15-index];
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assign block2_data[index] = writedata[23-index];
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assign block3_data[index] = writedata[31-index];
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end
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end
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else
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begin
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assign block0_data = writedata[7:0];
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assign block1_data = writedata[15:8];
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assign block2_data = writedata[23:16];
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assign block3_data = writedata[31:24];
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end
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endgenerate
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/*
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Control for the registered events. It assumes that either 8, 16, 24, or 32
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bit data is being written using byte enables. It is important that the data
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be in little endian format and no gaps of byte enables be present (like
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1011 or 1101 for example)
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*/
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always @ (posedge clk or posedge reset)
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begin
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if(reset == 1)
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begin
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crc_value <= 0;
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end
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else
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begin
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if(write && chipselect && (address == 3'b000))
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begin
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crc_value <= polynomial_inital; // reset the crc to the initial value
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end
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else if(write && chipselect && (address == 3'b001))
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begin
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if(byteenable == 4'b0001) // 8 bit data input
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begin
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crc_value <= cascade[0];
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end
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else if(byteenable == 4'b0011) // 16 bit data input
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begin
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crc_value <= cascade[1];
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end
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else if(byteenable == 4'b0111) // 24 bit data input
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begin
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crc_value <= cascade[2];
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end
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else if(byteenable == 4'b1111) // 32 bit data input
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begin
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crc_value <= cascade[3];
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end
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end
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end
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end
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/* four stages of cascade blocks (each block is crc_width x 8 bits) */
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XOR_Shift_Block cascade_block0(.block_input(crc_value), .poly(poly), .data_input(block0_data), .block_output(cascade[0]));
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defparam cascade_block0.crc_width = crc_width;
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XOR_Shift_Block cascade_block1(.block_input(cascade[0]), .poly(poly), .data_input(block1_data), .block_output(cascade[1]));
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defparam cascade_block1.crc_width = crc_width;
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XOR_Shift_Block cascade_block2(.block_input(cascade[1]), .poly(poly), .data_input(block2_data), .block_output(cascade[2]));
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defparam cascade_block2.crc_width = crc_width;
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XOR_Shift_Block cascade_block3(.block_input(cascade[2]), .poly(poly), .data_input(block3_data), .block_output(cascade[3]));
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defparam cascade_block3.crc_width = crc_width;
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/*
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Some standards like CRC16 and CRC32 require this bitreversal.
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This is to better support serial devices like uarts, ethernet, usb, etc...)
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*/
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generate if (reflected_output == 1)
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begin
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for(index = 0; index < crc_width; index = index + 1)
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begin: output_reflection32
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assign result[index] = crc_value[(crc_width-1)-index];
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end
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end
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else
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begin
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assign result = crc_value;
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end
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endgenerate
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/* This final xor operation occurs after the bit swap */
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assign result_xored = result ^ xor_output;
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/* Generates the appropriate MUX logic depending on the CRC width */
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generate if((crc_width > 32) && (crc_width < 65))
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begin
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assign mux_result = (address == 3'b100)? result_xored[31:0] : result_xored[crc_width-1:32];
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end
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else if((crc_width > 64) && (crc_width < 97))
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begin
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assign mux_result = (address == 3'b100)? result_xored[31:0] :
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((address == 3'b101)? result_xored[63:32] : result_xored[crc_width-1:64]);
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end
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else if((crc_width > 96) && (crc_width < 129))
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begin
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assign mux_result = (address == 3'b100)? result_xored[31:0] :
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((address == 3'b101)? result_xored[63:32] :
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((address == 3'b110)? result_xored[95:64] : result_xored[crc_width-1:96]));
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end
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else
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begin
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assign mux_result = result_xored;
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end
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endgenerate
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/* Registering the return path of the CRC data (32 bits of it) */
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always @ (posedge clk or posedge reset)
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begin
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if(reset == 1)
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begin
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readdata <= 0;
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end
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else if((read == 1) && (chipselect == 1))
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begin
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readdata <= mux_result;
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end
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end
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endmodule
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/* a single cascade block of width: crc_width and a length of eight input bits */
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module XOR_Shift_Block(block_input,
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poly,
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data_input,
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block_output);
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parameter crc_width = 32;
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input [(crc_width-1):0] block_input;
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input [(crc_width-1):0] poly;
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input [7:0] data_input;
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output [(crc_width-1):0] block_output;
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wire [(crc_width-1):0] cascade [7:0];
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XOR_Shift bit_0(.stage_input(block_input), .poly(poly), .new_bit(data_input[7]), .stage_output(cascade[0]));
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defparam bit_0.crc_width = crc_width;
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XOR_Shift bit_1(.stage_input(cascade[0]), .poly(poly), .new_bit(data_input[6]), .stage_output(cascade[1]));
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defparam bit_1.crc_width = crc_width;
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XOR_Shift bit_2(.stage_input(cascade[1]), .poly(poly), .new_bit(data_input[5]), .stage_output(cascade[2]));
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defparam bit_2.crc_width = crc_width;
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XOR_Shift bit_3(.stage_input(cascade[2]), .poly(poly), .new_bit(data_input[4]), .stage_output(cascade[3]));
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defparam bit_3.crc_width = crc_width;
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XOR_Shift bit_4(.stage_input(cascade[3]), .poly(poly), .new_bit(data_input[3]), .stage_output(cascade[4]));
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defparam bit_4.crc_width = crc_width;
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XOR_Shift bit_5(.stage_input(cascade[4]), .poly(poly), .new_bit(data_input[2]), .stage_output(cascade[5]));
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defparam bit_5.crc_width = crc_width;
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XOR_Shift bit_6(.stage_input(cascade[5]), .poly(poly), .new_bit(data_input[1]), .stage_output(cascade[6]));
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defparam bit_6.crc_width = crc_width;
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XOR_Shift bit_7(.stage_input(cascade[6]), .poly(poly), .new_bit(data_input[0]), .stage_output(cascade[7]));
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defparam bit_7.crc_width = crc_width;
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assign block_output = cascade[7];
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endmodule
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/* performs the 'new_bit' stuffing, shifting, and XOR operations for a single input bit */
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module XOR_Shift (stage_input,
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poly,
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new_bit,
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stage_output);
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parameter crc_width = 32;
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input [crc_width-1:0] stage_input;
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input [crc_width-1:0] poly;
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input new_bit;
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output [crc_width-1:0] stage_output;
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assign stage_output[0] = new_bit ^ stage_input[crc_width-1];
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assign stage_output[crc_width-1:1] = stage_input[crc_width-2:0] ^ ({crc_width-1{stage_output[0]}} & poly[crc_width-1:1]);
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endmodule
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