mirror of
https://github.com/mnaberez/py65.git
synced 2024-07-06 10:28:58 +00:00
Remove redundant setting of program counter
This commit is contained in:
Mike Naberezny
parent
4b149cbded
commit
3d2490bcce
@ -43,7 +43,7 @@ class MPU:
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# init
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self.reset()
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def reprformat(self):
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def reprformat(self):
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return ("%s PC AC XR YR SP NV-BDIZC\n" + \
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"%s: %04x %02x %02x %02x %02x %s"
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)
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@ -52,18 +52,16 @@ class MPU:
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flags = itoa(self.p, 2).rjust(self.byteWidth, '0')
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indent = ' ' * (len(self.name) + 2)
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return self.reprformat() % (indent, self.name,
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return self.reprformat() % (indent, self.name,
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self.pc, self.a, self.x, self.y, self.sp, flags)
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def step(self):
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instructCode = self.ImmediateByte()
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self.pc +=1
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self.pc &=self.addrMask
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self.pc = (self.pc + 1) & self.addrMask
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self.excycles = 0
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self.addcycles = self.extracycles[instructCode]
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self.instruct[instructCode](self)
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self.processorCycles += self.cycletime[instructCode]+self.excycles
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self.pc &= self.addrMask
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return self
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def reset(self):
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@ -170,7 +168,7 @@ class MPU:
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def stPushWord(self, z):
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self.stPush((z>>self.byteWidth)&self.byteMask)
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self.stPush(z&self.byteMask)
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def stPopWord(self):
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z = self.stPop()
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z += self.stPop()<<self.byteWidth
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@ -206,7 +204,7 @@ class MPU:
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self.p |= tbyte & self.NEGATIVE
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else:
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self.p |= self.ZERO
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if x is None:
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self.a = tbyte
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else:
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@ -234,7 +232,7 @@ class MPU:
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self.memory[addr]=tbyte
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def opBCL(self, x):
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if self.p & x:
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if self.p & x:
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self.pc += 1
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else:
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self.BranchRelAddr()
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@ -278,7 +276,7 @@ class MPU:
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else:
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if tbyte & self.NEGATIVE:
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self.p |= self.CARRY
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tbyte = tbyte << 1
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tbyte = tbyte << 1
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tbyte &= self.byteMask
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self.FlagsNZ(tbyte)
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@ -293,7 +291,7 @@ class MPU:
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def opADC(self, x):
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data = self.ByteAt(x())
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if self.p & self.DECIMAL:
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halfcarry = 0
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decimalcarry = 0
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@ -389,7 +387,7 @@ class MPU:
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def opSBC(self, x):
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data = self.ByteAt(x())
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if self.p & self.DECIMAL:
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halfcarry = 1
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decimalcarry = 0
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@ -504,7 +502,7 @@ class MPU:
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extracycles = [0] * 256
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disassemble = [('???', 'imp')] * 256
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instruction = make_instruction_decorator(instruct, disassemble,
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instruction = make_instruction_decorator(instruct, disassemble,
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cycletime, extracycles)
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@instruction(name="BRK", mode="imp", cycles=7)
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@ -532,16 +530,16 @@ class MPU:
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def inst_0x06(self):
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self.opASL(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="PHP", mode="imp", cycles=3)
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def inst_0x08(self):
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self.stPush(self.p | self.BREAK | self.UNUSED)
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@instruction(name="ORA", mode="imm", cycles=2)
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def inst_0x09(self):
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self.opORA(self.ProgramCounter)
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self.pc += 1
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@instruction(name="ASL", mode="acc", cycles=2)
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def inst_0x0a(self):
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self.opASL(None)
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@ -550,40 +548,40 @@ class MPU:
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def inst_0x0d(self):
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self.opORA(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="ASL", mode="abs", cycles=6)
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def inst_0x0e(self):
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self.opASL(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="BPL", mode="rel", cycles=2, extracycles=2)
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def inst_0x10(self):
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self.opBCL(self.NEGATIVE)
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@instruction(name="ORA", mode="iny", cycles=5, extracycles=1)
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def inst_0x11(self):
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self.opORA(self.IndirectYAddr)
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self.pc += 1
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@instruction(name="ORA", mode="zpx", cycles=4)
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def inst_0x15(self):
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self.opORA(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="ASL", mode="zpx", cycles=6)
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def inst_0x16(self):
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self.opASL(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="CLC", mode="imp", cycles=2)
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def inst_0x18(self):
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self.opCLR(self.CARRY)
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@instruction(name="ORA", mode="aby", cycles=4, extracycles=1)
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def inst_0x19(self):
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self.opORA(self.AbsoluteYAddr)
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self.pc += 2
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self.pc += 2
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@instruction(name="ORA", mode="abx", cycles=4, extracycles=1)
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def inst_0x1d(self):
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self.opORA(self.AbsoluteXAddr)
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@ -595,25 +593,25 @@ class MPU:
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self.pc += 2
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@instruction(name="JSR", mode="abs", cycles=6)
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def inst_0x20(self):
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def inst_0x20(self):
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self.stPushWord((self.pc+1)&self.addrMask)
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self.pc=self.WordAt(self.pc)
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@instruction(name="AND", mode="inx", cycles=6)
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def inst_0x21(self):
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self.opAND(self.IndirectXAddr)
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self.pc += 1
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@instruction(name="BIT", mode="zpg", cycles=3)
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def inst_0x24(self):
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self.opBIT(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="AND", mode="zpg", cycles=3)
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def inst_0x25(self):
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self.opAND(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="ROL", mode="zpg", cycles=5)
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def inst_0x26(self):
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self.opROL(self.ZeroPageAddr)
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@ -622,7 +620,7 @@ class MPU:
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@instruction(name="PLP", mode="imp", cycles=4)
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def inst_0x28(self):
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self.p = (self.stPop() | self.BREAK | self.UNUSED)
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@instruction(name="AND", mode="imm", cycles=2)
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def inst_0x29(self):
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self.opAND(self.ProgramCounter)
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@ -678,7 +676,7 @@ class MPU:
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@instruction(name="AND", mode="abx", cycles=4, extracycles=1)
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def inst_0x3d(self):
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self.opAND(self.AbsoluteXAddr)
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self.pc += 2
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self.pc += 2
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@instruction(name="ROL", mode="abx", cycles=7)
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def inst_0x3e(self):
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@ -726,7 +724,7 @@ class MPU:
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def inst_0x4d(self):
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self.opEOR(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="LSR", mode="abs", cycles=6)
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def inst_0x4e(self):
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self.opLSR(self.AbsoluteAddr)
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@ -812,13 +810,13 @@ class MPU:
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@instruction(name="ADC", mode="abs", cycles=4)
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def inst_0x6d(self):
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self.opADC(self.AbsoluteAddr)
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self.pc +=2
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self.pc +=2
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@instruction(name="ROR", mode="abs", cycles=6)
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def inst_0x6e(self):
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self.opROR(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="BVS", mode="rel", cycles=2, extracycles=2)
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def inst_0x70(self):
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self.opBST(self.OVERFLOW)
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@ -832,12 +830,12 @@ class MPU:
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def inst_0x75(self):
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self.opADC(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="ROR", mode="zpx", cycles=6)
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def inst_0x76(self):
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self.opROR(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="SEI", mode="imp", cycles=2)
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def inst_0x78(self):
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self.opSET(self.INTERRUPT)
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@ -851,7 +849,7 @@ class MPU:
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def inst_0x7d(self):
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self.opADC(self.AbsoluteXAddr)
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self.pc += 2
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@instruction(name="ROR", mode="abx", cycles=7)
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def inst_0x7e(self):
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self.opROR(self.AbsoluteXAddr)
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@ -882,17 +880,17 @@ class MPU:
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self.y -= 1
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self.y&=self.byteMask
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self.FlagsNZ(self.y)
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@instruction(name="TXA", mode="imp", cycles=2)
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def inst_0x8a(self):
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self.a=self.x
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self.FlagsNZ(self.a)
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@instruction(name="STY", mode="abs", cycles=4)
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def inst_0x8c(self):
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self.opSTY(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="STA", mode="abs", cycles=4)
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def inst_0x8d(self):
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self.opSTA(self.AbsoluteAddr)
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@ -902,36 +900,36 @@ class MPU:
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def inst_0x8e(self):
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self.opSTX(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="BCC", mode="rel", cycles=2, extracycles=2)
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def inst_0x90(self):
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self.opBCL(self.CARRY)
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@instruction(name="STA", mode="iny", cycles=6)
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def inst_0x91(self):
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self.opSTA(self.IndirectYAddr)
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self.pc += 1
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@instruction(name="STY", mode="zpx", cycles=4)
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def inst_0x94(self):
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self.opSTY(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="STA", mode="zpx", cycles=4)
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def inst_0x95(self):
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self.opSTA(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="STX", mode="zpy", cycles=4)
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def inst_0x96(self):
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self.opSTX(self.ZeroPageYAddr)
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self.pc += 1
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@instruction(name="TYA", mode="imp", cycles=2)
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def inst_0x98(self):
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self.a = self.y
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self.FlagsNZ(self.a)
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@instruction(name="STA", mode="aby", cycles=5)
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def inst_0x99(self):
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self.opSTA(self.AbsoluteYAddr)
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@ -947,7 +945,7 @@ class MPU:
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self.pc += 2
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@instruction(name="LDY", mode="imm", cycles=2)
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def inst_0xa0(self):
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def inst_0xa0(self):
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self.opLDY(self.ProgramCounter)
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self.pc += 1
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@ -975,14 +973,14 @@ class MPU:
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def inst_0xa6(self):
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self.opLDX(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="TAY", mode="imp", cycles=2)
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def inst_0xa8(self):
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self.y = self.a
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self.FlagsNZ(self.y)
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@instruction(name="LDA", mode="imm", cycles=2)
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def inst_0xa9(self):
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def inst_0xa9(self):
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self.opLDA(self.ProgramCounter)
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self.pc += 1
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@ -1005,11 +1003,11 @@ class MPU:
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def inst_0xae(self):
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self.opLDX(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="BCS", mode="rel", cycles=2, extracycles=2)
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def inst_0xb0(self):
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self.opBST(self.CARRY)
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@instruction(name="LDA", mode="iny", cycles=5, extracycles=1)
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def inst_0xb1(self):
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self.opLDA(self.IndirectYAddr)
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@ -1043,7 +1041,7 @@ class MPU:
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def inst_0xba(self):
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self.x = self.sp
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self.FlagsNZ(self.x)
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@instruction(name="LDY", mode="abx", cycles=4, extracycles=1)
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def inst_0xbc(self):
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self.opLDY(self.AbsoluteXAddr)
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@ -1091,7 +1089,7 @@ class MPU:
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self.FlagsNZ(self.y)
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@instruction(name="CMP", mode="imm", cycles=2)
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def inst_0xc9(self):
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def inst_0xc9(self):
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self.opCMPR(self.ProgramCounter, self.a)
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self.pc +=1
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@ -1115,7 +1113,7 @@ class MPU:
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def inst_0xce(self):
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self.opDECR(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="BNE", mode="rel", cycles=2, extracycles=2)
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def inst_0xd0(self):
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self.opBCL(self.ZERO)
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@ -1124,7 +1122,7 @@ class MPU:
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def inst_0xd1(self):
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self.opCMPR(self.IndirectYAddr, self.a)
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self.pc += 1
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@instruction(name="CMP", mode="zpx", cycles=4)
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def inst_0xd5(self):
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self.opCMPR(self.ZeroPageXAddr, self.a)
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@ -1163,12 +1161,12 @@ class MPU:
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def inst_0xe1(self):
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self.opSBC(self.IndirectXAddr)
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self.pc += 1
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@instruction(name="CPX", mode="zpg", cycles=3)
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def inst_0xe4(self):
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self.opCMPR(self.ZeroPageAddr, self.x)
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self.pc += 1
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@instruction(name="SBC", mode="zpg", cycles=3)
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def inst_0xe5(self):
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self.opSBC(self.ZeroPageAddr)
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@ -1178,13 +1176,13 @@ class MPU:
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def inst_0xe6(self):
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self.opINCR(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="INX", mode="imp", cycles=2)
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def inst_0xe8(self):
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self.x+=1
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self.x&=self.byteMask
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self.x&=self.byteMask
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self.FlagsNZ(self.x)
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@instruction(name="SBC", mode="imm", cycles=2)
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def inst_0xe9(self):
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self.opSBC(self.ProgramCounter)
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@ -1198,7 +1196,7 @@ class MPU:
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def inst_0xec(self):
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self.opCMPR(self.AbsoluteAddr, self.x)
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self.pc += 2
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@instruction(name="SBC", mode="abs", cycles=4)
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def inst_0xed(self):
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self.opSBC(self.AbsoluteAddr)
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@ -1227,11 +1225,11 @@ class MPU:
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def inst_0xf6(self):
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self.opINCR(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="SED", mode="imp", cycles=2)
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def inst_0xf8(self):
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self.opSET(self.DECIMAL)
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@instruction(name="SBC", mode="aby", cycles=4, extracycles=1)
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def inst_0xf9(self):
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self.opSBC(self.AbsoluteYAddr)
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@ -1242,7 +1240,7 @@ class MPU:
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self.opSBC(self.AbsoluteXAddr)
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self.pc += 2
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@instruction(name="INC", mode="abx", cycles=7)
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@instruction(name="INC", mode="abx", cycles=7)
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def inst_0xfe(self):
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self.opINCR(self.AbsoluteXAddr)
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self.pc += 2
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