From 4b453e3b7a94a0150369190d74eba5e4e0b27c72 Mon Sep 17 00:00:00 2001 From: BigEd Date: Sun, 21 Aug 2011 09:48:13 +0100 Subject: [PATCH] note the definition of 65Org16 and point to github implementaion --- src/py65/devices/mpu65Org16.py | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/py65/devices/mpu65Org16.py b/src/py65/devices/mpu65Org16.py index 4bac475..a316ccf 100644 --- a/src/py65/devices/mpu65Org16.py +++ b/src/py65/devices/mpu65Org16.py @@ -1,6 +1,15 @@ from py65.devices import mpu6502 from py65.utils.devices import make_instruction_decorator +# The 65Org16 is a derivative of the 6502 architecture +# - with 32-bit address space (by using 16-bit bytes) +# - with no specific support for 8-bit bytes +# - with BCD mode not supported +# - and otherwise all opcodes and addressing modes are like the NMOS 6502 +# - sign bit is bit 15, overflow bit is bit 14 +# +# One implementation can be found here: https://github.com/BigEd/verilog-6502/wiki + class MPU(mpu6502.MPU): def __init__(self, byteWidth=16, addrWidth=32, addrFmt="%08x", byteFmt="%04x", *args, **kwargs):