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Fix tests that broke when register display logic changed
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1c6494f55f
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@ -786,7 +786,7 @@ class MonitorTests(unittest.TestCase):
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mon.onecmd('~ $10')
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out = stdout.getvalue()
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expected = "+16\n$10\n0020\n00010000\n"
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self.assertEqual(expected, out)
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self.assertTrue(out.startswith(expected))
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def test_tilde_shortcut_without_space_for_vice_compatibility(self):
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stdout = StringIO()
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@ -794,7 +794,7 @@ class MonitorTests(unittest.TestCase):
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mon.onecmd('~$10')
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out = stdout.getvalue()
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expected = "+16\n$10\n0020\n00010000\n"
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self.assertEqual(expected, out)
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self.assertTrue(out.startswith(expected))
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def test_do_tilde(self):
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stdout = StringIO()
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@ -802,14 +802,15 @@ class MonitorTests(unittest.TestCase):
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mon.do_tilde('$10')
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out = stdout.getvalue()
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expected = "+16\n$10\n0020\n00010000\n"
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self.assertEqual(expected, out)
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self.assertTrue(out.startswith(expected))
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def test_help_tilde(self):
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stdout = StringIO()
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mon = Monitor(stdout=stdout)
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mon.help_tilde()
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out = stdout.getvalue()
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self.assertTrue(out.startswith("~ <number>"))
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expected = "~ <number>"
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self.assertTrue(out.startswith(expected))
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# show_labels
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