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Reorder instructions numerically

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This commit is contained in:
Mike Naberezny 2014-01-26 13:22:54 -08:00
parent c69ebc34ca
commit d63ec16966
1 changed files with 59 additions and 59 deletions
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118
py65/devices/mpu65c02.py
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@ -83,21 +83,45 @@ class MPU(mpu6502.MPU):
# 65C02 clears decimal flag, NMOS 6502 does not
self.p &= ~self.DECIMAL
@instruction(name="TSB", mode="zpg", cycles=5)
def inst_0x04(self):
self.opTSB(self.ZeroPageAddr)
self.pc += 1
@instruction(name="RMB0", mode="zpg", cycles=5)
def inst_0x07(self):
self.opRMB(self.ZeroPageAddr, 0xFE)
self.pc += 1
@instruction(name="TSB", mode="abs", cycles=6)
def inst_0x0c(self):
self.opTSB(self.AbsoluteAddr)
self.pc += 2
@instruction(name="ORA", mode="zpi", cycles=5)
def inst_0x12(self):
self.opORA(self.ZeroPageIndirectAddr)
self.pc += 1
@instruction(name="TRB", mode="zpg", cycles=5)
def inst_0x14(self):
self.opTRB(self.ZeroPageAddr)
self.pc += 1
@instruction(name="RMB1", mode="zpg", cycles=5)
def inst_0x17(self):
self.opRMB(self.ZeroPageAddr, 0xFD)
self.pc += 1
@instruction(name="INC", mode="acc", cycles=2)
def inst_0x1a(self):
self.opINCR(None)
@instruction(name="TRB", mode="abs", cycles=6)
def inst_0x1c(self):
self.opTRB(self.AbsoluteAddr)
self.pc += 2
@instruction(name="RMB2", mode="zpg", cycles=5)
def inst_0x27(self):
self.opRMB(self.ZeroPageAddr, 0xFB)
@ -118,6 +142,10 @@ class MPU(mpu6502.MPU):
self.opRMB(self.ZeroPageAddr, 0xF7)
self.pc += 1
@instruction(name="DEC", mode="acc", cycles=2)
def inst_0x3a(self):
self.opDECR(None)
@instruction(name="BIT", mode="abx", cycles=4)
def inst_0x3c(self):
self.opBIT(self.AbsoluteXAddr)
@ -152,6 +180,11 @@ class MPU(mpu6502.MPU):
self.opRMB(self.ZeroPageAddr, 0xBF)
self.pc += 1
@instruction(name="JMP", mode="ind", cycles=6)
def inst_0x6c(self):
ta = self.WordAt(self.pc)
self.pc = self.WordAt(ta)
@instruction(name="ADC", mode="zpi", cycles=5)
def inst_0x72(self):
self.opADC(self.ZeroPageIndirectAddr)
@ -162,15 +195,23 @@ class MPU(mpu6502.MPU):
self.opSTZ(self.ZeroPageXAddr)
self.pc += 1
@instruction(name="RMB7", mode="zpg", cycles=5)
def inst_0x77(self):
self.opRMB(self.ZeroPageAddr, 0x7F)
self.pc += 1
@instruction(name="PLY", mode="imp", cycles=4)
def inst_0x7a(self):
self.y = self.stPop()
self.FlagsNZ(self.y)
@instruction(name="RMB7", mode="zpg", cycles=5)
def inst_0x77(self):
self.opRMB(self.ZeroPageAddr, 0x7F)
self.pc += 1
@instruction(name="JMP", mode="iax", cycles=6)
def inst_0x7c(self):
self.pc = self.WordAt(self.IndirectAbsXAddr())
@instruction(name="BRA", mode="rel", cycles=1, extracycles=1)
def inst_0x80(self):
self.BranchRelAddr()
@instruction(name="SMB0", mode="zpg", cycles=5)
def inst_0x87(self):
@ -227,6 +268,15 @@ class MPU(mpu6502.MPU):
self.opSMB(self.ZeroPageAddr, 0x10)
self.pc += 1
@instruction(name="WAI", mode='imp', cycles=3)
def inst_0xcb(self):
self.waiting = True
@instruction(name="CMP", mode='zpi', cycles=5)
def inst_0xd2(self):
self.opCPY(self.ZeroPageIndirectAddr)
self.pc += 1
@instruction(name="SMB5", mode="zpg", cycles=5)
def inst_0xd7(self):
self.opSMB(self.ZeroPageAddr, 0x20)
@ -241,6 +291,11 @@ class MPU(mpu6502.MPU):
self.opSMB(self.ZeroPageAddr, 0x40)
self.pc += 1
@instruction(name="SBC", mode="zpi", cycles=5)
def inst_0xf2(self):
self.opSBC(self.ZeroPageIndirectAddr)
self.pc += 1
@instruction(name="SMB7", mode="zpg", cycles=5)
def inst_0xf7(self):
self.opSMB(self.ZeroPageAddr, 0x80)
@ -250,58 +305,3 @@ class MPU(mpu6502.MPU):
def inst_0xfa(self):
self.x = self.stPop()
self.FlagsNZ(self.x)
@instruction(name="TSB", mode="zpg", cycles=5)
def inst_0x04(self):
self.opTSB(self.ZeroPageAddr)
self.pc += 1
@instruction(name="TSB", mode="abs", cycles=6)
def inst_0x0c(self):
self.opTSB(self.AbsoluteAddr)
self.pc += 2
@instruction(name="TRB", mode="zpg", cycles=5)
def inst_0x14(self):
self.opTRB(self.ZeroPageAddr)
self.pc += 1
@instruction(name="INC", mode="acc", cycles=2)
def inst_0x1a(self):
self.opINCR(None)
@instruction(name="TRB", mode="abs", cycles=6)
def inst_0x1c(self):
self.opTRB(self.AbsoluteAddr)
self.pc += 2
@instruction(name="DEC", mode="acc", cycles=2)
def inst_0x3a(self):
self.opDECR(None)
@instruction(name="JMP", mode="ind", cycles=6)
def inst_0x6c(self):
ta = self.WordAt(self.pc)
self.pc = self.WordAt(ta)
@instruction(name="JMP", mode="iax", cycles=6)
def inst_0x7c(self):
self.pc = self.WordAt(self.IndirectAbsXAddr())
@instruction(name="BRA", mode="rel", cycles=1, extracycles=1)
def inst_0x80(self):
self.BranchRelAddr()
@instruction(name="WAI", mode='imp', cycles=3)
def inst_0xCB(self):
self.waiting = True
@instruction(name="CMP", mode='zpi', cycles=5)
def inst_0xD2(self):
self.opCPY(self.ZeroPageIndirectAddr)
self.pc += 1
@instruction(name="SBC", mode="zpi", cycles=5)
def inst_0xf2(self):
self.opSBC(self.ZeroPageIndirectAddr)
self.pc += 1