mirror of
https://github.com/mnaberez/py65.git
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305 lines
8.3 KiB
Python
305 lines
8.3 KiB
Python
from py65.devices import mpu6502
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from py65.utils.devices import make_instruction_decorator
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class MPU(mpu6502.MPU):
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def __init__(self, *args, **kwargs):
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mpu6502.MPU.__init__(self, *args, **kwargs)
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self.name = '65C02'
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self.waiting = False
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def step(self):
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if self.waiting:
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self.processorCycles += 1
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else:
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mpu6502.MPU.step(self)
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return self
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# Make copies of the lists
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instruct = mpu6502.MPU.instruct[:]
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cycletime = mpu6502.MPU.cycletime[:]
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extracycles = mpu6502.MPU.extracycles[:]
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disassemble = mpu6502.MPU.disassemble[:]
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instruction = make_instruction_decorator(instruct, disassemble,
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cycletime, extracycles)
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# addressing modes
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def ZeroPageIndirectAddr(self):
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return self.WordAt(255 & (self.ByteAt(self.pc)))
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def IndirectAbsXAddr(self):
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return (self.WordAt(self.pc) + self.x) & self.addrMask
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# operations
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def opRMB(self, x, mask):
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address = x()
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self.memory[address] &= mask
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def opSMB(self, x, mask):
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address = x()
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self.memory[address] |= mask
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def opSTZ(self, x):
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self.memory[x()] = 0x00
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def opTSB(self, x):
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address = x()
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m = self.memory[address]
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self.p &= ~self.ZERO
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z = m & self.a
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if z == 0:
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self.p |= self.ZERO
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self.memory[address] = m | self.a
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def opTRB(self, x):
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address = x()
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m = self.memory[address]
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self.p &= ~self.ZERO
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z = m & self.a
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if z == 0:
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self.p |= self.ZERO
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self.memory[address] = m & ~self.a
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# instructions
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@instruction(name="BRK", mode="imp", cycles=7)
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def inst_0x00(self):
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# pc has already been increased one
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pc = (self.pc + 1) & self.addrMask
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self.stPushWord(pc)
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self.p |= self.BREAK
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self.stPush(self.p | self.BREAK | self.UNUSED)
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self.p |= self.INTERRUPT
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self.pc = self.WordAt(self.IRQ)
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# 65C02 clears decimal flag, NMOS 6502 does not
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self.p &= ~self.DECIMAL
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@instruction(name="TSB", mode="zpg", cycles=5)
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def inst_0x04(self):
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self.opTSB(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="RMB0", mode="zpg", cycles=5)
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def inst_0x07(self):
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self.opRMB(self.ZeroPageAddr, 0xFE)
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self.pc += 1
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@instruction(name="TSB", mode="abs", cycles=6)
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def inst_0x0c(self):
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self.opTSB(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="ORA", mode="zpi", cycles=5)
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def inst_0x12(self):
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self.opORA(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="TRB", mode="zpg", cycles=5)
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def inst_0x14(self):
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self.opTRB(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="RMB1", mode="zpg", cycles=5)
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def inst_0x17(self):
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self.opRMB(self.ZeroPageAddr, 0xFD)
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self.pc += 1
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@instruction(name="INC", mode="acc", cycles=2)
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def inst_0x1a(self):
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self.opINCR(None)
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@instruction(name="TRB", mode="abs", cycles=6)
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def inst_0x1c(self):
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self.opTRB(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="RMB2", mode="zpg", cycles=5)
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def inst_0x27(self):
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self.opRMB(self.ZeroPageAddr, 0xFB)
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self.pc += 1
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@instruction(name="AND", mode="zpi", cycles=5)
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def inst_0x32(self):
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self.opAND(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="BIT", mode="zpx", cycles=4)
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def inst_0x34(self):
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self.opBIT(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="RMB3", mode="zpg", cycles=5)
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def inst_0x37(self):
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self.opRMB(self.ZeroPageAddr, 0xF7)
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self.pc += 1
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@instruction(name="DEC", mode="acc", cycles=2)
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def inst_0x3a(self):
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self.opDECR(None)
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@instruction(name="BIT", mode="abx", cycles=4)
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def inst_0x3c(self):
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self.opBIT(self.AbsoluteXAddr)
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self.pc += 2
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@instruction(name="RMB4", mode="zpg", cycles=5)
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def inst_0x47(self):
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self.opRMB(self.ZeroPageAddr, 0xEF)
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self.pc += 1
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@instruction(name="EOR", mode="zpi", cycles=5)
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def inst_0x52(self):
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self.opEOR(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="RMB5", mode="zpg", cycles=5)
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def inst_0x57(self):
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self.opRMB(self.ZeroPageAddr, 0xDF)
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self.pc += 1
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@instruction(name="PHY", mode="imp", cycles=3)
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def inst_0x5a(self):
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self.stPush(self.y)
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@instruction(name="STZ", mode="zpg", cycles=3)
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def inst_0x64(self):
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self.opSTZ(self.ZeroPageAddr)
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self.pc += 1
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@instruction(name="RMB6", mode="zpg", cycles=5)
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def inst_0x67(self):
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self.opRMB(self.ZeroPageAddr, 0xBF)
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self.pc += 1
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@instruction(name="JMP", mode="ind", cycles=6)
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def inst_0x6c(self):
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ta = self.WordAt(self.pc)
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self.pc = self.WordAt(ta)
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@instruction(name="ADC", mode="zpi", cycles=5)
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def inst_0x72(self):
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self.opADC(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="STZ", mode="zpx", cycles=4)
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def inst_0x74(self):
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self.opSTZ(self.ZeroPageXAddr)
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self.pc += 1
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@instruction(name="RMB7", mode="zpg", cycles=5)
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def inst_0x77(self):
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self.opRMB(self.ZeroPageAddr, 0x7F)
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self.pc += 1
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@instruction(name="PLY", mode="imp", cycles=4)
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def inst_0x7a(self):
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self.y = self.stPop()
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self.FlagsNZ(self.y)
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@instruction(name="JMP", mode="iax", cycles=6)
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def inst_0x7c(self):
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self.pc = self.WordAt(self.IndirectAbsXAddr())
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@instruction(name="BRA", mode="rel", cycles=1, extracycles=1)
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def inst_0x80(self):
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self.BranchRelAddr()
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@instruction(name="SMB0", mode="zpg", cycles=5)
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def inst_0x87(self):
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self.opSMB(self.ZeroPageAddr, 0x01)
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self.pc += 1
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@instruction(name="BIT", mode="imm", cycles=2)
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def inst_0x89(self):
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# This instruction (BIT #$12) does not use opBIT because in the
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# immediate mode, BIT only affects the Z flag.
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tbyte = self.ImmediateByte()
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self.p &= ~(self.ZERO)
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if (self.a & tbyte) == 0:
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self.p |= self.ZERO
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self.pc += 1
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@instruction(name="STA", mode="zpi", cycles=5)
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def inst_0x92(self):
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self.opSTA(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="SMB1", mode="zpg", cycles=5)
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def inst_0x97(self):
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self.opSMB(self.ZeroPageAddr, 0x02)
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self.pc += 1
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@instruction(name="STZ", mode="abs", cycles=4)
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def inst_0x9c(self):
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self.opSTZ(self.AbsoluteAddr)
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self.pc += 2
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@instruction(name="STZ", mode="abx", cycles=5)
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def inst_0x9e(self):
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self.opSTZ(self.AbsoluteXAddr)
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self.pc += 2
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@instruction(name="SMB2", mode="zpg", cycles=5)
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def inst_0xa7(self):
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self.opSMB(self.ZeroPageAddr, 0x04)
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self.pc += 1
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@instruction(name="LDA", mode="zpi", cycles=5)
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def inst_0xb2(self):
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self.opLDA(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="SMB3", mode="zpg", cycles=5)
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def inst_0xb7(self):
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self.opSMB(self.ZeroPageAddr, 0x08)
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self.pc += 1
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@instruction(name="SMB4", mode="zpg", cycles=5)
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def inst_0xc7(self):
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self.opSMB(self.ZeroPageAddr, 0x10)
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self.pc += 1
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@instruction(name="WAI", mode='imp', cycles=3)
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def inst_0xcb(self):
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self.waiting = True
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@instruction(name="CMP", mode='zpi', cycles=5)
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def inst_0xd2(self):
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self.opCMPR(self.ZeroPageIndirectAddr, self.a)
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self.pc += 1
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@instruction(name="SMB5", mode="zpg", cycles=5)
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def inst_0xd7(self):
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self.opSMB(self.ZeroPageAddr, 0x20)
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self.pc += 1
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@instruction(name="PHX", mode="imp", cycles=3)
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def inst_0xda(self):
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self.stPush(self.x)
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@instruction(name="SMB6", mode="zpg", cycles=5)
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def inst_0xe7(self):
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self.opSMB(self.ZeroPageAddr, 0x40)
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self.pc += 1
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@instruction(name="SBC", mode="zpi", cycles=5)
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def inst_0xf2(self):
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self.opSBC(self.ZeroPageIndirectAddr)
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self.pc += 1
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@instruction(name="SMB7", mode="zpg", cycles=5)
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def inst_0xf7(self):
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self.opSMB(self.ZeroPageAddr, 0x80)
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self.pc += 1
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@instruction(name="PLX", mode="imp", cycles=4)
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def inst_0xfa(self):
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self.x = self.stPop()
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self.FlagsNZ(self.x)
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