mirror of
https://github.com/mnaberez/py65.git
synced 2024-07-27 21:29:00 +00:00
1235 lines
27 KiB
Python
1235 lines
27 KiB
Python
class MPU:
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# vectors
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ResetTo = 0xfffc
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IrqTo = 0xfffe
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NMITo = 0xfffa
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# processor flags
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NEGATIVE = 128
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OVERFLOW = 64
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BREAK = 16
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DECIMAL = 8
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INTERRUPT = 4
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ZERO = 2
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CARRY = 1
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def __init__(self):
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# config
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self.debug = False
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self.externalLoop = True
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self.stopOnIterrupt = True
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# vm status
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self.breakFlag = False
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self.excycles = 0
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self.addcycles = False
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self.processorCycles = 0;
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self.internalCycleDelay=0;
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# init
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self.clearMemory()
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self.reset()
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def __repr__(self):
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out = '<6502: A=%02x, X=%02x, Y=%02x, Flags=%02x, SP=%02x, PC=%04x>'
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return out % (self.a, self.x, self.y,
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self.flags, self.sp, self.pc)
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def step(self):
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breakFlag = False
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instructCode = self.ImmediateByte()
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self.pc +=1
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self.pc &=0xffff
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self.excycles = 0
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self.addcycles = self.extracycles[instructCode]
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self.instruct[instructCode](self)
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self.processorCycles += self.cycletime[instructCode]+self.excycles
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self.pc &=0xffff
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return self
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def reset(self):
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self.pc=0
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self.sp=255
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self.a=self.x=self.y=0
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self.flags=32
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self.breakFlag=False
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self.processorCycles=0
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def clearMemory(self, start=0x0000, end=0xFFFF):
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self.memory = self.RAM = []
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for addr in range(start, end + 1):
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self.memory.insert(addr, 0x00)
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def ByteAt(self, addr):
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return self.memory[addr]
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def WordAt(self, addr):
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return self.ByteAt(addr) + self.ByteAt(0xffff&(addr+1))*256
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def ImmediateByte(self):
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return self.ByteAt(self.pc)
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def ZeroPageAddr(self):
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return self.ByteAt(self.pc)
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def ZeroPageXAddr(self):
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return 255 & (self.x + self.ByteAt(self.pc))
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def ZeroPageYAddr(self):
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return 255 & (self.y + self.ByteAt(self.pc))
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def IndirectXAddr(self):
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return self.WordAt( 255 & (self.ByteAt(self.pc) + self.x))
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def IndirectYAddr(self):
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if self.addcycles:
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a1 = self.WordAt(self.ByteAt(self.pc))
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a2 = (a1+self.y)&0xffff
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if ((a1&0xff00) != (a2&0xff00)):
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self.extracyles += 1
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return a2
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else:
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return (self.WordAt(self.ByteAt(self.pc))+self.y)&0xffff
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def AbsoluteAddr(self):
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return self.WordAt(self.pc)
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def AbsoluteXAddr(self):
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if self.addcycles:
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a1 = self.WordAt(self.pc)
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a2 = (a1+self.x)&0xffff
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if ((a1&0xff00)!=(a2&0xff00)):
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self.extracyles += 1;
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return a2
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else:
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return (self.WordAt(self.pc)+self.x)&0xffff
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def AbsoluteYAddr(self):
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if self.addcycles:
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a1 = self.WordAt(self.pc)
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a2=(a1+self.y)&0xffff
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if ((a1&0xff00)!=(a2&0xff00)):
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self.extracyles += 1;
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return a2
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else:
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return (self.WordAt(self.pc)+self.y)&0xffff
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def BranchRelAddr(self):
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self.excycles += 1
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addr = self.ImmediateByte()
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self.pc += 1
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if addr & 128:
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addr = self.pc - (addr ^ 0xFF) + 1
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else:
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addr = self.pc + addr
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if (self.pc & 0xff00) != (addr & 0xff00):
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self.excycles += 1
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self.pc = addr & 0xffff
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# stack
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def stPush(self,z):
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self.RAM[self.sp+256] = z&255;
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self.sp -= 1;
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self.sp &= 255
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def stPop(self):
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self.sp += 1
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self.sp &= 255
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return self.ByteAt(self.sp+256)
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def stPushWord(self, z):
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self.stPush((z>>8)&255)
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self.stPush(z&255)
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def stPopWord(self):
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z = self.stPop()
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z += 256*self.stPop()
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return z
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# operations
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def FlagsNZ(self, z):
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self.flags &= ~(self.ZERO + self.NEGATIVE)
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if z == 0:
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self.flags |= self.ZERO
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else:
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self.flags |= z & 128
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def opORA(self, x):
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self.a |= self.ByteAt(x())
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self.FlagsNZ(self.a)
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def opASL(self, x):
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addr = x()
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tbyte = self.ByteAt(addr);
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self.flags &= ~(self.CARRY + self.NEGATIVE + self.ZERO)
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if (tbyte&128):
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self.flags |= self.CARRY
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tbyte = (tbyte << 1) & 0xFF
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if (tbyte):
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self.flags |= tbyte & 128
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else:
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self.flags |= self.ZERO
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self.RAM[addr] = tbyte
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def opLSR(self, x):
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addr = x()
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tbyte = self.ByteAt(addr)
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self.flags &=~(self.CARRY+self.NEGATIVE+self.ZERO)
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self.flags |=tbyte&1
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tbyte=tbyte>>1
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if (tbyte):
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pass # {}
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else:
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self.flags |= self.ZERO
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self.RAM[addr]=tbyte
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def opBCL(self, x):
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if self.flags & x:
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self.pc += 1
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else:
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self.BranchRelAddr()
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def opBST(self, x):
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if (self.flags&x):
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self.BranchRelAddr()
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else:
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self.pc+=1
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def opCLR(self, x):
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self.flags &=~x
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def opSET(self, x):
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self.flags |= x
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def opAND(self, x):
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self.a &= self.ByteAt(x())
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self.FlagsNZ(self.a)
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def opBIT(self, x):
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tbyte = self.ByteAt(x())
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self.flags &=~(self.ZERO+self.NEGATIVE+self.OVERFLOW)
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if ((self.a&tbyte)==0):
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self.flags |=self.ZERO;
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self.flags |=tbyte&(128+64)
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def opROL(self, x):
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addr = x();
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tbyte = self.ByteAt(addr)
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if self.flags & self.CARRY:
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if tbyte & 128:
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pass
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else:
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self.flags &= ~self.CARRY
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tbyte = (tbyte << 1) | 1
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else:
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if tbyte & 128:
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self.flags |= self.CARRY
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tbyte = tbyte << 1
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self.FlagsNZ(tbyte)
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self.RAM[addr] = tbyte & 0xFF
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def opEOR(self, x):
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self.a^=self.ByteAt(x())
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self.FlagsNZ(a)
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def opADC(self, x):
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data=self.ByteAt(x())
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if (self.flags&self.DECIMAL):
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if (self.flags&self.CARRY):
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tmp = 1
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else:
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tmp = 0
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data = self.bcd2dec[data]+self.bcd2dec[self.a]+tmp
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self.flags &= ~(self.CARRY+self.OVERFLOW+self.NEGATIVE+self.ZERO)
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if (data>99):
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self.flags|=self.CARRY+self.OVERFLOW;
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data -=100
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if (data==0):
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self.flags|=self.ZERO
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else:
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self.flags |=data&128
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self.a=self.dec2bcd[data]
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else:
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if self.flags & self.CARRY:
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tmp = 1
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else:
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tmp = 0
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data += self.a + tmp;
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self.flags &= ~(self.CARRY+self.OVERFLOW+self.NEGATIVE+self.ZERO)
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if data > 255:
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self.flags|=self.OVERFLOW+self.CARRY
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data &=255
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if data == 0:
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self.flags |= self.ZERO
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else:
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self.flags |= data&128;
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self.a = data
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def opROR(self, x):
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addr=x()
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tbyte=self.ByteAt(addr)
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if (self.flags&self.CARRY):
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if (tbyte&1):
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pass # {}
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else:
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self.flags &=~ self.CARRY
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tbyte=(tbyte>>1)|128
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else:
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if (tbyte&1):
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self.flags |= self.CARRY
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tbyte=tbyte>>1
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self.FlagsNZ(tbyte)
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self.RAM[addr]=tbyte
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def opSTA(self, x):
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self.RAM[x()] = self.a
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def opSTY(self, x):
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self.RAM[x()] = self.y
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def opSTX(self, y):
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self.RAM[y()] = self.x
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def opCPY(self, x):
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tbyte=self.ByteAt(x());
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self.flags &=~(self.CARRY+self.ZERO+self.NEGATIVE)
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if (self.y==tbyte):
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self.flags |= self.CARRY + self.ZERO
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elif (self.y>tbyte):
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self.flags |= self.CARRY
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else:
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self.flags |= self.NEGATIVE;
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def opCPX(self, y):
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tbyte=self.ByteAt(y())
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self.flags &=~(self.CARRY+self.ZERO+self.NEGATIVE)
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if (self.x==tbyte):
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self.flags |= self.CARRY + self.ZERO
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elif (self.x>tbyte):
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self.flags |= self.CARRY
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else:
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self.flags |= self.NEGATIVE
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def opCMP(self, x):
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tbyte = self.ByteAt(x())
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self.flags &=~(self.CARRY+self.ZERO+self.NEGATIVE)
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if (self.a==tbyte):
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self.flags |= self.CARRY + self.ZERO
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elif (self.a>tbyte):
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self.flags |= self.CARRY
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else:
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self.flags |= self.NEGATIVE
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def opSBC(self, x):
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data = self.ByteAt(x())
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if (self.flags & self.DECIMAL):
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if (self.flags & self.CARRY):
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tmp = 0
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else:
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tmp = 1
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data = self.bcd2dec[a] - self.bcd2dec[data] - tmp
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self.flags &= ~(self.CARRY + self.ZERO + self.NEGATIVE + self.OVERFLOW)
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if (data==0):
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self.flags |= self.ZERO + self.CARRY
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elif (data>0):
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self.flags |= self.CARRY
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else:
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self.flags |= self.NEGATIVE
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data +=100
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self.a = self.dec2bcd[data]
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else:
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if (self.flags & self.CARRY):
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tmp = 0
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else:
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tmp = 1
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data = self.a - data - tmp
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self.flags &=~(self.CARRY + self.ZERO + self.OVERFLOW + self.NEGATIVE)
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if (data==0):
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self.flags |= self.ZERO + self.CARRY
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elif (data>0):
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self.flags |= self.CARRY
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else:
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self.flags |= self.OVERFLOW
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self.flags |= data&128
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self.a = data&255
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def opDECR(self, x):
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addr=x();
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tbyte = self.ByteAt(addr)
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self.flags &=~(self.ZERO+self.NEGATIVE)
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tbyte -= 1
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if tbyte:
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self.flags |= self.tbyte&128
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else:
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self.flags |= self.ZERO;
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self.RAM[addr] = tbyte
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def opINCR(self, x):
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addr=x();
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tbyte = self.ByteAt(addr)
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self.flags &=~(self.ZERO + self.NEGATIVE)
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tbyte += 1
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if (tbyte):
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self.flags |= tbyte&128
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else:
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self.flags |= fZER;
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self.RAM[addr]=tbyte
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def opLDA(self, x):
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self.a = self.ByteAt(x())
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self.FlagsNZ(self.a)
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def opLDY(self, x):
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self.y = self.ByteAt(x())
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self.FlagsNZ(self.y)
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def opLDX(self, y):
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self.x = self.ByteAt(y())
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self.FlagsNZ(self.x)
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# instructions
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def i00(self):
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pc = (self.pc + 2) & 0xFFFF
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self.stPushWord(pc)
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self.flags |= self.BREAK
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self.stPush(self.flags)
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self.flags |= self.INTERRUPT
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self.pc = self.WordAt(self.IrqTo)
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self.breakFlag = True
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def i01(self):
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self.opORA(self.IndirectXAddr)
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self.pc += 1
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def i05(self):
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self.opORA(self.ZeroPageAddr)
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self.pc += 1
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def i06(self):
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self.opASL(self.ZeroPageAddr)
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self.pc += 1
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def i08(self):
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self.stPush(self.flags)
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def i09(self):
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self.a |= self.ImmediateByte()
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self.FlagsNZ(self.a)
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self.pc += 1
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def i0a(self):
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if (self.a&128):
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self.flags |= self.CARRY
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else:
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self.flags &= ~self.CARRY;
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self.a = self.a << 1;
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self.FlagsNZ(self.a);
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self.a &= 255
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def i0d(self):
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self.opORA(self.AbsoluteAddr)
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self.pc += 2
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def i0e(self):
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self.opASL(self.AbsoluteAddr)
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self.pc += 2
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def i10(self):
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self.opBCL(self.NEGATIVE)
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def i11(self):
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self.opORA(self.IndirectYAddr)
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self.pc += 1
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def i15(self):
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self.opORA(self.ZeroPageXAddr)
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self.pc += 1
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def i16(self):
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self.opASL(self.ZeroPageXAddr)
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self.pc += 1
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def i18(self):
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self.opCLR(self.CARRY)
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def i19(self):
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self.opORA(self.AbsoluteYAddr)
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self.pc += 2
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def i1d(self):
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self.opORA(self.AbsoluteXAddr)
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self.pc += 2
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def i1e(self):
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self.opASL(self.AbsoluteXAddr)
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self.pc += 2
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def i20(self):
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self.stPushWord((self.pc+1)&0xffff)
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self.pc=self.WordAt(self.pc)
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def i21(self):
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self.opAND(self.IndirectXAddr)
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self.pc += 1
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def i24(self):
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self.opBIT(self.ZeroPageAddr)
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self.pc += 1
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def i25(self):
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self.opAND(self.ZeroPageAddr)
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self.pc += 1
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def i26(self):
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self.opROL(self.ZeroPageAddr)
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self.pc += 1
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def i28(self):
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self.flags = self.stPop()
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def i29(self):
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self.a &= self.ImmediateByte()
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self.FlagsNZ(self.a)
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self.pc += 1
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def i2a(self):
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if (self.flags & self.CARRY):
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if ((self.a & 128)==0):
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self.flags &=~self.CARRY;
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self.a=(self.a<<1)|1
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else:
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if (self.a&128):
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self.flags|=self.CARRY;
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self.a=self.a<<1
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self.FlagsNZ(self.a);
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self.a&=255
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def i2c(self):
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self.opBIT(self.AbsoluteAddr)
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self.pc+=2
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def i2d(self):
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self.opAND(self.AbsoluteAddr)
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self.pc+=2
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def i2e(self):
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self.opROL(self.AbsoluteAddr)
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self.pc += 2
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def i30(self):
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self.opBST(self.NEGATIVE)
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def i31(self):
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self.opAND(self.IndirectYAddr)
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self.pc += 1
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def i35(self):
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self.opAND(self.ZeroPageXAddr)
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self.pc += 1
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def i36(self):
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self.opROL(self.ZeroPageXAddr)
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self.pc += 1
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def i38(self):
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self.opSET(self.CARRY)
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def i39(self):
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self.opAND(self.AbsoluteYAddr)
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self.pc+=2
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def i3d(self):
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self.opAND(self.AbsoluteXAddr)
|
|
self.pc += 2
|
|
|
|
def i3e(self):
|
|
self.opROL(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def i40(self):
|
|
self.flags = self.stPop()
|
|
self.pc = self.stPopWord()
|
|
|
|
def i41(self):
|
|
self.opEOR(self.IndirectXAddr)
|
|
self.pc+=1
|
|
|
|
def i45(self):
|
|
self.opEOR(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def i46(self):
|
|
self.opLSR(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def i48(self):
|
|
self.stPush(self.a)
|
|
|
|
def i49(self):
|
|
self.a ^= self.ImmediateByte()
|
|
self.FlagsNZ(self.a)
|
|
self.pc+=1
|
|
|
|
def i4a(self):
|
|
self.flags &=~(self.CARRY+self.NEGATIVE+self.ZERO);
|
|
if (self.a&1):
|
|
self.flags |= self.CARRY
|
|
|
|
self.a=self.a>>1
|
|
if (self.a):
|
|
pass # {}
|
|
else:
|
|
self.flags |= self.ZERO
|
|
self.a&=255
|
|
|
|
def i4c(self):
|
|
self.pc=self.WordAt(self.pc)
|
|
|
|
def i4d(self):
|
|
self.opEOR(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def i4e(self):
|
|
self.opLSR(self.AbsoluteAddr)
|
|
self.pc += 2
|
|
|
|
def i50(self):
|
|
self.opBCL(self.OVERFLOW)
|
|
|
|
def i51(self):
|
|
self.opEOR(self.IndirectYAddr)
|
|
self.pc+=1
|
|
|
|
def i55(self):
|
|
self.opEOR(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def i56(self):
|
|
self.opLSR(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def i58(self):
|
|
self.opCLR(self.INTERRUPT)
|
|
|
|
def i59(self):
|
|
self.opEOR(self.AbsoluteYAddr)
|
|
self.pc +=2
|
|
|
|
def i5d(self):
|
|
self.opEOR(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def i5e(self):
|
|
self.opLSR(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def i60(self):
|
|
self.pc=self.stPopWord()
|
|
self.pc+=1
|
|
|
|
def i61(self):
|
|
self.opADC(self.IndirectXAddr)
|
|
self.pc+=1
|
|
|
|
def i65(self):
|
|
self.opADC(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def i66(self):
|
|
self.opROR(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def i68(self):
|
|
self.a = self.stPop()
|
|
self.FlagsNZ(self.a)
|
|
|
|
def i69(self):
|
|
data = self.ImmediateByte()
|
|
|
|
if (self.flags & self.CARRY):
|
|
tmp = 1
|
|
else:
|
|
tmp = 0
|
|
|
|
if (self.flags & self.DECIMAL):
|
|
data = self.bcd2dec[data] + self.bcd2dec[a] + tmp
|
|
self.flags &= ~(self.CARRY+self.OVERFLOW+self.NEGATIVE+self.ZERO)
|
|
if (data>99):
|
|
self.flags|=self.CARRY+self.OVERFLOW
|
|
data -=100
|
|
if (data==0):
|
|
self.flags |= self.ZERO
|
|
else:
|
|
self.flags |= self.data&128
|
|
self.a = self.dec2bcd[data]
|
|
else:
|
|
if (self.flags & self.CARRY):
|
|
tmp = 1
|
|
else:
|
|
tmp = 0
|
|
data += self.a + tmp
|
|
self.flags &= ~(self.CARRY+self.OVERFLOW+self.NEGATIVE+self.ZERO)
|
|
if (data>255):
|
|
self.flags |= self.OVERFLOW + self.CARRY
|
|
data &=255
|
|
if (data==0):
|
|
self.flags |= self.ZERO
|
|
else:
|
|
self.flags |= data&128
|
|
self.a=data
|
|
self.pc += 1
|
|
|
|
def i6a(self):
|
|
if self.flags & self.CARRY:
|
|
if (self.a & 1) == 0:
|
|
self.flags &= ~self.CARRY
|
|
self.a = (self.a >> 1) | 128
|
|
else:
|
|
if self.a & 1:
|
|
self.flags |= self.CARRY
|
|
self.a = self.a >> 1
|
|
self.FlagsNZ(self.a)
|
|
self.a &= 255
|
|
|
|
def i6c(self):
|
|
ta = self.WordAt(self.pc)
|
|
self.pc = self.WordAt(ta)
|
|
|
|
def i6d(self):
|
|
self.opADC(self.AbsoluteAddr)
|
|
self.pc +=2
|
|
|
|
def i6e(self):
|
|
self.opROR(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def i70(self):
|
|
self.opBST(self.OVERFLOW)
|
|
|
|
def i71(self):
|
|
self.opADC(self.IndirectYAddr)
|
|
self.pc+=1
|
|
|
|
def i75(self):
|
|
self.opADC(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def i76(self):
|
|
self.opROR(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def i78(self):
|
|
self.opSET(self.INTERRUPT)
|
|
|
|
def i79(self):
|
|
self.opADC(self.AbsoluteYAddr)
|
|
self.pc+=2
|
|
|
|
def i7d(self):
|
|
self.opADC(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def i7e(self):
|
|
self.opROR(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def i81(self):
|
|
self.opSTA(self.IndirectXAddr)
|
|
self.pc+=1
|
|
|
|
def i84(self):
|
|
self.opSTY(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def i85(self):
|
|
self.opSTA(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def i86(self):
|
|
self.opSTX(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def i88(self):
|
|
self.y -= 1
|
|
self.y&=255
|
|
self.FlagsNZ(self.y)
|
|
|
|
def i8a(self):
|
|
self.a=self.x
|
|
self.FlagsNZ(self.a)
|
|
|
|
def i8c(self):
|
|
self.opSTY(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def i8d(self):
|
|
self.opSTA(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def i8e(self):
|
|
self.opSTX(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def i90(self):
|
|
self.opBCL(self.CARRY)
|
|
|
|
def i91(self):
|
|
self.opSTA(self.IndirectYAddr)
|
|
self.pc+=1
|
|
|
|
def i94(self):
|
|
self.opSTY(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def i95(self):
|
|
self.opSTA(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def i96(self):
|
|
self.opSTX(self.ZeroPageYAddr)
|
|
self.pc+=1
|
|
|
|
def i98(self):
|
|
self.a = self.y
|
|
self.FlagsNZ(self.a)
|
|
|
|
def i99(self):
|
|
self.opSTA(self.AbsoluteYAddr)
|
|
self.pc+=2
|
|
|
|
def i9a(self):
|
|
self.sp=self.x
|
|
|
|
def i9d(self):
|
|
self.opSTA(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def ia0(self):
|
|
self.y=self.ImmediateByte()
|
|
self.FlagsNZ(self.y)
|
|
self.pc+=1
|
|
|
|
def ia1(self):
|
|
self.opLDA(self.IndirectXAddr)
|
|
self.pc+=1
|
|
|
|
def ia2(self):
|
|
self.x=self.ImmediateByte()
|
|
self.FlagsNZ(self.x)
|
|
self.pc+=1
|
|
|
|
def ia4(self):
|
|
self.opLDY(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def ia5(self):
|
|
self.opLDA(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def ia6(self):
|
|
self.opLDX(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def ia8(self):
|
|
self.y = self.a
|
|
self.FlagsNZ(self.y)
|
|
|
|
def ia9(self):
|
|
self.a = self.ImmediateByte()
|
|
self.FlagsNZ(self.a)
|
|
self.pc += 1
|
|
|
|
def iaa(self):
|
|
self.x = self.a
|
|
self.FlagsNZ(self.x)
|
|
|
|
def iac(self):
|
|
self.opLDY(self.AbsoluteAddr)
|
|
self.pc += 2
|
|
|
|
def iad(self):
|
|
self.opLDA(self.AbsoluteAddr)
|
|
self.pc += 2
|
|
|
|
def iae(self):
|
|
self.opLDX(self.AbsoluteAddr)
|
|
self.pc += 2
|
|
|
|
def ib0(self):
|
|
self.opBST(self.CARRY)
|
|
|
|
def ib1(self):
|
|
self.opLDA(self.IndirectYAddr)
|
|
self.pc+=1
|
|
|
|
def ib4(self):
|
|
self.opLDY(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def ib5(self):
|
|
self.opLDA(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def ib6(self):
|
|
self.opLDX(self.ZeroPageYAddr)
|
|
self.pc+=1
|
|
|
|
def ib8(self):
|
|
self.opCLR(self.OVERFLOW)
|
|
|
|
def ib9(self):
|
|
self.opLDA(self.AbsoluteYAddr)
|
|
self.pc+=2
|
|
|
|
def iba(self):
|
|
self.x = self.sp
|
|
self.FlagsNZ(self.x)
|
|
|
|
def ibc(self):
|
|
self.opLDY(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def ibd(self):
|
|
self.opLDA(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def ibe(self):
|
|
self.opLDX(self.AbsoluteYAddr)
|
|
self.pc+=2
|
|
|
|
def ic0(self):
|
|
tbyte = self.ImmediateByte()
|
|
self.flags &=~(self.CARRY+self.ZERO+self.NEGATIVE);
|
|
if (y==tbyte):
|
|
self.flags |= self.CARRY+self.ZERO
|
|
elif (y>tbyte):
|
|
self.flags |= self.CARRY
|
|
else:
|
|
self.flags |= self.NEGATIVE;
|
|
self.pc += 1
|
|
|
|
def ic1(self):
|
|
self.opCMP(self.IndirectXAddr)
|
|
self.pc+=1
|
|
|
|
def ic4(self):
|
|
self.opCPY(self.ZeroPageAddr)
|
|
self.pc += 1
|
|
|
|
def ic5(self):
|
|
self.opCMP(self.ZeroPageAddr)
|
|
self.pc += 1
|
|
|
|
def ic6(self):
|
|
self.opDECR(self.ZeroPageAddr)
|
|
self.pc += 1
|
|
|
|
def ic8(self):
|
|
self.y += 1
|
|
self.y &= 255
|
|
self.FlagsNZ(self.y)
|
|
|
|
def ic9(self):
|
|
tbyte = self.ImmediateByte()
|
|
self.flags &=~(self.CARRY+self.ZERO+self.NEGATIVE)
|
|
if (self.a==tbyte):
|
|
self.flags |= self.CARRY + self.ZERO
|
|
elif (a>tbyte):
|
|
self.flags |= self.CARRY
|
|
else:
|
|
self.flags |= self.NEGATIVE
|
|
self.pc +=1
|
|
|
|
def ica(self):
|
|
self.x -= 1
|
|
self.x &= 255
|
|
self.FlagsNZ(self.x)
|
|
|
|
def icc(self):
|
|
self.opCPY(self.AbsoluteAddr)
|
|
self.pc += 2
|
|
|
|
def icd(self):
|
|
self.opCMP(self.AbsoluteAddr)
|
|
self.pc += 2
|
|
|
|
def ice(self):
|
|
self.opDECR(self.AbsoluteAddr)
|
|
self.pc += 2
|
|
|
|
def id0(self):
|
|
self.opBCL(self.ZERO)
|
|
|
|
def id1(self):
|
|
self.opCMP(self.IndirectYAddr)
|
|
self.pc+=1
|
|
|
|
def id5(self):
|
|
self.opCMP(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def id6(self):
|
|
self.opDECR(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def id8(self):
|
|
self.opCLR(self.DECIMAL)
|
|
|
|
def id9(self):
|
|
self.opCMP(self.AbsoluteYAddr)
|
|
self.pc+=2
|
|
|
|
def idd(self):
|
|
self.opCMP(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def ide(self):
|
|
self.opDECR(AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def ie0(self):
|
|
tbyte = self.ImmediateByte()
|
|
self.flags &=~(self.CARRY+self.ZERO+self.NEGATIVE)
|
|
if (self.x==tbyte):
|
|
self.flags |= self.CARRY + self.ZERO
|
|
elif (self.x>tbyte):
|
|
self.flags |= self.CARRY
|
|
else:
|
|
self.flags |= self.NEGATIVE;
|
|
self.pc += 1
|
|
|
|
def ie1(self):
|
|
self.opSBC(self.IndirectXAddr)
|
|
self.pc+=1
|
|
|
|
def ie4(self):
|
|
self.opCPX(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def ie5(self):
|
|
self.opSBC(self.ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def ie6(self):
|
|
self.opINCR(ZeroPageAddr)
|
|
self.pc+=1
|
|
|
|
def ie8(self):
|
|
self.x+=1
|
|
self.x&=255
|
|
self.FlagsNZ(self.x)
|
|
|
|
def ie9(self):
|
|
data=self.ImmediateByte()
|
|
|
|
if (self.flags & self.DECIMAL):
|
|
if (self.flags & self.CARRY):
|
|
tmp = 0
|
|
else:
|
|
tmp = 1
|
|
data = self.bcd2dec[a] - self.bcd2dec[data] - tmp
|
|
self.flags &= ~(self.CARRY+self.ZERO+self.NEGATIVE+self.OVERFLOW)
|
|
if (data==0):
|
|
self.flags |= self.ZERO + self.CARRY
|
|
elif (data>0):
|
|
self.flags |= self.CARRY
|
|
else:
|
|
self.flags |= self.NEGATIVE;
|
|
data +=100
|
|
self.a = self.dec2bcd[data]
|
|
else:
|
|
if (self.flags & self.CARRY):
|
|
tmp = 0
|
|
else:
|
|
tmp = 1
|
|
data = self.a - data - tmp
|
|
self.flags &=~(self.CARRY+self.ZERO+self.OVERFLOW+self.NEGATIVE)
|
|
if (data==0):
|
|
self.flags |= self.ZERO + self.CARRY
|
|
elif (data>0):
|
|
self.flags |= self.CARRY
|
|
else:
|
|
self.flags |= self.OVERFLOW
|
|
data &= 255;
|
|
self.flags |= data&128;
|
|
self.a=data
|
|
self.pc+=1
|
|
|
|
def iea(self):
|
|
pass
|
|
|
|
def iec(self):
|
|
self.opCPX(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def ied(self):
|
|
self.opSBC(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def iee(self):
|
|
self.opINCR(self.AbsoluteAddr)
|
|
self.pc+=2
|
|
|
|
def if0(self):
|
|
self.opBST(self.ZERO)
|
|
|
|
def if1(self):
|
|
self.opSBC(self.IndirectYAddr)
|
|
self.pc+=1
|
|
|
|
def if5(self):
|
|
self.opSBC(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def if6(self):
|
|
self.opINCR(self.ZeroPageXAddr)
|
|
self.pc+=1
|
|
|
|
def if8(self):
|
|
self.opSET(self.DECIMAL)
|
|
|
|
def if9(self):
|
|
self.opSBC(self.AbsoluteYAddr)
|
|
self.pc+=2
|
|
|
|
def ifd(self):
|
|
self.opSBC(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def ife(self):
|
|
self.opINCR(self.AbsoluteXAddr)
|
|
self.pc+=2
|
|
|
|
def ini(self):
|
|
if self.debug:
|
|
raise NotImplementedError
|
|
self.pc+=1
|
|
|
|
|
|
# code pages
|
|
|
|
instruct = [
|
|
i00, i01, ini, ini, ini, i05, i06, ini,
|
|
i08, i09, i0a, ini, ini, i0d, i0e, ini,
|
|
i10, i11, ini, ini, ini, i15, i16, ini,
|
|
i18, i19, ini, ini, ini, i1d, i1e, ini,
|
|
i20, i21, ini, ini, i24, i25, i26, ini,
|
|
i28, i29, i2a, ini, i2c, i2d, i2e, ini,
|
|
i30, i31, ini, ini, ini, i35, i36, ini,
|
|
i38, i39, ini, ini, ini, i3d, i3e, ini,
|
|
i40, i41, ini, ini, ini, i45, i46, ini,
|
|
i48, i49, i4a, ini, i4c, i4d, i4e, ini,
|
|
i50, i51, ini, ini, ini, i55, i56, ini,
|
|
i58, i59, ini, ini, ini, i5d, i5e, ini,
|
|
i60, i61, ini, ini, ini, i65, i66, ini,
|
|
i68, i69, i6a, ini, i6c, i6d, i6e, ini,
|
|
i70, i71, ini, ini, ini, i75, i76, ini,
|
|
i78, i79, ini, ini, ini, i7d, i7e, ini,
|
|
ini, i81, ini, ini, i84, i85, i86, ini,
|
|
i88, ini, i8a, ini, i8c, i8d, i8e, ini,
|
|
i90, i91, ini, ini, i94, i95, i96, ini,
|
|
i98, i99, i9a, ini, ini, i9d, ini, ini,
|
|
ia0, ia1, ia2, ini, ia4, ia5, ia6, ini,
|
|
ia8, ia9, iaa, ini, iac, iad, iae, ini,
|
|
ib0, ib1, ini, ini, ib4, ib5, ib6, ini,
|
|
ib8, ib9, iba, ini, ibc, ibd, ibe, ini,
|
|
ic0, ic1, ini, ini, ic4, ic5, ic6, ini,
|
|
ic8, ic9, ica, ini, icc, icd, ice, ini,
|
|
id0, id1, ini, ini, ini, id5, id6, ini,
|
|
id8, id9, ini, ini, ini, idd, ide, ini,
|
|
ie0, ie1, ini, ini, ie4, ie5, ie6, ini,
|
|
ie8, ie9, iea, ini, iec, ied, iee, ini,
|
|
if0, if1, ini, ini, ini, if5, if6, ini,
|
|
if8, if9, ini, ini, ini, ifd, ife, ini
|
|
]
|
|
|
|
cycletime = [
|
|
7, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 0, 4, 6, 0, # 00
|
|
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, # 10
|
|
6, 6, 0, 0, 3, 3, 5, 0, 4, 2, 2, 0, 4, 4, 6, 0, # 20
|
|
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, # 30
|
|
6, 6, 0, 0, 0, 3, 5, 0, 3, 2, 2, 0, 3, 4, 6, 0, # 40
|
|
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, # 50
|
|
6, 6, 0, 0, 0, 3, 5, 0, 4, 2, 2, 0, 5, 4, 6, 0, # 60
|
|
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, # 70
|
|
0, 6, 0, 0, 3, 3, 3, 0, 2, 0, 2, 0, 4, 4, 4, 0, # 80
|
|
2, 6, 0, 0, 4, 4, 4, 0, 2, 5, 2, 0, 0, 5, 0, 0, # 90
|
|
2, 6, 2, 0, 3, 3, 3, 0, 2, 2, 2, 0, 4, 4, 4, 0, # A0
|
|
2, 5, 0, 0, 4, 4, 4, 0, 2, 4, 2, 0, 4, 4, 4, 0, # B0
|
|
2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 3, 0, # C0
|
|
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0, # D0
|
|
2, 6, 0, 0, 3, 3, 5, 0, 2, 2, 2, 0, 4, 4, 6, 0, # E0
|
|
2, 5, 0, 0, 0, 4, 6, 0, 2, 4, 0, 0, 0, 4, 7, 0 # F0
|
|
]
|
|
|
|
extracycles= [
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # 00
|
|
2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, # 10
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # 20
|
|
2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, # 30
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # 40
|
|
2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, # 50
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # 60
|
|
2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, # 70
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # 80
|
|
2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # 90
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # A0
|
|
2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 1, 1, 1, 0, # B0
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # C0
|
|
2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0, # D0
|
|
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, # E0
|
|
2, 1, 0, 0, 0, 0, 0, 0, 0, 1, 0, 0, 0, 1, 0, 0 # F0
|
|
]
|
|
|
|
# lookup tables for opBCD math.
|
|
bcd2dec = [
|
|
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, # 0x00
|
|
10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, # 0x10
|
|
20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, # 0x20
|
|
30, 31, 32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, # 0x30
|
|
40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 51, 52, 53, 54, 55, # 0x40
|
|
50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 65, # 0x50
|
|
60, 61, 62, 63, 64, 65, 66, 67, 68, 69, 70, 71, 72, 73, 74, 75, # 0x60
|
|
70, 71, 72, 73, 74, 75, 76, 77, 78, 79, 80, 81, 82, 83, 84, 85, # 0x70
|
|
80, 81, 82, 83, 84, 85, 86, 87, 88, 89, 90, 91, 92, 93, 94, 95, # 0x80
|
|
90, 91, 92, 93, 94, 95, 96, 97, 98, 99,100,101,102,103,104,105, # 0x90
|
|
100,101,102,103,104,105,106,107,108,109,110,111,112,113,114,115, # 0xA0
|
|
110,111,112,113,114,115,116,117,118,119,120,121,122,123,124,125, # 0xB0
|
|
120,121,122,123,124,125,126,127,128,129,130,131,132,133,134,135, # 0xC0
|
|
130,131,132,133,134,135,136,137,138,139,140,141,142,143,144,145, # 0xD0
|
|
140,141,142,143,144,145,146,147,148,149,150,151,152,153,154,155, # 0xE0
|
|
150,151,152,153,154,155,156,157,158,159,160,161,162,163,164,165 # 0xF0
|
|
]
|
|
|
|
dec2bcd= [
|
|
0x00,0x01,0x02,0x03,0x04,0x05,0x06,0x07,0x08,0x09,
|
|
0x10,0x11,0x12,0x13,0x14,0x15,0x16,0x17,0x18,0x19,
|
|
0x20,0x21,0x22,0x23,0x24,0x25,0x26,0x27,0x28,0x29,
|
|
0x30,0x31,0x32,0x33,0x34,0x35,0x36,0x37,0x38,0x39,
|
|
0x40,0x41,0x42,0x43,0x44,0x45,0x46,0x47,0x48,0x49,
|
|
0x50,0x51,0x52,0x53,0x54,0x55,0x56,0x57,0x58,0x59,
|
|
0x60,0x61,0x62,0x63,0x64,0x65,0x66,0x67,0x68,0x69,
|
|
0x70,0x71,0x72,0x73,0x74,0x75,0x76,0x77,0x78,0x79,
|
|
0x80,0x81,0x82,0x83,0x84,0x85,0x86,0x87,0x88,0x89,
|
|
0x90,0x91,0x92,0x93,0x94,0x95,0x96,0x97,0x98,0x99
|
|
]
|
|
|