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Add ASL and LSR emulation.
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@ -5,15 +5,15 @@ OP_NOPI_3,"nop",IMMEDIATE,2,NULL
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OP_NOPI_4,"nop",IMPLIED,1,NULL
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OP_TSB_ZP,"tsb",ZP,2,NULL
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OP_ORA_ZP,"ora",ZP,2,emul_ora
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OP_ASL_ZP,"asl",ZP,2,NULL
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OP_ASL_ZP,"asl",ZP,2,emul_asl
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OP_RMB0_ZP,"rmb0",ZP,2,emul_rmb0
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OP_PHP,"php",IMPLIED,1,emul_php
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OP_ORA_IMM,"ora",IMMEDIATE,2,emul_ora
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OP_ASL,"asl",ACCUMULATOR,1,NULL
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OP_ASL,"asl",ACCUMULATOR,1,emul_asl
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OP_NOPI_C,"nop",IMPLIED,1,NULL
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OP_TSB_ABS,"tsb",ABSOLUTE,3,NULL
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OP_ORA_ABS,"ora",ABSOLUTE,3,emul_ora
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OP_ASL_ABS,"asl",ABSOLUTE,3,NULL
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OP_ASL_ABS,"asl",ABSOLUTE,3,emul_asl
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OP_BBR0_REL,"bbr0",ZPR,2,NULL
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OP_BPL_REL,"bpl",RELATIVE,2,NULL
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OP_ORA_IZPY,"ora",IZPY,2,emul_ora
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@ -21,7 +21,7 @@ OP_ORA_IZP,"ora",IZP,2,emul_ora
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OP_NOPI_14,"nop",IMPLIED,1,NULL
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OP_TRB_ZP,"trb",ZP,2,NULL
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OP_ORA_ZPX,"ora",ZPX,2,emul_ora
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OP_ASL_ZPX,"asl",ZPX,2,NULL
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OP_ASL_ZPX,"asl",ZPX,2,emul_asl
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OP_RMB1_ZP,"rmb1",ZP,1,emul_rmb1
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OP_CLC,"clc",IMPLIED,1,emul_clc
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OP_ORA_ABSY,"ora",ABSOLUTEY,3,emul_ora
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@ -29,7 +29,7 @@ OP_INC,"inc",ACCUMULATOR,1,emul_inc
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OP_NOPI_1C,"nop",IMPLIED,1,NULL
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OP_TRB_ABS,"trb",ABSOLUTE,3,NULL
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OP_ORA_ABSX,"ora",ABSOLUTEX,3,emul_ora
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OP_ASL_ABSX,"asl",ABSOLUTEX,3,NULL
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OP_ASL_ABSX,"asl",ABSOLUTEX,3,emul_asl
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OP_BBR1_REL,"bbr1",ZPR,2,NULL
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OP_JSR,"jsr",ABSOLUTE,3,NULL
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OP_AND_IZPX,"and",IZPX,2,emul_and
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@ -69,15 +69,15 @@ OP_NOPI_43,"nop",IMMEDIATE,2,NULL
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OP_NOPI_44,"nop",IMPLIED,1,NULL
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OP_NOPI_45,"nop",ZP,2,NULL
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OP_EOR_ZP,"eor",ZP,2,emul_eor
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OP_LSR_ZP,"lsr",ZP,2,NULL
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OP_LSR_ZP,"lsr",ZP,2,emul_lsr
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OP_RMB4_ZP,"rmb4",ZP,2,emul_rmb4
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OP_PHA,"pha",IMPLIED,1,emul_pha
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OP_EOR_IMM,"eor",IMMEDIATE,2,emul_eor
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OP_LSR,"lsr",ACCUMULATOR,1,NULL
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OP_LSR,"lsr",ACCUMULATOR,1,emul_lsr
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OP_NOPI_4C,"nop",IMPLIED,1,NULL
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OP_JMP_ABS,"jmp",ABSOLUTE,3,NULL
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OP_EOR_ABS,"eor",ABSOLUTE,3,emul_eor
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OP_LSR_ABS,"lsr",ABSOLUTE,3,NULL
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OP_LSR_ABS,"lsr",ABSOLUTE,3,emul_lsr
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OP_BBR4_REL,"bbr4",ZPR,2,NULL
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OP_BVC_REL,"bvc",RELATIVE,2,NULL
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OP_EOR_IZPY,"eor",IZPY,2,emul_eor
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@ -85,7 +85,7 @@ OP_EOR_IZP,"eor",IZP,2,emul_eor
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OP_NOPI_54,"nop",IMPLIED,1,NULL
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OP_NOPI_55,"nop",ZPX,2,NULL
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OP_EOR_ZPX,"eor",ZPX,2,emul_eor
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OP_LSR_ZPX,"lsr",ZPX,2,NULL
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OP_LSR_ZPX,"lsr",ZPX,2,emul_lsr
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OP_RMB5_ZP,"rmb5",ZP,2,emul_rmb5
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OP_CLI,"cli",IMPLIED,1,NULL
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OP_EOR_ABSY,"eor",ABSOLUTEY,3,emul_eor
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@ -93,7 +93,7 @@ OP_PHY,"phy",IMPLIED,1,emul_phy
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OP_NOPI_5C,"nop",IMPLIED,1,NULL
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OP_NOPI_5D,"nop",ABSOLUTE,3,NULL
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OP_EOR_ABSX,"eor",ABSOLUTEX,3,emul_eor
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OP_LSR_ABSX,"lsr",ABSOLUTEX,3,NULL
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OP_LSR_ABSX,"lsr",ABSOLUTEX,3,emul_lsr
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OP_BBR5_REL,"bbr5",ZPR,2,NULL
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OP_RTS,"rts",IMPLIED,1,NULL
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OP_ADC_IZPX,"adc",IZPX,2,NULL
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@ -17,6 +17,32 @@ emul_and(rk65c02emu_t *e, void *id, instruction_t *i)
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instruction_status_adjust_negative(e, e->regs.A);
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}
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/* ASL - shift left one bit */
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void
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emul_asl(rk65c02emu_t *e, void *id, instruction_t *i)
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{
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bool ncarry;
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uint8_t val;
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ncarry = false;
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val = instruction_data_read_1(e, (instrdef_t *) id, i);
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/* carry flag value equals contents of bit 7 */
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if (val & 0x80)
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e->regs.P |= P_CARRY;
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else
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e->regs.P &= ~P_CARRY;
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/* shift left by one bit */
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val <<= 1;
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instruction_status_adjust_zero(e, val);
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instruction_status_adjust_negative(e, val);
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instruction_data_write_1(e, (instrdef_t *) id, i, val);
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}
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/* BIT - check if one or more bits are set */
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void
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emul_bit(rk65c02emu_t *e, void *id, instruction_t *i)
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@ -158,6 +184,29 @@ emul_ldy(rk65c02emu_t *e, void *id, instruction_t *i)
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instruction_status_adjust_negative(e, e->regs.Y);
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}
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/* LSR - shift right one bit */
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void
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emul_lsr(rk65c02emu_t *e, void *id, instruction_t *i)
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{
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uint8_t val;
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val = instruction_data_read_1(e, (instrdef_t *) id, i);
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/* carry flag value equals contents of bit 0 */
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if (val & 0x1)
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e->regs.P |= P_CARRY;
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else
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e->regs.P &= ~P_CARRY;
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/* shift right by one bit */
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val >>= 1;
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instruction_status_adjust_zero(e, val);
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/* XXX: cannot ever be negative */
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instruction_status_adjust_negative(e, val);
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instruction_data_write_1(e, (instrdef_t *) id, i, val);
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}
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/* NOP - do nothing */
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void
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emul_nop(rk65c02emu_t *e, void *id, instruction_t *i)
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