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Add emulation of BIT instruction and test cases for it.

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This commit is contained in:
Radosław Kujawa 2017-01-25 10:10:00 +01:00
parent 7915657355
commit acc0fad32e
8 changed files with 94 additions and 5 deletions
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10
src/65c02isa.csv
View File

@ -35,7 +35,7 @@ OP_JSR,"jsr",ABSOLUTE,3,NULL
OP_AND_IZPX,"and",IZPX,2,emul_and
OP_NOPI_23,"nop",IMMEDIATE,2,NULL
OP_NOPI_24,"nop",IMPLIED,1,NULL
OP_BIT_ZP,"bit",ZP,2,NULL
OP_BIT_ZP,"bit",ZP,2,emul_bit
OP_AND_ZP,"and",ZP,2,emul_and
OP_ROL_ZP,"rol",ZP,2,emul_rol
OP_RMB2_ZP,"rmb2",ZP,2,NULL
@ -43,7 +43,7 @@ OP_PLP,"plp",IMPLIED,1,emul_plp
OP_AND_IMM,"and",IMMEDIATE,2,emul_and
OP_ROL,"rol",ACCUMULATOR,1,emul_rol
OP_NOPI_2C,"nop",IMPLIED,1,NULL
OP_BIT_ABS,"bit",ABSOLUTE,3,NULL
OP_BIT_ABS,"bit",ABSOLUTE,3,emul_bit
OP_AND_ABS,"and",ABSOLUTE,3,emul_and
OP_ROL_ABS,"rol",ABSOLUTE,3,emul_rol
OP_BBR2_REL,"bbr2",ZPR,2,NULL
@ -51,7 +51,7 @@ OP_BMI_REL,"bmi",RELATIVE,2,NULL
OP_AND_IZPY,"and",IZPY,2,emul_and
OP_AND_IZP,"and",IZP,2,emul_and
OP_NOPI_34,"nop",IMPLIED,1,NULL
OP_BIT_ZPX,"bit",ZPX,2,NULL
OP_BIT_ZPX,"bit",ZPX,2,emul_bit
OP_AND_ZPX,"and",ZPX,2,emul_and
OP_ROL_ZPX,"rol",ZPX,2,emul_rol
OP_RMB3_ZP,"rmb3",ZP,2,NULL
@ -59,7 +59,7 @@ OP_SEC,"sec",IMPLIED,1,emul_sec
OP_AND_ABSY,"and",ABSOLUTEY,3,emul_and
OP_DEC,"dec",ACCUMULATOR,1,NULL
OP_NOPI_3C,"nop",IMPLIED,1,NULL
OP_BIT_ABSX,"bit",ABSOLUTEX,3,NULL
OP_BIT_ABSX,"bit",ABSOLUTEX,3,emul_bit
OP_AND_ABSX,"and",ABSOLUTEX,3,emul_and
OP_ROL_ABSX,"rol",ABSOLUTEX,3,emul_rol
OP_BBR3_REL,"bbr3",ZPR,2,NULL
@ -136,7 +136,7 @@ OP_STA_ZP,"sta",ZP,2,emul_sta
OP_STX_ZP,"stx",ZP,2,emul_stx
OP_SMB0_ZP,"smb0",ZP,2,NULL
OP_DEY,"dey",IMPLIED,1,emul_dey
OP_BIT_IMM,"bit",IMMEDIATE,2,NULL
OP_BIT_IMM,"bit",IMMEDIATE,2,emul_bit
OP_TXA,"txa",IMPLIED,1,emul_txa
OP_NOPI_8C,"nop",IMPLIED,1,NULL
OP_STY_ABS,"sty",ABSOLUTE,3,emul_sty

1 opcode_id mnemonic addressing size emulation
35 OP_AND_IZPX and IZPX 2 emul_and
36 OP_NOPI_23 nop IMMEDIATE 2 NULL
37 OP_NOPI_24 nop IMPLIED 1 NULL
38 OP_BIT_ZP bit ZP 2 NULL emul_bit
39 OP_AND_ZP and ZP 2 emul_and
40 OP_ROL_ZP rol ZP 2 emul_rol
41 OP_RMB2_ZP rmb2 ZP 2 NULL
43 OP_AND_IMM and IMMEDIATE 2 emul_and
44 OP_ROL rol ACCUMULATOR 1 emul_rol
45 OP_NOPI_2C nop IMPLIED 1 NULL
46 OP_BIT_ABS bit ABSOLUTE 3 NULL emul_bit
47 OP_AND_ABS and ABSOLUTE 3 emul_and
48 OP_ROL_ABS rol ABSOLUTE 3 emul_rol
49 OP_BBR2_REL bbr2 ZPR 2 NULL
51 OP_AND_IZPY and IZPY 2 emul_and
52 OP_AND_IZP and IZP 2 emul_and
53 OP_NOPI_34 nop IMPLIED 1 NULL
54 OP_BIT_ZPX bit ZPX 2 NULL emul_bit
55 OP_AND_ZPX and ZPX 2 emul_and
56 OP_ROL_ZPX rol ZPX 2 emul_rol
57 OP_RMB3_ZP rmb3 ZP 2 NULL
59 OP_AND_ABSY and ABSOLUTEY 3 emul_and
60 OP_DEC dec ACCUMULATOR 1 NULL
61 OP_NOPI_3C nop IMPLIED 1 NULL
62 OP_BIT_ABSX bit ABSOLUTEX 3 NULL emul_bit
63 OP_AND_ABSX and ABSOLUTEX 3 emul_and
64 OP_ROL_ABSX rol ABSOLUTEX 3 emul_rol
65 OP_BBR3_REL bbr3 ZPR 2 NULL
136 OP_STX_ZP stx ZP 2 emul_stx
137 OP_SMB0_ZP smb0 ZP 2 NULL
138 OP_DEY dey IMPLIED 1 emul_dey
139 OP_BIT_IMM bit IMMEDIATE 2 NULL emul_bit
140 OP_TXA txa IMPLIED 1 emul_txa
141 OP_NOPI_8C nop IMPLIED 1 NULL
142 OP_STY_ABS sty ABSOLUTE 3 emul_sty

24
src/emulation.c
View File

@ -12,6 +12,30 @@ emul_and(rk65c02emu_t *e, void *id, instruction_t *i)
instruction_status_adjust_negative(e, e->regs.A);
}
/* BIT - check if one or more bits are set */
void
emul_bit(rk65c02emu_t *e, void *id, instruction_t *i)
{
/* uint8_t v = instruction_data_read_1(e, (instrdef_t *) id, i);
printf("%x\n", v);*/
/* zero flag set if acculumator AND memory equals zero */
if (e->regs.A & instruction_data_read_1(e, (instrdef_t *) id, i))
e->regs.P &= ~P_ZERO;
else
e->regs.P |= P_ZERO;
if (BIT(instruction_data_read_1(e, (instrdef_t *) id, i), 6))
e->regs.P |= P_SIGN_OVERFLOW;
else
e->regs.P &= ~P_SIGN_OVERFLOW;
if (BIT(instruction_data_read_1(e, (instrdef_t *) id, i), 7))
e->regs.P |= P_NEGATIVE;
else
e->regs.P &= ~P_NEGATIVE;
}
/* CLC - clear carry flag */
void
emul_clc(rk65c02emu_t *e, void *id, instruction_t *i)

50
test/test_emulation.c
View File

@ -22,6 +22,55 @@ rom_start(rk65c02emu_t *e, const char *name)
return true;
}
ATF_TC_WITHOUT_HEAD(emul_bit);
ATF_TC_BODY(emul_bit, tc)
{
rk65c02emu_t e;
bus_t b;
b = bus_init();
e = rk65c02_init(&b);
/* BIT immediate */
e.regs.A = 0x40;
ATF_REQUIRE(rom_start(&e, "test_emulation_bit_imm.rom"));
ATF_CHECK(!(e.regs.P & P_ZERO));
ATF_CHECK(e.regs.P & P_SIGN_OVERFLOW);
ATF_CHECK(!(e.regs.P & P_NEGATIVE));
/* BIT zero page */
e.regs.A = 0x40;
bus_write_1(&b, 0x10, 0x80);
ATF_REQUIRE(rom_start(&e, "test_emulation_bit_zp.rom"));
ATF_CHECK(e.regs.P & P_ZERO);
ATF_CHECK(!(e.regs.P & P_SIGN_OVERFLOW));
ATF_CHECK(e.regs.P & P_NEGATIVE);
/* BIT zero page X */
e.regs.A = 0x40;
e.regs.X = 0x1;
bus_write_1(&b, 0x10, 0x40);
ATF_REQUIRE(rom_start(&e, "test_emulation_bit_zpx.rom"));
ATF_CHECK(!(e.regs.P & P_ZERO));
ATF_CHECK(e.regs.P & P_SIGN_OVERFLOW);
ATF_CHECK(!(e.regs.P & P_NEGATIVE));
/* BIT absolute */
e.regs.A = 0x80;
bus_write_1(&b, 0x2010, 0x80);
ATF_REQUIRE(rom_start(&e, "test_emulation_bit_abs.rom"));
ATF_CHECK(!(e.regs.P & P_ZERO));
ATF_CHECK(!(e.regs.P & P_SIGN_OVERFLOW));
ATF_CHECK(e.regs.P & P_NEGATIVE);
/* BIT absolute X */
e.regs.A = 0x40;
e.regs.X = 0x2;
bus_write_1(&b, 0x2010, 0x80);
ATF_REQUIRE(rom_start(&e, "test_emulation_bit_absx.rom"));
ATF_CHECK(e.regs.P & P_ZERO);
ATF_CHECK(!(e.regs.P & P_SIGN_OVERFLOW));
ATF_CHECK(e.regs.P & P_NEGATIVE);
bus_finish(&b);
}
ATF_TC_WITHOUT_HEAD(emul_dex_dey);
ATF_TC_BODY(emul_dex_dey, tc)
{
@ -424,6 +473,7 @@ ATF_TC_BODY(emul_php_plp, tc)
ATF_TP_ADD_TCS(tp)
{
ATF_TP_ADD_TC(tp, emul_and);
ATF_TP_ADD_TC(tp, emul_bit);
ATF_TP_ADD_TC(tp, emul_dex_dey);
ATF_TP_ADD_TC(tp, emul_clc_sec);
ATF_TP_ADD_TC(tp, emul_inx_iny);

3
test/test_emulation_bit_abs.s Normal file
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@ -0,0 +1,3 @@
start: bit 0x2010
stp

3
test/test_emulation_bit_absx.s Normal file
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@ -0,0 +1,3 @@
start: bit 0x200E,X
stp

3
test/test_emulation_bit_imm.s Normal file
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@ -0,0 +1,3 @@
start: bit #0x55
stp

3
test/test_emulation_bit_zp.s Normal file
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@ -0,0 +1,3 @@
start: bit 0x10
stp

3
test/test_emulation_bit_zpx.s Normal file
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@ -0,0 +1,3 @@
start: bit 0xF,X
stp