Add RMB emulation.

src/65c02isa.csv

@@ -6,7 +6,7 @@ OP_NOPI_4,"nop",IMPLIED,1,NULL
 OP_TSB_ZP,"tsb",ZP,2,NULL
 OP_ORA_ZP,"ora",ZP,2,emul_ora
 OP_ASL_ZP,"asl",ZP,2,NULL
-OP_RMB0_ZP,"rmb0",ZP,2,NULL
+OP_RMB0_ZP,"rmb0",ZP,2,emul_rmb0
 OP_PHP,"php",IMPLIED,1,emul_php
 OP_ORA_IMM,"ora",IMMEDIATE,2,emul_ora
 OP_ASL,"asl",ACCUMULATOR,1,NULL
@@ -22,7 +22,7 @@ OP_NOPI_14,"nop",IMPLIED,1,NULL
 OP_TRB_ZP,"trb",ZP,2,NULL
 OP_ORA_ZPX,"ora",ZPX,2,emul_ora
 OP_ASL_ZPX,"asl",ZPX,2,NULL
-OP_RMB1_ZP,"rmb1",ZP,1,NULL
+OP_RMB1_ZP,"rmb1",ZP,1,emul_rmb1
 OP_CLC,"clc",IMPLIED,1,emul_clc
 OP_ORA_ABSY,"ora",ABSOLUTEY,3,emul_ora
 OP_INC,"inc",ACCUMULATOR,1,emul_inc
@@ -38,7 +38,7 @@ OP_NOPI_24,"nop",IMPLIED,1,NULL
 OP_BIT_ZP,"bit",ZP,2,emul_bit
 OP_AND_ZP,"and",ZP,2,emul_and
 OP_ROL_ZP,"rol",ZP,2,emul_rol
-OP_RMB2_ZP,"rmb2",ZP,2,NULL
+OP_RMB2_ZP,"rmb2",ZP,2,emul_rmb2
 OP_PLP,"plp",IMPLIED,1,emul_plp
 OP_AND_IMM,"and",IMMEDIATE,2,emul_and
 OP_ROL,"rol",ACCUMULATOR,1,emul_rol
@@ -54,7 +54,7 @@ OP_NOPI_34,"nop",IMPLIED,1,NULL
 OP_BIT_ZPX,"bit",ZPX,2,emul_bit
 OP_AND_ZPX,"and",ZPX,2,emul_and
 OP_ROL_ZPX,"rol",ZPX,2,emul_rol
-OP_RMB3_ZP,"rmb3",ZP,2,NULL
+OP_RMB3_ZP,"rmb3",ZP,2,emul_rmb3
 OP_SEC,"sec",IMPLIED,1,emul_sec
 OP_AND_ABSY,"and",ABSOLUTEY,3,emul_and
 OP_DEC,"dec",ACCUMULATOR,1,emul_dec
@@ -70,7 +70,7 @@ OP_NOPI_44,"nop",IMPLIED,1,NULL
 OP_NOPI_45,"nop",ZP,2,NULL
 OP_EOR_ZP,"eor",ZP,2,emul_eor
 OP_LSR_ZP,"lsr",ZP,2,NULL
-OP_RMB4_ZP,"rmb4",ZP,2,NULL
+OP_RMB4_ZP,"rmb4",ZP,2,emul_rmb4
 OP_PHA,"pha",IMPLIED,1,emul_pha
 OP_EOR_IMM,"eor",IMMEDIATE,2,emul_eor
 OP_LSR,"lsr",ACCUMULATOR,1,NULL
@@ -86,7 +86,7 @@ OP_NOPI_54,"nop",IMPLIED,1,NULL
 OP_NOPI_55,"nop",ZPX,2,NULL
 OP_EOR_ZPX,"eor",ZPX,2,emul_eor
 OP_LSR_ZPX,"lsr",ZPX,2,NULL
-OP_RMB5_ZP,"rmb5",ZP,2,NULL
+OP_RMB5_ZP,"rmb5",ZP,2,emul_rmb5
 OP_CLI,"cli",IMPLIED,1,NULL
 OP_EOR_ABSY,"eor",ABSOLUTEY,3,emul_eor
 OP_PHY,"phy",IMPLIED,1,emul_phy
@@ -102,7 +102,7 @@ OP_NOPI_64,"nop",IMPLIED,1,NULL
 OP_STZ_ZP,"stz",ZP,2,emul_stz
 OP_ADC_ZP,"adc",ZP,2,NULL
 OP_ROR_ZP,"ror",ZP,2,emul_ror
-OP_RMB6_ZP,"rmb6",ZP,2,NULL
+OP_RMB6_ZP,"rmb6",ZP,2,emul_rmb6
 OP_PLA,"pla",IMPLIED,1,emul_pla
 OP_ADC_IMM,"adc",IMMEDIATE,2,NULL
 OP_ROR,"ror",ACCUMULATOR,1,emul_ror
@@ -118,7 +118,7 @@ OP_NOPI_74,"nop",IMPLIED,1,NULL
 OP_STZ_ZPX,"stz",ZPX,2,emul_stz
 OP_ADC_ZPX,"adc",ZPX,2,NULL
 OP_ROR_ZPX,"ror",ZPX,2,emul_ror
-OP_RMB7_ZP,"rmb7",ZP,2,NULL
+OP_RMB7_ZP,"rmb7",ZP,2,emul_rmb7
 OP_SEI,"sei",IMPLIED,1,NULL
 OP_ADC_ABSY,"adc",ABSOLUTEY,3,NULL
 OP_PLY,"ply",IMPLIED,1,emul_ply

src/emulation.c

@@ -2,6 +2,11 @@
 
 #include "emulation.h"
 
+/* RMB, SMB, BBR, BBS are handled specially */
+void emul_rmb(rk65c02emu_t *, void *, instruction_t *, uint8_t);
+
+/* Implementation of emulation of instructions follows below */
+
 /* AND - logical AND */
 void
 emul_and(rk65c02emu_t *e, void *id, instruction_t *i)
@@ -228,6 +233,60 @@ emul_ply(rk65c02emu_t *e, void *id, instruction_t *i)
 	e->regs.Y = stack_pop(e);
 }
 
+/* RMBx - reset or set memory bit (handles RMB0-RMB7) */
+void
+emul_rmb(rk65c02emu_t *e, void *id, instruction_t *i, uint8_t bit)
+{
+	uint8_t val;
+
+	val = instruction_data_read_1(e, (instrdef_t *) id, i);
+
+	val &= ~(1 << bit);
+
+	instruction_data_write_1(e, id, i, val);
+}
+
+void
+emul_rmb0(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 0);
+}
+void
+emul_rmb1(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 1);
+}
+void
+emul_rmb2(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 2);
+}
+void
+emul_rmb3(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 3);
+}
+void
+emul_rmb4(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 4);
+}
+void
+emul_rmb5(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 5);
+}
+void
+emul_rmb6(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 6);
+}
+void
+emul_rmb7(rk65c02emu_t *e, void *id, instruction_t *i)
+{
+	emul_rmb(e, id, i, 7);
+}
+
 /* ROL - rotate left */
 void
 emul_rol(rk65c02emu_t *e, void *id, instruction_t *i)