mirror of
https://github.com/rkujawa/rk65c02.git
synced 2024-12-11 18:49:16 +00:00
128 lines
2.9 KiB
C
128 lines
2.9 KiB
C
#include <atf-c.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <stdbool.h>
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#include <string.h>
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#include "bus.h"
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#include "rk65c02.h"
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#include "instruction.h"
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#include "log.h"
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#include "device_ram.h"
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#include "utils.h"
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#define ISR_ADDR 0xC100
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/*
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* Test case for software generated interrupt (by BRK instruction).
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*/
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ATF_TC_WITHOUT_HEAD(intr_brk);
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ATF_TC_BODY(intr_brk, tc)
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{
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const uint16_t isr_addr = ISR_ADDR;
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rk65c02emu_t e;
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bus_t b;
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rk65c02_loglevel_set(LOG_TRACE);
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b = bus_init_with_default_devs();
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bus_device_add(&b, device_ram_init(0x100), 0xFF00);
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e = rk65c02_init(&b);
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e.regs.PC = ROM_LOAD_ADDR;
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e.regs.SP = 0xFF;
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bus_write_1(&b, 0x10, 0x40);
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ATF_REQUIRE(bus_load_file(&b, ROM_LOAD_ADDR,
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rom_path("test_interrupt_brk.rom", tc)));
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ATF_REQUIRE(bus_load_file(&b, isr_addr,
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rom_path("test_interrupt_brk_isr.rom", tc)));
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bus_write_1(&b, VECTOR_IRQ, isr_addr & 0xFF);
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bus_write_1(&b, VECTOR_IRQ+1, isr_addr >> 8);
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/* Execute first instruction, of the main program, which is a nop... */
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rk65c02_step(&e, 1);
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rk65c02_dump_regs(e.regs);
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/* BRK is next, save its address... */
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//brkaddr = e.regs.PC + 1;
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/* Execute BRK instruction, which should start ISR (regardless of IRQ disable flag). */
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rk65c02_step(&e, 1);
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rk65c02_dump_regs(e.regs);
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rk65c02_dump_stack(&e, 0x4);
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/* Are we in ISR really? */
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ATF_CHECK(e.regs.PC == isr_addr);
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ATF_CHECK(e.regs.P & P_IRQ_DISABLE);
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/* XXX: separate test case is needed to check return to main program. */
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/*
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rk65c02_step(&e, 1);
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rk65c02_dump_regs(e.regs);
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rk65c02_start(&e);
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*/
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}
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/*
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* Test case for return from interrupt by RTI instruction.
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*/
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ATF_TC_WITHOUT_HEAD(intr_rti);
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ATF_TC_BODY(intr_rti, tc)
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{
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bus_t b;
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rk65c02emu_t e;
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uint8_t *asmbuf;
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uint16_t israsmpc;
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uint8_t bsize;
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b = bus_init_with_default_devs();
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e = rk65c02_init(&b);
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israsmpc = ISR_ADDR;
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ATF_REQUIRE(assemble_single_buf_implied(&asmbuf, &bsize, "nop"));
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ATF_REQUIRE(bus_load_buf(&b, israsmpc, asmbuf, bsize));
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israsmpc += bsize;
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ATF_REQUIRE(assemble_single_buf_implied(&asmbuf, &bsize, "rti"));
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ATF_REQUIRE(bus_load_buf(&b, israsmpc, asmbuf, bsize));
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israsmpc += bsize;
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ATF_REQUIRE(assemble_single_buf_implied(&asmbuf, &bsize, "nop"));
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ATF_REQUIRE(bus_load_buf(&b, ROM_LOAD_ADDR, asmbuf, bsize));
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/* There's a return address and saved processor flags on stack. */
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e.regs.SP = 0xFF;
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stack_push(&e, ROM_LOAD_ADDR >> 8);
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stack_push(&e, ROM_LOAD_ADDR & 0xFF);
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stack_push(&e, e.regs.P);
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/* We're in the middle of interrupt service routine, just before RTI. */
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e.regs.PC = ISR_ADDR;
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rk65c02_step(&e, 1);
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ATF_CHECK(e.regs.PC == ISR_ADDR + 1);
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rk65c02_dump_regs(e.regs);
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rk65c02_dump_stack(&e, 0x4);
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/* Step onto RTI. */
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rk65c02_step(&e, 1);
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rk65c02_dump_regs(e.regs);
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/* Check if we're back in the main program. */
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ATF_CHECK(e.regs.PC == ROM_LOAD_ADDR);
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}
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ATF_TP_ADD_TCS(tp)
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{
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ATF_TP_ADD_TC(tp, intr_brk);
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ATF_TP_ADD_TC(tp, intr_rti);
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return (atf_no_error());
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}
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