mirror of https://github.com/sethm/symon.git
Cleanup some IntelliJ IDEA warnings
Cleaning up some warnings for the first time in many eons.
This commit is contained in:
Seth Morabito
parent
5f8f743f7d
commit
b36b442b14
10
pom.xml
10
pom.xml
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@ -19,7 +19,7 @@
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<dependency>
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<groupId>ch.qos.logback</groupId>
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<artifactId>logback-classic</artifactId>
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<version>1.2.3</version>
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<version>1.4.5</version>
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</dependency>
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<dependency>
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<groupId>junit</groupId>
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@ -30,13 +30,13 @@
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<dependency>
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<groupId>org.mockito</groupId>
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<artifactId>mockito-core</artifactId>
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<version>3.12.4</version>
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<version>4.8.0</version>
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<scope>test</scope>
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</dependency>
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<dependency>
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<groupId>commons-cli</groupId>
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<artifactId>commons-cli</artifactId>
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<version>1.4</version>
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<version>1.5.0</version>
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</dependency>
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</dependencies>
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@ -79,8 +79,8 @@
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<version>3.7.0</version>
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<configuration>
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<compilerArgument>-Xlint:unchecked</compilerArgument>
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<source>1.7</source>
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<target>1.7</target>
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<source>11</source>
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<target>11</target>
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</configuration>
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</plugin>
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@ -15,7 +15,7 @@
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* NON-INFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE
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* LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
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* OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
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* WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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@ -32,7 +32,7 @@ import org.slf4j.LoggerFactory;
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/**
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* This class provides a simulation of the MOS 6502 CPU's state machine.
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* A simple interface allows this 6502 to read and write to a simulated bus,
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* and exposes some of the internal state for inspection and debugging.
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* and exposes some internal state for inspection and debugging.
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*/
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public class Cpu implements InstructionTable {
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@ -283,7 +283,7 @@ public class Cpu implements InstructionTable {
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// Execute
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switch (state.ir) {
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/** Single Byte Instructions; Implied and Relative **/
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// Single Byte Instructions; Implied and Relative
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case 0x00: // BRK - Force Interrupt - Implied
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handleBrk(state.pc + 1);
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break;
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@ -457,7 +457,7 @@ public class Cpu implements InstructionTable {
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setArithmeticFlags(state.x);
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break;
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/** JMP *****************************************************************/
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// JMP
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case 0x4c: // JMP - Absolute
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state.pc = Utils.address(state.args[0], state.args[1]);
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break;
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@ -495,7 +495,7 @@ public class Cpu implements InstructionTable {
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state.pc = Utils.address(bus.read(lo, true), bus.read(hi, true));
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break;
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/** ORA - Logical Inclusive Or ******************************************/
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// ORA - Logical Inclusive Or
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case 0x09: // #Immediate
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state.a |= state.args[0];
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setArithmeticFlags(state.a);
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@ -517,7 +517,7 @@ public class Cpu implements InstructionTable {
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break;
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/** ASL - Arithmetic Shift Left *****************************************/
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// ASL - Arithmetic Shift Left
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case 0x0a: // Accumulator
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state.a = asl(state.a);
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setArithmeticFlags(state.a);
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@ -532,7 +532,7 @@ public class Cpu implements InstructionTable {
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break;
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/** BIT - Bit Test ******************************************************/
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// BIT - Bit Test
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case 0x89: // 65C02 #Immediate
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setZeroFlag((state.a & state.args[0]) == 0);
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break;
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@ -551,7 +551,7 @@ public class Cpu implements InstructionTable {
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break;
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/** AND - Logical AND ***************************************************/
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// AND - Logical AND
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case 0x29: // #Immediate
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state.a &= state.args[0];
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setArithmeticFlags(state.a);
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@ -573,7 +573,7 @@ public class Cpu implements InstructionTable {
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break;
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/** ROL - Rotate Left ***************************************************/
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// ROL - Rotate Left
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case 0x2a: // Accumulator
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state.a = rol(state.a);
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setArithmeticFlags(state.a);
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@ -588,7 +588,7 @@ public class Cpu implements InstructionTable {
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break;
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/** EOR - Exclusive OR **************************************************/
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// EOR - Exclusive OR
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case 0x49: // #Immediate
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state.a ^= state.args[0];
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setArithmeticFlags(state.a);
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@ -610,7 +610,7 @@ public class Cpu implements InstructionTable {
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break;
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/** LSR - Logical Shift Right *******************************************/
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// LSR - Logical Shift Right
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case 0x4a: // Accumulator
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state.a = lsr(state.a);
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setArithmeticFlags(state.a);
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@ -625,7 +625,7 @@ public class Cpu implements InstructionTable {
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break;
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/** ADC - Add with Carry ************************************************/
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// ADC - Add with Carry
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case 0x69: // #Immediate
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if (state.decimalModeFlag) {
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state.a = adcDecimal(state.a, state.args[0]);
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@ -653,7 +653,7 @@ public class Cpu implements InstructionTable {
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break;
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/** ROR - Rotate Right **************************************************/
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// ROR - Rotate Right
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case 0x6a: // Accumulator
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state.a = ror(state.a);
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setArithmeticFlags(state.a);
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@ -668,7 +668,7 @@ public class Cpu implements InstructionTable {
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break;
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/** STA - Store Accumulator *********************************************/
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// STA - Store Accumulator
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case 0x92: // 65C02 STA (ZP)
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if (behavior == CpuBehavior.NMOS_6502 ||
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behavior == CpuBehavior.NMOS_WITH_ROR_BUG) {
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@ -685,7 +685,7 @@ public class Cpu implements InstructionTable {
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break;
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/** STY - Store Y Register **********************************************/
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// STY - Store Y Register
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case 0x84: // Zero Page
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case 0x8c: // Absolute
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case 0x94: // Zero Page,X
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@ -693,14 +693,14 @@ public class Cpu implements InstructionTable {
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break;
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/** STX - Store X Register **********************************************/
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// STX - Store X Register
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case 0x86: // Zero Page
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case 0x8e: // Absolute
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case 0x96: // Zero Page,Y
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bus.write(effectiveAddress, state.x);
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break;
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/** STZ - 65C02 Store Zero ****************************************************/
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// STZ - 65C02 Store Zero
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case 0x64: // Zero Page
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case 0x74: // Zero Page,X
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case 0x9c: // Absolute
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@ -712,7 +712,7 @@ public class Cpu implements InstructionTable {
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bus.write(effectiveAddress, 0);
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break;
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/** LDY - Load Y Register ***********************************************/
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// LDY - Load Y Register
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case 0xa0: // #Immediate
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state.y = state.args[0];
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setArithmeticFlags(state.y);
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@ -726,7 +726,7 @@ public class Cpu implements InstructionTable {
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break;
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/** LDX - Load X Register ***********************************************/
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// LDX - Load X Register
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case 0xa2: // #Immediate
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state.x = state.args[0];
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setArithmeticFlags(state.x);
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@ -740,7 +740,7 @@ public class Cpu implements InstructionTable {
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break;
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/** LDA - Load Accumulator **********************************************/
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// LDA - Load Accumulator
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case 0xa9: // #Immediate
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state.a = state.args[0];
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setArithmeticFlags(state.a);
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@ -762,7 +762,7 @@ public class Cpu implements InstructionTable {
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break;
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/** CPY - Compare Y Register ********************************************/
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// CPY - Compare Y Register
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case 0xc0: // #Immediate
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cmp(state.y, state.args[0]);
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break;
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@ -772,7 +772,7 @@ public class Cpu implements InstructionTable {
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break;
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/** CMP - Compare Accumulator *******************************************/
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// CMP - Compare Accumulator
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case 0xc9: // #Immediate
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cmp(state.a, state.args[0]);
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break;
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@ -792,7 +792,7 @@ public class Cpu implements InstructionTable {
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break;
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/** DEC - Decrement Memory **********************************************/
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// DEC - Decrement Memory
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case 0x3a: // 65C02 Immediate
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if (behavior == CpuBehavior.NMOS_6502 ||
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behavior == CpuBehavior.NMOS_WITH_ROR_BUG) {
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@ -811,7 +811,7 @@ public class Cpu implements InstructionTable {
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break;
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/** CPX - Compare X Register ********************************************/
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// CPX - Compare X Register
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case 0xe0: // #Immediate
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cmp(state.x, state.args[0]);
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break;
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@ -821,7 +821,7 @@ public class Cpu implements InstructionTable {
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break;
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/** SBC - Subtract with Carry (Borrow) **********************************/
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// SBC - Subtract with Carry (Borrow)
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case 0xe9: // #Immediate
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if (state.decimalModeFlag) {
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state.a = sbcDecimal(state.a, state.args[0]);
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@ -849,7 +849,7 @@ public class Cpu implements InstructionTable {
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break;
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/** INC - Increment Memory **********************************************/
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// INC - Increment Memory
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case 0x1a: // 65C02 Increment Immediate
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if (behavior == CpuBehavior.NMOS_6502 ||
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behavior == CpuBehavior.NMOS_WITH_ROR_BUG) {
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@ -868,14 +868,14 @@ public class Cpu implements InstructionTable {
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break;
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/** 65C02 RMB - Reset Memory Bit **************************************/
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// 65C02 RMB - Reset Memory Bit
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case 0x07: // 65C02 RMB0 - Zero Page
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if (behavior == CpuBehavior.NMOS_6502 ||
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behavior == CpuBehavior.NMOS_WITH_ROR_BUG) {
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break;
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}
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tmp = bus.read(effectiveAddress, true) & 0xff;
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tmp &= ~(1 << 0);
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tmp &= ~1;
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bus.write(effectiveAddress, tmp);
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break;
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case 0x17: // 65C02 RMB1 - Zero Page
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@ -943,14 +943,14 @@ public class Cpu implements InstructionTable {
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break;
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/** 65C02 SMB - Set Memory Bit **************************************/
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// 65C02 SMB - Set Memory Bit
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case 0x87: // 65C02 SMB0 - Zero Page
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if (behavior == CpuBehavior.NMOS_6502 ||
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behavior == CpuBehavior.NMOS_WITH_ROR_BUG) {
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break;
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}
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tmp = bus.read(effectiveAddress, true) & 0xff;
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tmp |= (1);
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tmp |= 1;
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bus.write(effectiveAddress, tmp);
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break;
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case 0x97: // 65C02 SMB1 - Zero Page
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@ -1017,7 +1017,7 @@ public class Cpu implements InstructionTable {
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bus.write(effectiveAddress, tmp);
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break;
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/** 65C02 TRB/TSB - Test and Reset Bit/Test and Set Bit ***************/
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// 65C02 TRB/TSB - Test and Reset Bit/Test and Set Bit
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case 0x14: // 65C02 TRB - Test and Reset bit - Zero Page
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case 0x1c: // 65C02 TRB - Test and Reset bit - Absolute
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if (behavior == CpuBehavior.NMOS_6502 ||
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@ -1026,8 +1026,9 @@ public class Cpu implements InstructionTable {
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}
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tmp = bus.read(effectiveAddress, true);
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setZeroFlag((state.a & tmp) == 0);
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tmp = (tmp &= ~(state.a)) & 0xff;
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bus.write(effectiveAddress,tmp);
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tmp &= ~(state.a);
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tmp &= 0xff;
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bus.write(effectiveAddress, tmp);
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break;
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case 0x04: // 65C02 TSB - Test and Set bit - Zero Page
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@ -1038,18 +1039,19 @@ public class Cpu implements InstructionTable {
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}
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tmp = bus.read(effectiveAddress, true);
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setZeroFlag((state.a & tmp) == 0);
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tmp = (tmp |= (state.a)) & 0xff;
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tmp |= state.a;
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tmp = tmp & 0xff;
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bus.write(effectiveAddress,tmp);
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break;
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/** 65C02 BBR - Branch if Bit Reset *************************************/
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// 65C02 BBR - Branch if Bit Reset
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case 0x0f: // 65C02 BBR - Branch if bit 0 reset - Zero Page
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if (behavior == CpuBehavior.NMOS_6502 ||
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behavior == CpuBehavior.NMOS_WITH_ROR_BUG) {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 0) == 0) {
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if ((tmp & 1) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1060,7 +1062,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 1) == 0) {
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if ((tmp & (1 << 1)) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1071,7 +1073,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 2) == 0) {
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if ((tmp & (1 << 2)) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1082,7 +1084,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 3) == 0) {
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if ((tmp & (1 << 3)) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1093,7 +1095,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 4) == 0) {
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if ((tmp & (1 << 4)) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1105,7 +1107,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 5) == 0) {
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if ((tmp & (1 << 5)) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1116,7 +1118,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 6) == 0) {
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if ((tmp & (1 << 6)) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1127,20 +1129,20 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 7) == 0) {
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if ((tmp & (1 << 7)) == 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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/** 65C02 BBS - Branch if Bit Set ************************************/
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// 65C02 BBS - Branch if Bit Set
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case 0x8f: // 65C02 BBS - Branch if bit 0 set - Zero Page
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if (behavior == CpuBehavior.NMOS_6502 ||
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behavior == CpuBehavior.NMOS_WITH_ROR_BUG) {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 0) > 0) {
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if ((tmp & 1) != 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1151,7 +1153,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 1) > 0) {
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if ((tmp & (1 << 1)) != 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1162,7 +1164,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 2) > 0) {
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if ((tmp & (1 << 2)) > 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1173,7 +1175,7 @@ public class Cpu implements InstructionTable {
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break;
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}
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tmp = bus.read(effectiveAddress, true);
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if ((tmp & 1 << 3) > 0) {
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if ((tmp & (1 << 3)) > 0) {
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state.pc = relAddress(state.args[1]);
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}
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break;
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@ -1185,7 +1187,7 @@ public class Cpu implements InstructionTable {
|
|||
break;
|
||||
}
|
||||
tmp = bus.read(effectiveAddress, true);
|
||||
if ((tmp & 1 << 4) > 0) {
|
||||
if ((tmp & (1 << 4)) > 0) {
|
||||
state.pc = relAddress(state.args[1]);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1197,7 +1199,7 @@ public class Cpu implements InstructionTable {
|
|||
break;
|
||||
}
|
||||
tmp = bus.read(effectiveAddress, true);
|
||||
if ((tmp & 1 << 5) > 0) {
|
||||
if ((tmp & (1 << 5)) > 0) {
|
||||
state.pc = relAddress(state.args[1]);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1208,7 +1210,7 @@ public class Cpu implements InstructionTable {
|
|||
break;
|
||||
}
|
||||
tmp = bus.read(effectiveAddress, true);
|
||||
if ((tmp & 1 << 6) > 0) {
|
||||
if ((tmp & (1 << 6)) > 0) {
|
||||
state.pc = relAddress(state.args[1]);
|
||||
}
|
||||
break;
|
||||
|
|
@ -1219,13 +1221,13 @@ public class Cpu implements InstructionTable {
|
|||
break;
|
||||
}
|
||||
tmp = bus.read(effectiveAddress, true);
|
||||
if ((tmp & 1 << 7) > 0) {
|
||||
if ((tmp & (1 << 7)) > 0) {
|
||||
state.pc = relAddress(state.args[1]);
|
||||
}
|
||||
break;
|
||||
|
||||
|
||||
/** Unimplemented Instructions ****************************************/
|
||||
// Unimplemented Instructions
|
||||
// TODO: Create a flag to enable highly-accurate emulation of unimplemented instructions.
|
||||
default:
|
||||
setOpTrap();
|
||||
|
|
@ -1234,7 +1236,7 @@ public class Cpu implements InstructionTable {
|
|||
|
||||
delayLoop(state.ir);
|
||||
|
||||
// Peek ahead to the next insturction and arguments
|
||||
// Peek ahead to the next instruction and arguments
|
||||
peekAhead();
|
||||
}
|
||||
|
||||
|
|
@ -1265,7 +1267,7 @@ public class Cpu implements InstructionTable {
|
|||
/**
|
||||
* Handle the common behavior of BRK, /IRQ, and /NMI
|
||||
*
|
||||
* @throws MemoryAccessException
|
||||
* @throws MemoryAccessException on memory access failure
|
||||
*/
|
||||
private void handleInterrupt(int returnPc, int vectorLow, int vectorHigh, boolean isBreak) throws MemoryAccessException {
|
||||
|
||||
|
|
@ -1674,7 +1676,7 @@ public class Cpu implements InstructionTable {
|
|||
public void setProgramCounter(int addr) {
|
||||
state.pc = addr;
|
||||
|
||||
// As a side-effect of setting the program counter,
|
||||
// As a side effect of setting the program counter,
|
||||
// we want to peek ahead at the next state.
|
||||
try {
|
||||
peekAhead();
|
||||
|
|
@ -1971,7 +1973,7 @@ public class Cpu implements InstructionTable {
|
|||
*/
|
||||
public String disassembleOpAtAddress(int address) throws MemoryAccessException {
|
||||
int opCode = bus.read(address, true);
|
||||
int args[] = new int[2];
|
||||
int[] args = new int[2];
|
||||
int size = Cpu.instructionSizes[opCode];
|
||||
for (int i = 1; i < size; i++) {
|
||||
int nextRead = (address + i) % bus.endAddress();
|
||||
|
|
|
|||
|
|
@ -12,7 +12,7 @@ public class CpuState {
|
|||
public int a;
|
||||
|
||||
/**
|
||||
* X index regsiter
|
||||
* X index register
|
||||
*/
|
||||
public int x;
|
||||
|
||||
|
|
@ -61,13 +61,12 @@ public class CpuState {
|
|||
public CpuState() {}
|
||||
|
||||
/**
|
||||
* Snapshot a copy of the CpuState.
|
||||
*
|
||||
* (This is a copy constructor rather than an implementation of <code>Cloneable</code>
|
||||
* based on Josh Bloch's recommendation)
|
||||
* Snapshot a copy of the CpuState. (This is a copy constructor rather than an
|
||||
* implementation of <code>Cloneable</code> based on Josh Bloch's recommendation)
|
||||
*
|
||||
* @param s The CpuState to copy.
|
||||
*/
|
||||
@SuppressWarnings("CopyConstructorMissesField")
|
||||
public CpuState(CpuState s) {
|
||||
this.a = s.a;
|
||||
this.x = s.x;
|
||||
|
|
@ -83,6 +82,7 @@ public class CpuState {
|
|||
this.nextArgs[1] = s.nextArgs[1];
|
||||
this.instSize = s.instSize;
|
||||
this.opTrap = s.opTrap;
|
||||
this.nmiAsserted = s.nmiAsserted;
|
||||
this.irqAsserted = s.irqAsserted;
|
||||
this.carryFlag = s.carryFlag;
|
||||
this.negativeFlag = s.negativeFlag;
|
||||
|
|
|
|||
Loading…
Reference in New Issue