mirror of
https://github.com/nArnoSNES/tcc-65816.git
synced 2025-02-21 11:29:01 +00:00
135 lines
3.6 KiB
C
135 lines
3.6 KiB
C
/* Based on execute/simd-1.c, modified by joern.rennecke@st.com to
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trigger a reload bug. Verified for gcc mainline from 20050722 13:00 UTC
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for sh-elf -m4 -O2. */
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#ifndef STACK_SIZE
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#define STACK_SIZE (256*1024)
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#endif
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typedef struct { char c[STACK_SIZE/2]; } big_t;
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typedef int __attribute__((mode(SI))) __attribute__((vector_size (8))) vecint;
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typedef int __attribute__((mode(SI))) siint;
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vecint i = { 150, 100 };
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vecint j = { 10, 13 };
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vecint k;
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union {
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vecint v;
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siint i[2];
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} res;
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void
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verify (siint a1, siint a2, siint b1, siint b2, big_t big)
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{
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if (a1 != b1
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|| a2 != b2)
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abort ();
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}
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int
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main ()
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{
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big_t big;
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vecint k0, k1, k2, k3, k4, k5, k6, k7;
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k0 = i + j;
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res.v = k0;
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verify (res.i[0], res.i[1], 160, 113, big);
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k1 = i * j;
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res.v = k1;
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verify (res.i[0], res.i[1], 1500, 1300, big);
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k2 = i / j;
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/* This is the observed failure - reload 0 has the wrong type and thus the
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conflict with reload 1 is missed:
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(insn:HI 94 92 96 1 pr23135.c:46 (parallel [
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(set (subreg:SI (reg:DI 253) 0)
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(div:SI (reg:SI 4 r4)
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(reg:SI 5 r5)))
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(clobber (reg:SI 146 pr))
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(clobber (reg:DF 64 fr0))
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(clobber (reg:DF 66 fr2))
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(use (reg:PSI 151 ))
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(use (reg/f:SI 256))
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]) 60 {divsi3_i4} (insn_list:REG_DEP_TRUE 90 (insn_list:REG_DEP_TRUE 89
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(insn_list:REG_DEP_TRUE 42 (insn_list:REG_DEP_TRUE 83 (insn_list:REG_DEP_TRUE 92
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(insn_list:REG_DEP_TRUE 91 (nil)))))))
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(expr_list:REG_DEAD (reg:SI 4 r4)
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(expr_list:REG_DEAD (reg:SI 5 r5)
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(expr_list:REG_UNUSED (reg:DF 66 fr2)
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(expr_list:REG_UNUSED (reg:DF 64 fr0)
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(expr_list:REG_UNUSED (reg:SI 146 pr)
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(insn_list:REG_RETVAL 91 (nil))))))))
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Reloads for insn # 94
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Reload 0: reload_in (SI) = (plus:SI (reg/f:SI 14 r14)
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(const_int 64 [0x40]))
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GENERAL_REGS, RELOAD_FOR_OUTADDR_ADDRESS (opnum = 0)
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reload_in_reg: (plus:SI (reg/f:SI 14 r14)
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(const_int 64 [0x40]))
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reload_reg_rtx: (reg:SI 3 r3)
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Reload 1: GENERAL_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, se
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condary_reload_p
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reload_reg_rtx: (reg:SI 3 r3)
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Reload 2: reload_out (SI) = (mem:SI (plus:SI (plus:SI (reg/f:SI 14 r14)
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(const_int 64 [0x40]))
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(const_int 28 [0x1c])) [ 16 S8 A32])
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FPUL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
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reload_out_reg: (subreg:SI (reg:DI 253) 0)
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reload_reg_rtx: (reg:SI 150 fpul)
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secondary_out_reload = 1
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Reload 3: reload_in (SI) = (symbol_ref:SI ("__sdivsi3_i4") [flags 0x1])
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GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1), can't combine
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reload_in_reg: (reg/f:SI 256)
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reload_reg_rtx: (reg:SI 3 r3)
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*/
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res.v = k2;
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verify (res.i[0], res.i[1], 15, 7, big);
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k3 = i & j;
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res.v = k3;
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verify (res.i[0], res.i[1], 2, 4, big);
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k4 = i | j;
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res.v = k4;
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verify (res.i[0], res.i[1], 158, 109, big);
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k5 = i ^ j;
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res.v = k5;
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verify (res.i[0], res.i[1], 156, 105, big);
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k6 = -i;
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res.v = k6;
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verify (res.i[0], res.i[1], -150, -100, big);
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k7 = ~i;
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res.v = k7;
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verify (res.i[0], res.i[1], -151, -101, big);
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k = k0 + k1 + k3 + k4 + k5 + k6 + k7;
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res.v = k;
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verify (res.i[0], res.i[1], 1675, 1430, big);
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k = k0 * k1 * k3 * k4 * k5 * k6 * k7;
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res.v = k;
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verify (res.i[0], res.i[1], 1456467968, -1579586240, big);
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k = k0 / k1 / k2 / k3 / k4 / k5 / k6 / k7;
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res.v = k;
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verify (res.i[0], res.i[1], 0, 0, big);
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exit (0);
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}
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