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Start on 8051.
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Jeff Tranter
parent
915f0ea743
commit
5f6d4e3677
320
8051.py
Normal file
320
8051.py
Normal file
@ -0,0 +1,320 @@
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##########################################################################
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#
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# Processor specific code
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# CPU = "8080"
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# Description = "Intel 8051 8-bit microprocessor."
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# DataWidth = 8 # 8-bit data
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# AddressWidth = 16 # 16-bit addresses
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# Maximum length of an instruction (for formatting purposes)
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maxLength = 3
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# Leadin bytes for multibyte instructions
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leadInBytes = []
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# Addressing mode table
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# List of addressing modes and corresponding format strings for operands.
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addressModeTable = {
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"" : "",
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"addr11" : "${0:02X}",
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"addr16" : "${1:02X}{0:02X}",
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"direct" : "${0:02X}",
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"a" : "a",
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"r0" : "r0",
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"r1" : "r1",
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"r2" : "r2",
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"r3" : "r3",
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"r4" : "r4",
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"r5" : "r5",
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"r6" : "r6",
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"r7" : "r7",
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"@r0" : "@r0",
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"@r1" : "@r1",
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}
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# Op Code Table
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# Key is numeric opcode (possibly multiple bytes)
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# Value is a list:
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# # bytes
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# mnemonic
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# addressing mode
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# flags (e.g. pcr)
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opcodeTable = {
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0x00 : [ 1, "nop", "" ],
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0x01 : [ 2, "ajmp", "addr11" ],
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0x02 : [ 3, "ljmp", "addr16" ],
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0x03 : [ 1, "rr", "a" ],
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0x04 : [ 1, "inc", "a" ],
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0x05 : [ 2, "inc", "direct" ],
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0x06 : [ 1, "inc", "@r0" ],
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0x07 : [ 1, "inc", "@r1" ],
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0x08 : [ 1, "inc", "r0" ],
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0x09 : [ 1, "inc", "r1" ],
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0x0a : [ 1, "inc", "r2" ],
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0x0b : [ 1, "inc", "r3" ],
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0x0c : [ 1, "inc", "r4" ],
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0x0d : [ 1, "inc", "r5" ],
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0x0e : [ 1, "inc", "r6" ],
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0x0f : [ 1, "inc", "r7" ],
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0x10 : [ 3, "jbc", "bit,offset" ],
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0x11 : [ 2, "acall", "addr11" ],
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0x12 : [ 3, "lcall", "addr16" ],
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0x13 : [ 1, "rrc", "a" ],
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0x14 : [ 1, "dec", "a" ],
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0x15 : [ 2, "dec", "direct" ],
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0x16 : [ 1, "dec", "r0" ],
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0x17 : [ 1, "dec", "@r1" ],
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0x18 : [ 1, "dec", "r0" ],
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0x19 : [ 1, "dec", "r1" ],
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0x1a : [ 1, "dec", "r2" ],
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0x1b : [ 1, "dec", "r3" ],
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0x1c : [ 1, "dec", "r4" ],
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0x1d : [ 1, "dec", "r5" ],
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0x1e : [ 1, "dec", "r6" ],
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0x1f : [ 1, "dec", "r7" ],
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0x20 : [ 3, "jb", "bit,offset" ],
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0x21 : [ 2, "ajmp", "addr11" ],
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0x22 : [ 1, "ret", "" ],
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0x23 : [ 1, "rl", "a" ],
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0x24 : [ 2, "add", "a,immed" ],
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0x25 : [ 2, "add", "a,direct" ],
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0x26 : [ 1, "add", "a,r0" ],
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0x27 : [ 1, "add", "a,@r1" ],
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0x28 : [ 1, "add", "a,r0" ],
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0x29 : [ 1, "add", "a,r1" ],
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0x2a : [ 1, "add", "a,r2" ],
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0x2b : [ 1, "add", "a,r3" ],
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0x2c : [ 1, "add", "a,r4" ],
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0x2d : [ 1, "add", "a,r5" ],
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0x2e : [ 1, "add", "a,r6" ],
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0x2f : [ 1, "add", "a,r7" ],
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0x30 : [ 3, "jnb", "bit,offset" ],
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0x31 : [ 2, "acall", "addr11" ],
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0x32 : [ 1, "reti", "" ],
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0x33 : [ 1, "rlc", "a" ],
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0x34 : [ 2, "addc", "a,immed" ],
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0x35 : [ 2, "addc", "a,direct" ],
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0x36 : [ 1, "addc", "a,@r0" ],
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0x37 : [ 1, "addc", "a,@r1" ],
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0x38 : [ 1, "addc", "a,r0" ],
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0x39 : [ 1, "addc", "a,r1" ],
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0x3a : [ 1, "addc", "a,r2" ],
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0x3b : [ 1, "addc", "a,r3" ],
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0x3c : [ 1, "addc", "a,r4" ],
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0x3d : [ 1, "addc", "a,r5" ],
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0x3e : [ 1, "addc", "a,r6" ],
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0x3f : [ 1, "addc", "a,r7" ],
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0x40 : [ 2, "jc offset
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0x41 : [ 2, "ajmp addr11
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0x42 : [ 2, "orl", "direct", a
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0x43 : [ 3, "orl", "direct", #immed
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0x44 : [ 2, "orl a, #immed
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0x45 : [ 2, "orl a,", "direct"
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0x46 : [ 1, "orl a, @r0
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0x47 : [ 1, "orl a, @r1
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0x48 : [ 1, "orl a, r0
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0x49 : [ 1, "orl a, r1
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0x4a : [ 1, "orl a, r2
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0x4b : [ 1, "orl a, r3
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0x4c : [ 1, "orl a, r4
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0x4d : [ 1, "orl a, r5
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0x4e : [ 1, "orl a, r6
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0x4f : [ 1, "orl a, r7
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0x50 : [ 2, "jnc offset
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0x51 : [ 2, "acall addr11
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0x52 : [ 2, "anl direct, a
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0x53 : [ 3, "anl direct, #immed
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0x54 : [ 2, "anl a, #immed
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0x55 : [ 2, "anl a,", "direct"
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0x56 : [ 1, "anl a, @r0
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0x57 : [ 1, "anl a, @r1
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0x58 : [ 1, "anl a, r0
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0x59 : [ 1, "anl a, r1
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0x5a : [ 1, "anl a, r2
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0x5b : [ 1, "anl a, r3
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0x5c : [ 1, "anl a, r4
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0x5d : [ 1, "anl a, r5
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0x5e : [ 1, "anl a, r6
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0x5f : [ 1, "anl a, r7
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0x60 : [ 2, "jz offset
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0x61 : [ 2, "ajmp addr11
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0x62 : [ 2, "xrl direct, a
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0x63 : [ 3, "xrl direct, #immed
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0x64 : [ 2, "xrl a, #immed
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0x65 : [ 2, "xrl a,", "direct"
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0x66 : [ 1, "xrl a, @r0
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0x67 : [ 1, "xrl a, @r1
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0x68 : [ 1, "xrl a, r0
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0x69 : [ 1, "xrl a, r1
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0x6a : [ 1, "xrl a, r2
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0x6b : [ 1, "xrl a, r3
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0x6c : [ 1, "xrl a, r4
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0x6d : [ 1, "xrl a, r5
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0x6e : [ 1, "xrl a, r6
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0x6f : [ 1, "xrl a, r7
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0x70 : [ 2, "jnz offset
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0x71 : [ 2, "acall addr11
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0x72 : [ 2, "orl c, bit
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0x73 : [ 1, "jmp @a+dptr
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0x74 : [ 2, "mov a, #immed
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0x75 : [ 3, "mov direct, #immed
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0x76 : [ 2, "mov @r0, #immed
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0x77 : [ 2, "mov @r1, #immed
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0x78 : [ 2, "mov r0, #immed
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0x79 : [ 2, "mov r1, #immed
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0x7a : [ 2, "mov r2, #immed
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0x7b : [ 2, "mov r3, #immed
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0x7c : [ 2, "mov r4, #immed
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0x7d : [ 2, "mov r5, #immed
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0x7e : [ 2, "mov r6, #immed
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0x7f : [ 2, "mov r7, #immed
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0x80 : [ 2, "sjmp offset
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0x81 : [ 2, "ajmp addr11
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0x82 : [ 2, "anl c, bit
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0x83 : [ 1, "movc a, @a+pc
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0x84 : [ 1, "div ab
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0x85 : [ 3, "mov direct, direct
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0x86 : [ 2, "mov direct, @r0
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0x87 : [ 2, "mov direct, @r1
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0x88 : [ 2, "mov direct, r0
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0x89 : [ 2, "mov direct, r1
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0x8a : [ 2, "mov direct, r2
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0x8b : [ 2, "mov direct, r3
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0x8c : [ 2, "mov direct, r4
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0x8d : [ 2, "mov direct, r5
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0x8e : [ 2, "mov direct, r6
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0x8f : [ 2, "mov direct, r7
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0x90 : [ 3, "mov dptr, #immed
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0x91 : [ 2, "acall addr11
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0x92 : [ 2, "mov bit, c
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0x93 : [ 1, "movc a, @a+dptr
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0x94 : [ 2, "subb a, #immed
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0x95 : [ 2, "subb a, direct
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0x96 : [ 1, "subb a, @r0
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0x97 : [ 1, "subb a, @r1
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0x98 : [ 1, "subb a, r0
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0x99 : [ 1, "subb a, r1
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0x9a : [ 1, "subb a, r2
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0x9b : [ 1, "subb a, r3
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0x9c : [ 1, "subb a, r4
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0x9d : [ 1, "subb a, r5
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0x9e : [ 1, "subb a, r6
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0x9f : [ 1, "subb a, r7
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0xa0 : [ 2, "orl c, /bit
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0xa1 : [ 2, "ajmp addr11
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0xa2 : [ 2, "mov c, bit
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0xa3 : [ 1, "inc dptr
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0xa4 : [ 1, "mul ab
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0xa5 reserved
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0xa6 : [ 2, "mov @r0, direct
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0xa7 : [ 2, "mov @r1, direct
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0xa8 : [ 2, "mov r0, direct
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0xa9 : [ 2, "mov r1, direct
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0xaa : [ 2, "mov r2, direct
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0xab : [ 2, "mov r3, direct
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0xac : [ 2, "mov r4, direct
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0xad : [ 2, "mov r5, direct
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0xae : [ 2, "mov r6, direct
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0xaf : [ 2, "mov r7, direct
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0xb0 : [ 2, "anl c, /bit
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0xb1 : [ 2, "acall addr11
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0xb2 : [ 2, "cpl bit
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0xb3 : [ 1, "cpl c
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0xb4 : [ 3, "cjne a, #immed, offset
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0xb5 : [ 3, "cjne a, direct, offset
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0xb6 : [ 3, "cjne @r0, #immed, offset
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0xb7 : [ 3, "cjne @r1, #immed, offset
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0xb8 : [ 3, "cjne r0, #immed, offset
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0xb9 : [ 3, "cjne r1, #immed, offset
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0xba : [ 3, "cjne r2, #immed, offset
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0xbb : [ 3, "cjne r3, #immed, offset
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0xbc : [ 3, "cjne r4, #immed, offset
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0xbd : [ 3, "cjne r5, #immed, offset
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0xbe : [ 3, "cjne r6, #immed, offset
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0xbf : [ 3, "cjne r7, #immed, offset
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0xc0 : [ 2, "push direct
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0xc1 : [ 2, "ajmp addr11
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0xc2 : [ 2, "clr bit
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0xc3 : [ 1, "clr c
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0xc4 : [ 1, "swap a
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0xc5 : [ 2, "xch a, direct
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0xc6 : [ 1, "xch a, @r0
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0xc7 : [ 1, "xch a, @r1
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0xc8 : [ 1, "xch a, r0
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0xc9 : [ 1, "xch a, r1
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0xca : [ 1, "xch a, r2
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0xcb : [ 1, "xch a, r3
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0xcc : [ 1, "xch a, r4
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0xcd : [ 1, "xch a, r5
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0xce : [ 1, "xch a, r6
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0xcf : [ 1, "xch a, r7
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0xd0 : [ 2, "pop", "direct"
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0xd1 : [ 2, "acall addr11
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0xd2 : [ 2, "setb bit
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0xd3 : [ 1, "setb c
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0xd4 : [ 1, "da a
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0xd5 : [ 3, "djnz direct, offset
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0xd6 : [ 1, "xchd a, @r0
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0xd7 : [ 1, "xchd a, @r1
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0xd8 : [ 2, "djnz r0, offset
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0xd9 : [ 2, "djnz r1, offset
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0xda : [ 2, "djnz r2, offset
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0xdb : [ 2, "djnz r3, offset
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0xdc : [ 2, "djnz r4, offset
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0xdd : [ 2, "djnz r5, offset
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0xde : [ 2, "djnz r6, offset
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0xdf : [ 2, "djnz r7, offset
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0xe0 : [ 1, "movx a, @dptr
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0xe1 : [ 2, "ajmp addr11
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0xe2 : [ 1, "movx a, @r0
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0xe3 : [ 1, "movx a, @r1
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0xe4 : [ 1, "clr a
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0xe5 : [ 2, "mov a, direct
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0xe6 : [ 1, "mov a, @r0
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0xe7 : [ 1, "mov a, @r1
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0xe8 : [ 1, "mov a, r0
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0xe9 : [ 1, "mov a, r1
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0xea : [ 1, "mov a, r2
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0xeb : [ 1, "mov a, r3
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0xec : [ 1, "mov a, r4
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0xed : [ 1, "mov a, r5
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0xee : [ 1, "mov a, r6
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0xef : [ 1, "mov a, r7
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0xf0 : [ 1, "movx @dptr, a
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0xf1 : [ 2, "acall addr11
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0xf2 : [ 1, "movx @r0, a
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0xf3 : [ 1, "movx @r1, a
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0xf4 : [ 1, "cpl a
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0xf5 : [ 2, "mov direct, a
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0xf6 : [ 1, "mov @r0, a
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0xf7 : [ 1, "mov @r1, a
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0xf8 : [ 1, "mov r0, a
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0xf9 : [ 1, "mov r1, a
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0xfa : [ 1, "mov r2, a
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0xfb : [ 1, "mov r3, a
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0xfc : [ 1, "mov r4, a
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0xfd : [ 1, "mov r5, a
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0xfe : [ 1, "mov r6, a
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0xff : [ 1, "mov r7, a
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}
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# End of processor specific code
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##########################################################################
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