mirror of
https://github.com/jefftranter/udis.git
synced 2024-10-31 22:05:24 +00:00
390 lines
12 KiB
Python
390 lines
12 KiB
Python
##########################################################################
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#
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# Processor specific code
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# CPU = "8080"
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# Description = "Intel 8080 8-bit microprocessor."
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# DataWidth = 8 # 8-bit data
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# AddressWidth = 16 # 16-bit addresses
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# Maximum length of an instruction (for formatting purposes)
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maxLength = 3
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# Leadin bytes for multibyte instructions
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leadInBytes = []
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# Addressing mode table
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# List of addressing modes and corresponding format strings for operands.
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addressModeTable = {
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"implied" : "",
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"rega" : "a",
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"regb" : "b",
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"regc" : "c",
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"regd" : "d",
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"rege" : "e",
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"regh" : "h",
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"regl" : "l",
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"regm" : "m",
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"regsp" : "sp",
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"regbb" : "b,b",
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"regbc" : "b,c",
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"regbd" : "b,d",
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"regbe" : "b,e",
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"regbh" : "b,h",
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"regbl" : "b,l",
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"regbm" : "b,m",
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"regba" : "b,a",
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"regcb" : "c,b",
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"regcc" : "c,c",
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"regcd" : "c,d",
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"regce" : "c,e",
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"regch" : "c,h",
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"regcl" : "c,l",
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"regcm" : "c,m",
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"regca" : "c,a",
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"regdb" : "d,b",
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"regdc" : "d,c",
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"regdd" : "d,d",
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"regde" : "d,e",
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"regdh" : "d,h",
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"regdl" : "d,l",
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"regdm" : "d,m",
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"regda" : "d,a",
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"regeb" : "e,b",
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"regec" : "e,c",
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"reged" : "e,d",
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"regee" : "e,e",
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"regeh" : "e,h",
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"regel" : "e,l",
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"regem" : "e,m",
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"regea" : "e,a",
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"reghb" : "h,b",
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"reghc" : "h,c",
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"reghd" : "h,d",
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"reghe" : "h,e",
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"reghh" : "h,h",
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"reghl" : "h,l",
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"reghm" : "h,m",
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"regha" : "h,a",
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"reglb" : "l,b",
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"reglc" : "l,c",
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"regld" : "l,d",
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"regle" : "l,e",
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"reglh" : "l,h",
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"regll" : "l,l",
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"reglm" : "l,m",
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"regla" : "l,a",
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"regmb" : "m,b",
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"regmc" : "m,c",
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"regmd" : "m,d",
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"regme" : "m,e",
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"regmh" : "m,h",
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"regml" : "m,l",
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"regma" : "m,a",
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"regab" : "a,b",
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"regac" : "a,c",
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"regad" : "a,d",
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"regae" : "a,e",
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"regah" : "a,h",
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"regal" : "a,l",
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"regam" : "a,m",
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"regaa" : "a,a",
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"regpsw" : "psw",
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"imm" : "${0:02X}",
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"imma" : "a,${0:02X}",
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"immb" : "b,${0:02X}",
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"immc" : "c,${0:02X}",
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"immd" : "d,${0:02X}",
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"imme" : "e,${0:02X}",
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"immh" : "h,${0:02X}",
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"imml" : "l,${0:02X}",
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"immm" : "m,${0:02X}",
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"immxb" : "b,${1:02X}{0:02X}",
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"immxd" : "d,${1:02X}{0:02X}",
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"immxh" : "h,${1:02X}{0:02X}",
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"immxsp" : "sp,${1:02X}{0:02X}",
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"direct" : "${1:02X}{0:02X}",
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"0" : "0",
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"1" : "1",
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"2" : "2",
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"3" : "3",
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"4" : "4",
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"5" : "5",
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"6" : "6",
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"7" : "7",
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}
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# Op Code Table
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# Key is numeric opcode (possibly multiple bytes)
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# Value is a list:
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# # bytes
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# mnemonic
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# addressing mode
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# flags (e.g. pcr)
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opcodeTable = {
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0x00 : [ 1, "nop", "implied" ],
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0x01 : [ 3, "lxi", "immxb" ],
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0x02 : [ 1, "stax", "regb" ],
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0x03 : [ 1, "inx", "regb" ],
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0x04 : [ 1, "inr", "regb" ],
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0x05 : [ 1, "dcr", "regb" ],
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0x06 : [ 2, "mvi", "immb" ],
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0x07 : [ 1, "rlc", "implied" ],
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0x09 : [ 1, "dad", "regb" ],
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0x0a : [ 1, "ldax", "regb" ],
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0x0b : [ 1, "dcx", "regb" ],
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0x0c : [ 1, "inr", "regc" ],
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0x0d : [ 1, "dcr", "regc" ],
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0x0e : [ 2, "mvi", "immc" ],
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0x0f : [ 1, "rrc", "implied" ],
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0x11 : [ 3, "lxi", "immxd" ],
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0x12 : [ 1, "stax", "regd" ],
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0x13 : [ 1, "inx", "regd" ],
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0x14 : [ 1, "inr", "regd" ],
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0x15 : [ 1, "dcr", "regd" ],
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0x16 : [ 2, "mvi", "immd" ],
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0x17 : [ 1, "ral", "implied" ],
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0x19 : [ 1, "dad", "implied" ],
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0x1a : [ 1, "ldax", "regd" ],
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0x1b : [ 1, "dcx", "regd" ],
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0x1c : [ 1, "inr", "rege" ],
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0x1d : [ 1, "dcr", "rege" ],
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0x1e : [ 2, "mvi", "imme" ],
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0x1f : [ 1, "rar", "implied" ],
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0x21 : [ 3, "lxi", "immxh" ],
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0x22 : [ 3, "shld", "direct" ],
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0x23 : [ 1, "inx", "regh" ],
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0x24 : [ 1, "inr", "regh" ],
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0x25 : [ 1, "dcr", "regh" ],
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0x26 : [ 2, "mvi", "immh" ],
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0x27 : [ 1, "daa", "implied" ],
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0x29 : [ 1, "dad", "regh" ],
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0x2a : [ 3, "lhld", "direct" ],
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0x2b : [ 1, "dcx", "regh" ],
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0x2c : [ 1, "inr", "regl" ],
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0x2d : [ 1, "dcr", "regl" ],
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0x2e : [ 2, "mvi", "imml" ],
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0x2f : [ 1, "cma", "implied" ],
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0x31 : [ 3, "lxi", "immxsp" ],
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0x32 : [ 3, "sta", "direct" ],
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0x33 : [ 1, "inx", "regsp" ],
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0x34 : [ 1, "inr", "regm" ],
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0x35 : [ 1, "dcr", "regm" ],
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0x36 : [ 2, "mvi", "immm" ],
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0x37 : [ 1, "stc", "implied" ],
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0x39 : [ 1, "dad", "regsp" ],
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0x3a : [ 3, "lda", "direct" ],
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0x3b : [ 1, "dcx", "regsp" ],
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0x3c : [ 1, "inr", "rega" ],
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0x3d : [ 1, "dcr", "rega" ],
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0x3e : [ 2, "mvi", "imma" ],
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0x3f : [ 1, "cmc", "implied" ],
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0x40 : [ 1, "mov", "regbb" ],
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0x41 : [ 1, "mov", "regbc" ],
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0x42 : [ 1, "mov", "regbd" ],
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0x43 : [ 1, "mov", "regbe" ],
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0x44 : [ 1, "mov", "regbh" ],
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0x45 : [ 1, "mov", "regbl" ],
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0x46 : [ 1, "mov", "regbm" ],
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0x47 : [ 1, "mov", "regba" ],
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0x48 : [ 1, "mov", "regcb" ],
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0x49 : [ 1, "mov", "regcc" ],
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0x4a : [ 1, "mov", "regcd" ],
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0x4b : [ 1, "mov", "regce" ],
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0x4c : [ 1, "mov", "regch" ],
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0x4d : [ 1, "mov", "regcl" ],
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0x4e : [ 1, "mov", "regcm" ],
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0x4f : [ 1, "mov", "regca" ],
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0x50 : [ 1, "mov", "regdb" ],
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0x51 : [ 1, "mov", "regdc" ],
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0x52 : [ 1, "mov", "regdd" ],
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0x53 : [ 1, "mov", "regde" ],
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0x54 : [ 1, "mov", "regdh" ],
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0x55 : [ 1, "mov", "regdl" ],
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0x56 : [ 1, "mov", "regdm" ],
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0x57 : [ 1, "mov", "regda" ],
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0x58 : [ 1, "mov", "regeb" ],
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0x59 : [ 1, "mov", "regec" ],
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0x5a : [ 1, "mov", "reged" ],
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0x5b : [ 1, "mov", "regee" ],
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0x5c : [ 1, "mov", "regeh" ],
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0x5d : [ 1, "mov", "regel" ],
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0x5e : [ 1, "mov", "regem" ],
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0x5f : [ 1, "mov", "regea" ],
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0x60 : [ 1, "mov", "reghb" ],
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0x61 : [ 1, "mov", "reghc" ],
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0x62 : [ 1, "mov", "reghd" ],
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0x63 : [ 1, "mov", "reghe" ],
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0x64 : [ 1, "mov", "reghh" ],
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0x65 : [ 1, "mov", "reghl" ],
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0x66 : [ 1, "mov", "reghm" ],
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0x67 : [ 1, "mov", "regha" ],
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0x68 : [ 1, "mov", "reglb" ],
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0x69 : [ 1, "mov", "reglc" ],
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0x6a : [ 1, "mov", "regld" ],
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0x6b : [ 1, "mov", "regle" ],
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0x6c : [ 1, "mov", "reglh" ],
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0x6d : [ 1, "mov", "regll" ],
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0x6e : [ 1, "mov", "reglm" ],
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0x6f : [ 1, "mov", "regla" ],
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0x70 : [ 1, "mov", "regmb" ],
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0x71 : [ 1, "mov", "regmc" ],
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0x72 : [ 1, "mov", "regmd" ],
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0x73 : [ 1, "mov", "regme" ],
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0x74 : [ 1, "mov", "regmh" ],
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0x75 : [ 1, "mov", "regml" ],
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0x76 : [ 1, "hlt", "implied" ],
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0x77 : [ 1, "mov", "regma" ],
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0x78 : [ 1, "mov", "regab" ],
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0x79 : [ 1, "mov", "regac" ],
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0x7a : [ 1, "mov", "regad" ],
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0x7b : [ 1, "mov", "regae" ],
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0x7c : [ 1, "mov", "regah" ],
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0x7d : [ 1, "mov", "regal" ],
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0x7e : [ 1, "mov", "regam" ],
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0x7f : [ 1, "mov", "regaa" ],
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0x80 : [ 1, "add", "regb" ],
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0x81 : [ 1, "add", "regc" ],
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0x82 : [ 1, "add", "regd" ],
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0x83 : [ 1, "add", "rege" ],
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0x84 : [ 1, "add", "regh" ],
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0x85 : [ 1, "add", "regl" ],
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0x86 : [ 1, "add", "regm" ],
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0x87 : [ 1, "add", "rega" ],
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0x88 : [ 1, "adc", "regb" ],
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0x89 : [ 1, "adc", "regc" ],
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0x8a : [ 1, "adc", "regd" ],
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0x8b : [ 1, "adc", "rege" ],
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0x8c : [ 1, "adc", "regh" ],
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0x8d : [ 1, "adc", "regl" ],
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0x8e : [ 1, "adc", "regm" ],
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0x8f : [ 1, "adc", "rega" ],
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0x90 : [ 1, "sub", "regb" ],
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0x91 : [ 1, "sub", "regc" ],
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0x92 : [ 1, "sub", "regd" ],
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0x93 : [ 1, "sub", "rege" ],
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0x94 : [ 1, "sub", "regh" ],
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0x95 : [ 1, "sub", "regl" ],
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0x96 : [ 1, "sub", "regm" ],
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0x97 : [ 1, "sub", "rega" ],
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0x98 : [ 1, "sbb", "regb" ],
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0x99 : [ 1, "sbb", "regc" ],
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0x9a : [ 1, "sbb", "regd" ],
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0x9b : [ 1, "sbb", "rege" ],
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0x9c : [ 1, "sbb", "regh" ],
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0x9d : [ 1, "sbb", "regl" ],
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0x9e : [ 1, "sbb", "regm" ],
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0x9f : [ 1, "sbb", "rega" ],
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0xa0 : [ 1, "ana", "regb" ],
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0xa1 : [ 1, "ana", "regc" ],
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0xa2 : [ 1, "ana", "regd" ],
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0xa3 : [ 1, "ana", "rege" ],
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0xa4 : [ 1, "ana", "regh" ],
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0xa5 : [ 1, "ana", "regl" ],
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0xa6 : [ 1, "ana", "regm" ],
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0xa7 : [ 1, "ana", "rega" ],
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0xa8 : [ 1, "xra", "regb" ],
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0xa9 : [ 1, "xra", "regc" ],
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0xaa : [ 1, "xra", "regd" ],
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0xab : [ 1, "xra", "rege" ],
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0xac : [ 1, "xra", "regh" ],
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0xad : [ 1, "xra", "regl" ],
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0xae : [ 1, "xra", "regm" ],
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0xaf : [ 1, "xra", "rega" ],
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0xb0 : [ 1, "ora", "regb" ],
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0xb1 : [ 1, "ora", "regc" ],
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0xb2 : [ 1, "ora", "regd" ],
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0xb3 : [ 1, "ora", "rege" ],
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0xb4 : [ 1, "ora", "regh" ],
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0xb5 : [ 1, "ora", "regl" ],
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0xb6 : [ 1, "ora", "regm" ],
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0xb7 : [ 1, "ora", "rega" ],
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0xb8 : [ 1, "cmp", "regb" ],
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0xb9 : [ 1, "cmp", "regc" ],
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0xba : [ 1, "cmp", "regd" ],
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0xbb : [ 1, "cmp", "rege" ],
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0xbc : [ 1, "cmp", "regh" ],
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0xbd : [ 1, "cmp", "regl" ],
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0xbe : [ 1, "cmp", "regm" ],
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0xbf : [ 1, "cmp", "rega" ],
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0xc0 : [ 1, "rnz", "implied" ],
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0xc1 : [ 1, "pop", "regb" ],
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0xc2 : [ 3, "jnz", "direct" ],
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0xc3 : [ 3, "jmp", "direct" ],
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0xc4 : [ 3, "cnz", "direct" ],
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0xc5 : [ 1, "push", "regb" ],
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0xc6 : [ 2, "adi", "imm" ],
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0xc7 : [ 1, "rst", "0" ],
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0xc8 : [ 1, "rz", "implied" ],
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0xc9 : [ 1, "ret", "implied" ],
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0xca : [ 3, "jz", "direct" ],
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0xcc : [ 3, "cz", "direct" ],
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0xcd : [ 3, "call", "direct" ],
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0xce : [ 2, "aci", "imm" ],
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0xcf : [ 1, "rst", "1" ],
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0xd0 : [ 1, "rnc", "implied" ],
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0xd1 : [ 1, "pop", "regd" ],
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0xd2 : [ 3, "jnc", "direct" ],
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0xd3 : [ 2, "out", "imm" ],
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0xd4 : [ 3, "cnc", "direct" ],
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0xd5 : [ 1, "push", "regd" ],
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0xd6 : [ 2, "sui", "imm" ],
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0xd7 : [ 1, "rst", "2" ],
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0xd8 : [ 1, "rc", "implied" ],
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0xda : [ 3, "jc", "direct" ],
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0xdb : [ 2, "in", "imm" ],
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0xdc : [ 3, "cc", "direct" ],
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0xde : [ 2, "sbi", "imm" ],
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0xdf : [ 1, "rst", "3" ],
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0xe0 : [ 1, "rpo", "implied" ],
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0xe1 : [ 1, "pop", "regh" ],
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0xe2 : [ 3, "jpo", "direct" ],
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0xe3 : [ 1, "xthl", "implied" ],
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0xe4 : [ 3, "cpo", "direct" ],
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0xe5 : [ 1, "push", "regh" ],
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0xe6 : [ 2, "ani", "imm" ],
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0xe7 : [ 1, "rst", "4" ],
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0xe8 : [ 1, "rpe", "implied" ],
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0xe9 : [ 1, "pchl", "implied" ],
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0xea : [ 3, "jpe", "direct" ],
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0xeb : [ 1, "xchg", "implied" ],
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0xec : [ 3, "cpe", "direct" ],
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0xee : [ 2, "xri", "imm" ],
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0xef : [ 1, "rst", "5" ],
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0xf0 : [ 1, "rp", "implied" ],
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0xf1 : [ 1, "pop", "regpsw" ],
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0xf2 : [ 3, "jp", "direct" ],
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0xf3 : [ 1, "di", "implied" ],
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0xf4 : [ 3, "cp", "direct" ],
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0xf5 : [ 1, "push", "regpsw" ],
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0xf6 : [ 2, "ori", "imm" ],
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0xf7 : [ 1, "rst", "6" ],
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0xf8 : [ 1, "rm", "implied" ],
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0xf9 : [ 1, "sphl", "implied" ],
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0xfa : [ 3, "jm", "direct" ],
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0xfb : [ 1, "ei", "implied" ],
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0xfc : [ 3, "cm", "direct" ],
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0xfe : [ 2, "cpi", "imm" ],
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0xff : [ 1, "rst", "7" ],
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}
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# End of processor specific code
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##########################################################################
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