mirror of
https://github.com/jefftranter/udis.git
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277 lines
10 KiB
Python
277 lines
10 KiB
Python
##########################################################################
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#
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# Processor specific code
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# CPU = "65C02"
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# Description = "Western Design Center (and others) 65C02 8-bit microprocessor."
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# DataWidth = 8 # 8-bit data
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# AddressWidth = 16 # 16-bit addresses
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# Maximum length of an instruction (for formatting purposes)
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maxLength = 3
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# Leadin bytes for multibyte instructions
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leadInBytes = []
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# Addressing mode table
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# List of addressing modes and corresponding format strings for operands.
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addressModeTable = {
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"implicit" : "",
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"absolute" : "${1:02X}{0:02X}",
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"absolutex" : "${1:02X}{0:02X},x",
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"absolutey" : "${1:02X}{0:02X},y",
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"accumulator" : "a",
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"immediate" : "#${0:02X}",
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"indirectx" : "(${0:02X},x)",
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"indirecty" : "(${0:02X}),y",
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"indirect" : "(${1:02X}{0:02X})",
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"relative" : "${0:04X}",
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"zeropage" : "${0:02X}",
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"zeropagex" : "${0:02X},x",
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"zeropagey" : "${0:02X},y",
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"indirectzeropage" : "(${0:02X})",
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"absoluteindexedindirect" : "(${1:02X}{0:02X},x)",
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"zeropagerelative" : "${0:02X},${1:04X}",
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}
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# Op Code Table
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# Key is numeric opcode (possibly multiple bytes)
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# Value is a list:
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# # bytes
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# mnemonic
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# addressing mode
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# flags (e.g. pcr)
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opcodeTable = {
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0x00 : [ 1, "brk", "implicit" ],
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0x01 : [ 2, "ora", "indirectx" ],
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0x04 : [ 2, "tsb", "zeropage", ],
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0x05 : [ 2, "ora", "zeropage" ],
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0x06 : [ 2, "asl", "zeropage" ],
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0x07 : [ 2, "rmb0", "zeropage" ],
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0x08 : [ 1, "php", "implicit" ],
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0x09 : [ 2, "ora", "immediate" ],
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0x0a : [ 1, "asl", "accumulator" ],
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0x0c : [ 3, "tsb", "absolute" ],
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0x0d : [ 3, "ora", "absolute" ],
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0x0e : [ 3, "asl", "absolute" ],
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0x0f : [ 3, "bbr0", "zeropagerelative", pcr ],
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0x10 : [ 2, "bpl", "relative", pcr ],
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0x11 : [ 2, "ora", "indirecty" ],
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0x12 : [ 2, "ora", "indirectzeropage" ],
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0x14 : [ 2, "trb", "zeropage" ],
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0x15 : [ 2, "ora", "zeropagex" ],
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0x16 : [ 2, "asl", "zeropagex" ],
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0x17 : [ 2, "rmb1", "zeropage" ],
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0x18 : [ 1, "clc", "implicit" ],
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0x19 : [ 3, "ora", "absolutey" ],
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0x1a : [ 1, "inc", "accumulator" ],
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0x1c : [ 3, "trb", "absolute" ],
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0x1d : [ 3, "ora", "absolutex" ],
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0x1e : [ 3, "asl", "absolutex" ],
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0x1f : [ 3, "bbr1", "zeropagerelative", pcr ],
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0x20 : [ 3, "jsr", "absolute" ],
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0x21 : [ 2, "and", "indirectx" ],
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0x24 : [ 2, "bit", "zeropage" ],
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0x25 : [ 2, "and", "zeropage" ],
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0x26 : [ 2, "rol", "zeropage" ],
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0x27 : [ 2, "rmb2", "zeropage" ],
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0x28 : [ 1, "plp", "implicit" ],
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0x29 : [ 2, "and", "immediate" ],
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0x2a : [ 1, "rol", "accumulator" ],
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0x2c : [ 3, "bit", "absolute" ],
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0x2d : [ 3, "and", "absolute" ],
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0x2e : [ 3, "rol", "absolute" ],
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0x2f : [ 3, "bbr2", "zeropagerelative", pcr ],
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0x30 : [ 2, "bmi", "relative", pcr ],
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0x31 : [ 2, "and", "indirecty" ],
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0x32 : [ 2, "and", "indirectzeropage" ],
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0x34 : [ 2, "bit", "zeropagex" ],
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0x35 : [ 2, "and", "zeropagex" ],
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0x36 : [ 2, "rol", "zeropagex" ],
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0x37 : [ 2, "rmb3", "zeropage" ],
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0x38 : [ 1, "sec", "implicit" ],
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0x39 : [ 3, "and", "absolutey" ],
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0x3a : [ 1, "dec", "accumulator" ],
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0x3c : [ 3, "bit", "absolutex" ],
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0x3d : [ 3, "and", "absolutex" ],
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0x3e : [ 3, "rol", "absolutex" ],
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0x3f : [ 3, "bbr3", "zeropagerelative", pcr ],
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0x40 : [ 1, "rti", "implicit" ],
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0x41 : [ 2, "eor", "indirectx" ],
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0x45 : [ 2, "eor", "zeropage" ],
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0x46 : [ 2, "lsr", "zeropage" ],
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0x47 : [ 2, "rmb4", "zeropage" ],
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0x48 : [ 1, "pha", "implicit" ],
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0x49 : [ 2, "eor", "immediate" ],
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0x4a : [ 1, "lsr", "accumulator" ],
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0x4c : [ 3, "jmp", "absolute" ],
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0x4d : [ 3, "eor", "absolute" ],
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0x4e : [ 3, "lsr", "absolute" ],
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0x4f : [ 3, "bbr4", "zeropagerelative", pcr ],
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0x50 : [ 2, "bvc", "relative", pcr ],
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0x51 : [ 2, "eor", "indirecty" ],
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0x52 : [ 2, "eor", "indirectzeropage" ],
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0x55 : [ 2, "eor", "zeropagex" ],
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0x56 : [ 2, "lsr", "zeropagex" ],
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0x57 : [ 2, "rmb5", "zeropage" ],
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0x58 : [ 1, "cli", "implicit" ],
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0x59 : [ 3, "eor", "absolutey" ],
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0x5a : [ 1, "phy", "implicit" ],
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0x5d : [ 3, "eor", "absolutex" ],
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0x5e : [ 3, "lsr", "absolutex" ],
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0x5f : [ 3, "bbr5", "zeropagerelative", pcr ],
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0x60 : [ 1, "rts", "implicit" ],
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0x61 : [ 2, "adc", "indirectx" ],
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0x64 : [ 2, "stz", "zeropage" ],
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0x65 : [ 2, "adc", "zeropage" ],
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0x66 : [ 2, "ror", "zeropage" ],
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0x67 : [ 2, "rmb6", "zeropage" ],
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0x68 : [ 1, "pla", "implicit" ],
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0x69 : [ 2, "adc", "immediate" ],
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0x6a : [ 1, "ror", "accumulator" ],
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0x6c : [ 3, "jmp", "indirect" ],
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0x6d : [ 3, "adc", "absolute" ],
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0x6e : [ 3, "ror", "absolute" ],
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0x6f : [ 3, "bbr6", "zeropagerelative", pcr ],
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0x70 : [ 2, "bvs", "relative", pcr ],
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0x71 : [ 2, "adc", "indirecty" ],
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0x72 : [ 2, "adc", "indirectzeropage" ],
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0x74 : [ 2, "stz", "zeropagex" ],
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0x75 : [ 2, "adc", "zeropagex" ],
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0x76 : [ 2, "ror", "zeropagex" ],
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0x77 : [ 2, "rmb7", "zeropage" ],
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0x78 : [ 1, "sei", "implicit" ],
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0x79 : [ 3, "adc", "absolutey" ],
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0x7a : [ 1, "ply", "implicit" ],
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0x7c : [ 3, "jmp", "absoluteindexedindirect" ],
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0x7d : [ 3, "adc", "absolutex" ],
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0x7e : [ 3, "ror", "absolutex" ],
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0x7f : [ 3, "bbr7", "zeropagerelative", pcr ],
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0x80 : [ 2, "bra", "relative", pcr ],
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0x81 : [ 2, "sta", "indirectx" ],
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0x84 : [ 2, "sty", "zeropage" ],
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0x85 : [ 2, "sta", "zeropage" ],
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0x86 : [ 2, "stx", "zeropage" ],
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0x87 : [ 2, "smb0", "zeropage" ],
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0x88 : [ 1, "dey", "implicit" ],
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0x89 : [ 2, "bit", "immediate" ],
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0x8a : [ 1, "txa", "implicit" ],
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0x8c : [ 3, "sty", "absolute" ],
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0x8d : [ 3, "sta", "absolute" ],
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0x8e : [ 3, "stx", "absolute" ],
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0x8f : [ 3, "bbs0", "zeropagerelative", pcr ],
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0x90 : [ 2, "bcc", "relative", pcr ],
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0x91 : [ 2, "sta", "indirecty" ],
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0x92 : [ 2, "sta", "indirectzeropage" ],
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0x94 : [ 2, "sty", "zeropagex" ],
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0x95 : [ 2, "sta", "zeropagex" ],
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0x96 : [ 2, "stx", "zeropagey" ],
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0x97 : [ 2, "smb1", "zeropage" ],
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0x98 : [ 1, "tya", "implicit" ],
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0x99 : [ 3, "sta", "absolutey" ],
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0x9a : [ 1, "txs", "implicit" ],
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0x9c : [ 3, "stz", "absolute" ],
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0x9d : [ 3, "sta", "absolutex" ],
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0x9e : [ 3, "stz", "absolutex" ],
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0x9f : [ 3, "bbs1", "zeropagerelative", pcr ],
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0xa0 : [ 2, "ldy", "immediate" ],
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0xa1 : [ 2, "lda", "indirectx" ],
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0xa2 : [ 2, "ldx", "immediate" ],
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0xa4 : [ 2, "ldy", "zeropage" ],
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0xa5 : [ 2, "lda", "zeropage" ],
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0xa6 : [ 2, "ldx", "zeropage" ],
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0xa7 : [ 2, "smb2", "zeropage" ],
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0xa8 : [ 1, "tay", "implicit" ],
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0xa9 : [ 2, "lda", "immediate" ],
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0xaa : [ 1, "tax", "implicit" ],
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0xac : [ 3, "ldy", "absolute" ],
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0xad : [ 3, "lda", "absolute" ],
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0xae : [ 3, "ldx", "absolute" ],
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0xaf : [ 3, "bbs2", "zeropagerelative", pcr ],
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0xb0 : [ 2, "bcs", "relative", pcr ],
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0xb1 : [ 2, "lda", "indirecty" ],
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0xb2 : [ 2, "lda", "indirectzeropage" ],
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0xb4 : [ 2, "ldy", "zeropagex" ],
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0xb5 : [ 2, "lda", "zeropagex" ],
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0xb6 : [ 2, "ldx", "zeropagey" ],
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0xb7 : [ 2, "smb3", "zeropage" ],
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0xb8 : [ 1, "clv", "implicit" ],
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0xb9 : [ 3, "lda", "absolutey" ],
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0xba : [ 1, "tsx", "implicit" ],
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0xbc : [ 3, "ldy", "absolutex" ],
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0xbd : [ 3, "lda", "absolutex" ],
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0xbe : [ 3, "ldx", "absolutey" ],
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0xbf : [ 3, "bbs3", "zeropagerelative", pcr ],
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0xc0 : [ 2, "cpy", "immediate" ],
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0xc1 : [ 2, "cmp", "indirectx" ],
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0xc4 : [ 2, "cpy", "zeropage" ],
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0xc5 : [ 2, "cmp", "zeropage" ],
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0xc6 : [ 2, "dec", "zeropage" ],
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0xc7 : [ 2, "smb4", "zeropage" ],
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0xc8 : [ 1, "iny", "implicit" ],
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0xc9 : [ 2, "cmp", "immediate" ],
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0xca : [ 1, "dex", "implicit" ],
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0xcb : [ 1, "wai", "implicit" ], # WDC 65C02 only (not Rockwell)
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0xcc : [ 3, "cpy", "absolute" ],
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0xcd : [ 3, "cmp", "absolute" ],
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0xce : [ 3, "dec", "absolute" ],
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0xcf : [ 3, "bbs4", "zeropagerelative", pcr ],
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0xd0 : [ 2, "bne", "relative", pcr ],
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0xd1 : [ 2, "cmp", "indirecty" ],
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0xd2 : [ 2, "cmp", "indirectzeropage" ],
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0xd5 : [ 2, "cmp", "zeropagex" ],
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0xd6 : [ 2, "dec", "zeropagex" ],
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0xd7 : [ 2, "smb5", "zeropage" ],
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0xd8 : [ 1, "cld", "implicit" ],
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0xd9 : [ 3, "cmp", "absolutey" ],
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0xda : [ 1, "phx", "implicit" ],
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0xdb : [ 1, "stp", "implicit" ], # WDC 65C02 only (not Rockwell)
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0xdd : [ 3, "cmp", "absolutex" ],
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0xde : [ 3, "dec", "absolutex" ],
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0xdf : [ 3, "bbs5", "zeropagerelative", pcr ],
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0xe0 : [ 2, "cpx", "immediate" ],
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0xe1 : [ 2, "sbc", "indirectx" ],
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0xe4 : [ 2, "cpx", "zeropage" ],
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0xe5 : [ 2, "sbc", "zeropage" ],
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0xe6 : [ 2, "inc", "zeropage" ],
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0xe7 : [ 2, "smb6", "zeropage" ],
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0xe8 : [ 1, "inx", "implicit" ],
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0xe9 : [ 2, "sbc", "immediate" ],
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0xea : [ 1, "nop", "implicit" ],
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0xec : [ 3, "cpx", "absolute" ],
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0xed : [ 3, "sbc", "absolute" ],
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0xee : [ 3, "inc", "absolute" ],
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0xef : [ 3, "bbs6", "zeropagerelative", pcr ],
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0xf0 : [ 2, "beq", "relative", pcr ],
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0xf1 : [ 2, "sbc", "indirecty" ],
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0xf2 : [ 2, "sbc", "indirectzeropage" ],
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0xf5 : [ 2, "sbc", "zeropagex" ],
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0xf6 : [ 2, "inc", "zeropagex" ],
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0xf7 : [ 2, "smb7", "zeropage" ],
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0xf8 : [ 1, "sed", "implicit" ],
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0xf9 : [ 3, "sbc", "absolutey" ],
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0xfa : [ 1, "plx", "implicit" ],
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0xfd : [ 3, "sbc", "absolutex" ],
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0xfe : [ 3, "inc", "absolutex" ],
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0xff : [ 3, "bbs7", "zeropagerelative", pcr ],
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}
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# End of processor specific code
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##########################################################################
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