(WIP) compiles now
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43
Cpu6502.cpp
43
Cpu6502.cpp
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@ -8,12 +8,13 @@
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#include "Cpu6502.h"
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#include "TransNetwork.h"
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#include "trans.h"
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#include "AddressBus.h"
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#include "addressbus.h"
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#include "Trace.h"
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#include "cpu.h"
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#include <iostream>
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#include "StateCalculator.h"
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@ -51,7 +52,7 @@ void Cpu6502::powerOn() {
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* temporary variable (see "step" method), we
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* need to initialize it here, to "phase one".
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*/
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segs[n->CLK0].on = true;
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n->CLK0->on = true;
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@ -59,11 +60,23 @@ void Cpu6502::powerOn() {
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initPins();
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std::cout << "initial full calculation..." << std::endl;
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recalcAll();
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recalc(segs.all());
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dumpRegs();
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dumpSegs();
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}
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void Cpu6502::setSeg(Segment* s, bool on) {
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s->set(on);
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}
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void Cpu6502::recalc(Segment* s) {
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StateCalculator::recalc(s,n->VSS,n->VCC);
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}
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void Cpu6502::recalc(std::set<Segment*> s) {
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StateCalculator::recalc(s,n->VSS,n->VCC);
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}
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void Cpu6502::initPins() {
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// set voltage supply and ground.
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setSeg(n->VCC, true);
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@ -115,7 +128,7 @@ void Cpu6502::step() {
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*
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* The real 6502, of course, does not do this.
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*/
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const bool nextPhase = !segs[n->CLK0].on;
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const bool nextPhase = !n->CLK0->on;
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clock(nextPhase);
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rw();
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@ -131,11 +144,11 @@ void Cpu6502::clock(bool phase) {
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void Cpu6502::rw() {
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// database read/write happens during Clock Phase 2 (only)
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if (segs[n->CLK2OUT].on) {
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if (n->CLK2OUT->on) {
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readBus();
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std::set<int> s;
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addDataToRecalc(s);
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std::set<Segment*> s;
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segs.addDataToRecalc(s);
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recalc(s);
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writeBus();
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@ -188,17 +201,3 @@ void Cpu6502::write(unsigned short addr, unsigned char data) {
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std::cout << std::endl;
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#endif
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}
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void Cpu6502::recalcAll() {
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std::set<int> riSeg;
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for (int iSeg = 0; iSeg < segs.size(); ++iSeg) {
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addRecalc(iSeg,riSeg);
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}
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recalc(riSeg);
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}
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12
Cpu6502.h
12
Cpu6502.h
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@ -8,6 +8,9 @@
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#ifndef CPU6502_H
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#define CPU6502_H
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#include "TransNetwork.h"
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class TransNetwork;
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class AddressBus;
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class Trace;
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@ -15,7 +18,7 @@ class Trace;
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class Cpu6502 {
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public:
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Cpu6502(TransNetwork& transNetwork, AddressBus& addressBus, Trace& trace) : transNetwork(transNetwork), addressBus(addressBus), trace(trace) {
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Cpu6502(TransNetwork& transNetwork, AddressBus& addressBus, Trace& trace) : transNetwork(transNetwork), addressBus(addressBus), trace(trace), segs(transNetwork.segs), n(segs.c) {
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}
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virtual ~Cpu6502() {
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@ -37,10 +40,17 @@ private:
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unsigned char read(unsigned short addr);
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void write(unsigned short addr, unsigned char data);
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static void setSeg(Segment* s, bool on);
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void recalc(Segment* s);
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void recalc(std::set<Segment*> s);
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TransNetwork& transNetwork;
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AddressBus& addressBus;
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Trace& trace;
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SegmentCache& segs;
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SegmentCache::Common* n;
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};
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#endif /* CPU6502_H */
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@ -26,6 +26,14 @@ public:
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Segment* getOrAdd(const std::string& id);
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Segment* get(const std::string& id) const;
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std::set<Segment*> all() {
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std::set<Segment*> s;
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for (std::map<const std::string, std::shared_ptr<Segment > >::const_iterator i = cache.begin(); i != cache.end(); ++i) {
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s.insert(i->second.get());
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}
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return s;
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}
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class Common {
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public:
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Segment* VSS;
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@ -14,6 +14,7 @@
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#include "Cpu6502.h"
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#include "TransNetwork.h"
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#include "Trace.h"
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//memory[0xFF] = 0x68; // PLA
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@ -45,8 +46,9 @@ int main(int argc, char *argv[]) {
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exit(EXIT_FAILURE);
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}
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TransNetwork tn(if_trans);
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Cpu6502 cpu(tn);
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AddressBus mem;
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Trace trace(tn.segs);
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Cpu6502 cpu(tn,mem,trace);
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}
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int xxxmain(int argc, char *argv[]) {
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