mirror of
https://github.com/cmosher01/v6502cpp.git
synced 2026-03-11 20:41:45 +00:00
incorporate new transistor format file into code
This commit is contained in:
Christopher Mosher
225
cpu.cpp
225
cpu.cpp
@@ -3,6 +3,7 @@
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#include <algorithm>
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#include <utility>
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#include <iterator>
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#include <string>
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#include <vector>
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#include <set>
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#include <map>
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@@ -51,78 +52,190 @@ static void pHexw(const unsigned short x) {
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/* power */
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#define VCC sg->isegVCC
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#define VSS sg->isegVSS
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/* inputs */
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#define CLK0 sg->isegCLK0
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#define IRQ sg->isegIRQ
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#define RES sg->isegRES
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#define NMI sg->isegNMI
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#define RDY sg->isegRDY
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#define SO sg->isegSO
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/* data bus (I/O) */
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#define DB0 sg->isegDB0
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#define DB1 sg->isegDB1
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#define DB3 sg->isegDB3
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#define DB2 sg->isegDB2
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#define DB5 sg->isegDB5
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#define DB4 sg->isegDB4
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#define DB7 sg->isegDB7
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#define DB6 sg->isegDB6
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/* address bus (output) */
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#define AB0 sg->isegAB0
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#define AB1 sg->isegAB1
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#define AB2 sg->isegAB2
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#define AB3 sg->isegAB3
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#define AB4 sg->isegAB4
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#define AB5 sg->isegAB5
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#define AB6 sg->isegAB6
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#define AB7 sg->isegAB7
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#define AB8 sg->isegAB8
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#define AB9 sg->isegAB9
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#define AB12 sg->isegAB12
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#define AB13 sg->isegAB13
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#define AB10 sg->isegAB10
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#define AB11 sg->isegAB11
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#define AB14 sg->isegAB14
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#define AB15 sg->isegAB15
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/* outputs */
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#define RW sg->isegRW
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#define SYNC sg->isegSYNC
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#define CLK1OUT sg->isegCLK1OUT
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#define CLK2OUT sg->isegCLK2OUT
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/* internal registers */
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#define A0 sg->isegA0
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#define A1 sg->isegA1
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#define A2 sg->isegA2
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#define A3 sg->isegA3
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#define A4 sg->isegA4
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#define A5 sg->isegA5
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#define A6 sg->isegA6
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#define A7 sg->isegA7
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#define X0 sg->isegX0
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#define X1 sg->isegX1
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#define X2 sg->isegX2
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#define X3 sg->isegX3
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#define X4 sg->isegX4
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#define X5 sg->isegX5
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#define X6 sg->isegX6
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#define X7 sg->isegX7
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#define Y0 sg->isegY0
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#define Y1 sg->isegY1
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#define Y2 sg->isegY2
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#define Y3 sg->isegY3
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#define Y4 sg->isegY4
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#define Y5 sg->isegY5
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#define Y6 sg->isegY6
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#define Y7 sg->isegY7
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#define PCL0 sg->isegPCL0
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#define PCL1 sg->isegPCL1
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#define PCL2 sg->isegPCL2
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#define PCL3 sg->isegPCL3
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#define PCL4 sg->isegPCL4
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#define PCL5 sg->isegPCL5
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#define PCL6 sg->isegPCL6
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#define PCL7 sg->isegPCL7
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#define PCH0 sg->isegPCH0
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#define PCH1 sg->isegPCH1
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#define PCH2 sg->isegPCH2
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#define PCH3 sg->isegPCH3
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#define PCH4 sg->isegPCH4
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#define PCH5 sg->isegPCH5
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#define PCH6 sg->isegPCH6
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#define PCH7 sg->isegPCH7
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#define P0 sg->isegP0
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#define P1 sg->isegP1
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#define P2 sg->isegP2
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#define P3 sg->isegP3
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#define P4 sg->isegP4
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#define P6 sg->isegP6
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#define P7 sg->isegP7
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#define S0 sg->isegS0
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#define S1 sg->isegS1
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#define S2 sg->isegS2
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#define S3 sg->isegS3
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#define S4 sg->isegS4
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#define S5 sg->isegS5
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#define S6 sg->isegS6
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#define S7 sg->isegS7
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static nodes* sg;
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static std::map<int,std::string> map_i_seg;
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static int get_i_seg(const std::string& seg, std::map<std::string,int>& map_seg_i) {
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static int i_segin(0);
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int i_seg = -1;
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if (map_seg_i.find(seg) == map_seg_i.end()) {
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i_seg = i_segin++;
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map_seg_i[seg] = i_seg;
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map_i_seg[i_seg] = seg;
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} else {
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i_seg = map_seg_i[seg];
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}
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return i_seg;
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}
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CPU::CPU(AddressBus& addressBus) :
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addressBus(addressBus) {
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std::cout << "reading segsonly";
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std::ifstream if_segs("segsonly");
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if (!if_segs.is_open()) {
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std::cerr << "error opening file: segs" << std::endl;
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std::cout << "reading transistors";
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std::ifstream if_trans("transistors");
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if (!if_trans.is_open()) {
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std::cerr << "error opening file: transistors" << std::endl;
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exit(EXIT_FAILURE);
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}
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int i_seg(0);
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while (if_segs.good()) {
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int i_segin(-1);
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bool b_on(false);
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if_segs >> i_segin >> b_on;
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if (i_segin >= 0) {
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if (i_segin != i_seg++) {
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std::cerr << "error: mismatch in segsonly file near " << i_segin << std::endl;
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exit(EXIT_FAILURE);
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}
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std::cout << ".";
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seg s;
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s.pullup = b_on;
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s.pulldown = false;
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s.on = false;
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segs.push_back(s);
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}
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}
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std::cout << std::endl << "read " << segs.size() << " segs" << std::endl;
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std::cout << "reading trns";
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std::ifstream if_trns("trns");
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if (!if_trns.is_open()) {
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std::cerr << "error opening file: trns" << std::endl;
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exit(EXIT_FAILURE);
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}
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int i_trn(0);
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while (if_trns.good()) {
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std::string seg_c1, seg_gate, seg_c2;
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if_trans >> seg_c1 >> seg_gate >> seg_c2;
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while (if_trans.good()) {
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std::cout << ".";
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int i_trnin(-1);
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int i_gate, i_c1, i_c2;
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if_trns >> i_trnin >> i_gate >> i_c1 >> i_c2;
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if (i_trnin >= 0) {
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if (i_trnin != i_trn++) {
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std::cerr << "error: mismatch in trns file near " << i_trnin << std::endl;
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exit(EXIT_FAILURE);
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}
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trn t;
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t.gate = i_gate;
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t.c1 = i_c1;
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t.c2 = i_c2;
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t.on = false;
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trns.push_back(t);
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}
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}
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std::cout << std::endl << "read " << trns.size() << " trns" << std::endl;
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trn t;
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t.on = false;
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t.c1 = get_i_seg(seg_c1,map_seg_i);
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t.gate = get_i_seg(seg_gate,map_seg_i);
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t.c2 = get_i_seg(seg_c2,map_seg_i);
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trns.push_back(t);
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if_trans >> seg_c1 >> seg_gate >> seg_c2;
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}
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std::cout << std::endl << "read " << map_seg_i.size() << " segments, " << trns.size() << " transistors" << std::endl;
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for (int i_seg = 0; i_seg < map_seg_i.size(); ++i_seg)
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{
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const std::string id_seg = map_i_seg[i_seg];
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seg s;
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s.id = id_seg;
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s.pullup = id_seg[0] == '+';
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s.pulldown = false;
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s.on = false;
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segs.push_back(s);
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}
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const int isegVSS = map_seg_i["-vss"];
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const int isegVCC = map_seg_i["-vcc"];
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for (int i = 0; i != trns.size(); ++i) {
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trn& t = trns[i];
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if (t.c1 == VSS) {
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if (t.c1 == isegVSS) {
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t.c1 = t.c2;
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t.c2 = VSS;
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} else if (t.c1 == VCC) {
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t.c2 = isegVSS;
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} else if (t.c1 == isegVCC) {
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t.c1 = t.c2;
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t.c2 = VCC;
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t.c2 = isegVCC;
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}
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segs[t.gate].gates.push_back(i);
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segs[t.c1].c1c2s.push_back(i);
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segs[t.c2].c1c2s.push_back(i);
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}
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sg = new nodes(map_seg_i);
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}
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CPU::~CPU() {
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