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[dev]name some reset signals

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BigEd 2010-09-30 19:20:56 +00:00
parent f26a508c4e
commit 4849ad6ebc
1 changed files with 6 additions and 2 deletions
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@ -259,6 +259,10 @@ pd5: 829,
pd6: 1669, pd6: 1669,
pd7: 1690, pd7: 1690,
notRdy0: 248, // internal signal: global pipeline control notRdy0: 248, // internal signal: global pipeline control
Reset0: 67, // internal signal: retimed reset from pin
C1x5Reset: 926, // retimed and pipelined reset in progress
notRnWprepad: 187, // internal signal: to pad, yet to be inverted and retimed
RnWstretched: 353, // internal signal: control datapad output drivers
cp1: 710, // internal signal: clock phase 1 cp1: 710, // internal signal: clock phase 1
cclk: 943, // unbonded pad: internal non-overlappying phi2 cclk: 943, // unbonded pad: internal non-overlappying phi2
fetch: 879, // internal signal fetch: 879, // internal signal
@ -451,8 +455,8 @@ pipeUNK20: 294,
pipeUNK21: 1176, pipeUNK21: 1176,
pipeUNK22: 561, // becomes dpc22 pipeUNK22: 561, // becomes dpc22
pipeUNK23: 596, pipeUNK23: 596,
pipeUNK24: 449, pipephi2Reset0: 449,
pipeUNK25: 1036, pipephi2Reset0x: 1036, // a second copy of the same latch
pipeUNK26: 1321, pipeUNK26: 1321,
pipeUNK27: 73, pipeUNK27: 73,
pipeUNK28: 685, pipeUNK28: 685,