From 27d0eb8fb2a59f70aa74fcf4c8cc806dfef83bc9 Mon Sep 17 00:00:00 2001 From: mmfoerster Date: Tue, 19 Sep 2017 20:01:47 -0400 Subject: [PATCH 1/8] Created plain-text documentation for the 6502 clock time codes. Added function that creates the text expression of the time codes seen in the documentation to macros.js and expert-allinone.js. Added documentation file: 6502timecodes.txt Added function: allTCStates() --- 6502timecodes.txt | 125 +++++++++++++++++++++++++++++++++++++++++++++ expert-allinone.js | 53 +++++++++++++++++++ macros.js | 53 +++++++++++++++++++ 3 files changed, 231 insertions(+) create mode 100644 6502timecodes.txt diff --git a/6502timecodes.txt b/6502timecodes.txt new file mode 100644 index 0000000..61f3f17 --- /dev/null +++ b/6502timecodes.txt @@ -0,0 +1,125 @@ +6502 Time codes. + + There are two things that are critical for correct instruction execution in +the 6502 (indeed, for any CPU chip): the pattern of bits in the instruction +register AND the pattern of "time code" bits from the timing control block of +circuits. + Both sets of bits (IR and time code), in combination, control the output +bits of the PLA block of circuits. PLA outputs, in turn, affect the RCL block +of circuits, and their control outputs directly operate the connections among +the registers, busses, and ALU on the other end of the chip die to actually get +the instructions' work done. + The 6502's timing control has ten states (effectively) and six explicit +output bits. Only the explicit output bits affect the PLA. The output bits are +labelled T0, T+, T2, T3, T4, and T5. The bits are considered active when their +logic states are low. There are two states where two of these explicit output +bits are active at the same time. There are also two states where none of the +explicit output bits are active. All other states have only one output bit +active at a time. + The two states with two bits active together are T0 with T+, and T0 with T2. +The two states with all explicit bits inactive are referred to as T1 and T6. +Those two states can only be distinguished within the timing control block of +circuits by paying attention to a logic node that is responsible for clearing +(making inactive) the explicit output bits T2 through T5. The clearing node +at logic high (active) corresponds to the T1 state, and low corresponds to the +T6 state. For the visual6502, this is node 1357. + + The notation developed for trace/debug output, and the notation presented +hereafter in this document, lists the explicit output bits in numeric order +followed by square brackets around the non-explicit internal state of T1 or T6. +When one or more of the explicit bits is active, the square bracketed label will +be blank. + Wherever one of the explicit bits is inactive, a blank placeholder of ".." +is present for it. This also applies to the bracketed label. + +For example, the T0 state is presented as: + +T0 .. .. .. .. .. [..] + +...and the T1 state is presented as: + +.. .. .. .. .. .. [T1] + + The low-profile "blank" notation of ".." assists visual examination of +trace/debug output by keeping consistent placeholders for bits when they are +inactive, with minimized visual clutter. Aligning everything in fixed positions +contributes to rapid recognition of changes. + +Time codes seen around instruction execution + +All instructions, with a few exceptions, always end with T0 in their time code +for the last cycle. The presence of T0 indicates, "last cycle". + +The strictly 2-cycle instructions always end with the time code: + +T0 .. T2 .. .. .. [..] + +All other instructions end with the time code: + +T0 .. .. .. .. .. [..] + +The mentioned exceptions to last-cycle T0 time codes are the conditional branch +instructions. When they do not take the branch, their last cycle time code is: + +.. .. T2 .. .. .. [..] + +When they do take the branch, and the branch does not cross a memory page, their +last cycle time code is: + +.. .. .. T3 .. .. [..] + +When the branch instructions take the branch, and the branch crosses a memory +page, they end with a T0 last cycle just like all the other instructions do. + +Instructions that vary in the number of cycles required to execute, other than +the conditional branch instructions, end with a T0 cycle for both the minimum +and maximum execution duration. This covers instructions that use indexed +addressing modes that require one more cycle when page crossing is required to +access the correct memory address. This situation is already covered by +statements above ("All instructions ... always end with T0..."): it has been +specifically (re)stated here for such instructions for reassurance emphasis. + +For all instructions, if the previous instruction's last cycle was a cycle with +T0 in it, its opcode fetch cycle will be a time code of: + +.. T+ .. .. .. .. [..] + +If the previous instruction's last cycle did not have T0, its opcode fetch cycle +will be a time code of: + +.. .. .. .. .. .. [T1] + +Restated, instructions begin with T1 instead of T+ after a conditional branch +instruction that did not branch, or that branched without page crossing. + +Instructions appear to work equally well either way. This is because a new +instruction's first actions do not begin during opcode fetch. Their earliest +effect can be only in the first half of the next cycle, T2, when the IR is set +from the predecode register. + +This implies that an instruction's actions may extend as far as the second half of the opcode fetch of the next instruction, in concert with the T+ time code +bit. Not all instructions may necessarily use this: it could be an unused +constraint for some instructions. + +Branch instructions definitely don't use T+ or T0 (since two cases out of three +don't even cause those time codes to arise). + +In sequence, all of the possible time codes during normal instruction execution +are: + +.. T+ .. .. .. .. [..] OR .. .. .. .. .. .. [T1] +.. .. T2 .. .. .. [..] OR T0 .. T2 .. .. .. [..] +.. .. .. T3 .. .. [..] +.. .. .. .. T4 .. [..] +.. .. .. .. .. T5 [..] +.. .. .. .. .. .. [T6] +T0 .. .. .. .. .. [..] + +The time code: + +T0 T+ .. .. .. .. [..] + +arises when RES is down when a T0 F1 clock state is clocked in. This can be +either the T0 that is usually scheduled for an instruction's last cycle, or +the T0 caused by instruction abort. + diff --git a/expert-allinone.js b/expert-allinone.js index 5449bbd..dc2db67 100644 --- a/expert-allinone.js +++ b/expert-allinone.js @@ -14023,6 +14023,59 @@ function listActiveTCStates() { return s.join("+"); } + // Show all time code node states (active and inactive) in fixed format, + // with T1/T6 indication in square brackets. ".." for a node indicates + // inactive state, "T"* for a node indicates active state. +function allTCStates() +{ + var s = ""; + var allHigh, thisHigh; + thisHigh = isNodeHigh( nodenames[ 'clock1' ] ); + allHigh = thisHigh; + if ( !thisHigh ) s += "T0"; else s += ".."; + s += " "; + // T+ in visual6502 is called T1x in + // http://www.weihenstephan.org/~michaste/pagetable/6502/6502.jpg + // Notated as T+ for compatibility with PLA node names + thisHigh = isNodeHigh( nodenames[ 'clock2' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T+"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't2' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T2"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't3' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T3"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't4' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T4"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't5' ] ) + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T5"; else s += ".."; + s += " ["; + // If all of the time code bits are high (inactive)... + if ( allHigh ) { + // ...distinguish T1 from T6 + // If bits T2 through T5 are actively being cleared... + if ( isNodeHigh( 1357 ) ) { + // ...then this is T1 + s += "T1"; + } else { + // ...else T2 through T5 are clear because the bits ran off the end + // of the T2 through T5 complex: this is T6 + s += "T6"; + } + } else { + s += ".."; + } + s += "]"; + return s; +} + function readBit(name){ return isNodeHigh(nodenames[name])?1:0; } diff --git a/macros.js b/macros.js index e71b8cb..bb05e01 100644 --- a/macros.js +++ b/macros.js @@ -304,6 +304,59 @@ function listActiveTCStates() { return s.join("+"); } + // Show all time code node states (active and inactive) in fixed format, + // with T1/T6 indication in square brackets. ".." for a node indicates + // inactive state, "T"* for a node indicates active state. +function allTCStates() +{ + var s = ""; + var allHigh, thisHigh; + thisHigh = isNodeHigh( nodenames[ 'clock1' ] ); + allHigh = thisHigh; + if ( !thisHigh ) s += "T0"; else s += ".."; + s += " "; + // T+ in visual6502 is called T1x in + // http://www.weihenstephan.org/~michaste/pagetable/6502/6502.jpg + // Notated as T+ for compatibility with PLA node names + thisHigh = isNodeHigh( nodenames[ 'clock2' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T+"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't2' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T2"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't3' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T3"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't4' ] ); + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T4"; else s += ".."; + s += " "; + thisHigh = isNodeHigh( nodenames[ 't5' ] ) + allHigh = allHigh && thisHigh; + if ( !thisHigh ) s += "T5"; else s += ".."; + s += " ["; + // If all of the time code bits are high (inactive)... + if ( allHigh ) { + // ...distinguish T1 from T6 + // If bits T2 through T5 are actively being cleared... + if ( isNodeHigh( 1357 ) ) { + // ...then this is T1 + s += "T1"; + } else { + // ...else T2 through T5 are clear because the bits ran off the end + // of the T2 through T5 complex: this is T6 + s += "T6"; + } + } else { + s += ".."; + } + s += "]"; + return s; +} + function readBit(name){ return isNodeHigh(nodenames[name])?1:0; } From 587fa47d8a6673af8d7a14f08aa4c33ab9b7be5a Mon Sep 17 00:00:00 2001 From: mmfoerster Date: Tue, 19 Sep 2017 21:50:42 -0400 Subject: [PATCH 2/8] Tamed a long line in the new 6502 time codes documentation --- 6502timecodes.txt | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/6502timecodes.txt b/6502timecodes.txt index 61f3f17..6f27a1f 100644 --- a/6502timecodes.txt +++ b/6502timecodes.txt @@ -97,7 +97,8 @@ instruction's first actions do not begin during opcode fetch. Their earliest effect can be only in the first half of the next cycle, T2, when the IR is set from the predecode register. -This implies that an instruction's actions may extend as far as the second half of the opcode fetch of the next instruction, in concert with the T+ time code +This implies that an instruction's actions may extend as far as the second half +of the opcode fetch of the next instruction, in concert with the T+ time code bit. Not all instructions may necessarily use this: it could be an unused constraint for some instructions. From d39bab73024efa0ef0f06bb870877b370dedaffe Mon Sep 17 00:00:00 2001 From: mmfoerster Date: Tue, 19 Sep 2017 23:56:43 -0400 Subject: [PATCH 3/8] Clarified causation statement about T0 T+ time code in 6502 time codes documentation --- 6502timecodes.txt | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/6502timecodes.txt b/6502timecodes.txt index 6f27a1f..add6d70 100644 --- a/6502timecodes.txt +++ b/6502timecodes.txt @@ -120,7 +120,7 @@ The time code: T0 T+ .. .. .. .. [..] -arises when RES is down when a T0 F1 clock state is clocked in. This can be -either the T0 that is usually scheduled for an instruction's last cycle, or -the T0 caused by instruction abort. +arises when RES is down when a T0 phase 1 clock state is clocked in. This can +be either the T0 that is usually scheduled for an instruction's last cycle, or +the T0 caused by instruction abort (later caused by the RES). From c1409b78cb98509d2bc031cc92a395f96886cb27 Mon Sep 17 00:00:00 2001 From: mmfoerster Date: Mon, 9 Oct 2017 17:49:53 -0400 Subject: [PATCH 4/8] busToString( 'TState' ) and busToString( 'TStateF' ) now call allTCStates(). 'TState' returns the string returned by allTCStates(). 'TStateF' returns the string returned by allTCStates() with phase indication appended: "F1" or "F2" for phase1 or phase2 respectively. 'F' is chosen since that's all that Phi really is: an "eff". Perhaps another enhancement could call out an actual phi glyph for the HTML (browser) context. allTCStates() is also enhanced by an optional boolean parameter to control the spacing of non-blank text within the string it returns. * A true parameter puts HTML non-breaking spaces between non-blank text, suitable for display on a browser page. This is always used by busToString(). * A false or absent parameter puts ASCII spaces between non-blank text, suitable for text logging. --- expert-allinone.js | 29 ++++++++++++++++++++++------- macros.js | 29 ++++++++++++++++++++++------- 2 files changed, 44 insertions(+), 14 deletions(-) diff --git a/expert-allinone.js b/expert-allinone.js index dc2db67..139dda1 100644 --- a/expert-allinone.js +++ b/expert-allinone.js @@ -14026,37 +14026,42 @@ function listActiveTCStates() { // Show all time code node states (active and inactive) in fixed format, // with T1/T6 indication in square brackets. ".." for a node indicates // inactive state, "T"* for a node indicates active state. -function allTCStates() +function allTCStates( useNBSP ) { var s = ""; + var _spc; + useNBSP = (typeof useNBSP === 'undefined') ? false : useNBSP; + // Use Non-Breaking Space for presentation in an HTML (browser) + // context, else use ASCII space for logging context + _spc = useNBSP ? ' ' : ' '; var allHigh, thisHigh; thisHigh = isNodeHigh( nodenames[ 'clock1' ] ); allHigh = thisHigh; if ( !thisHigh ) s += "T0"; else s += ".."; - s += " "; + s += _spc; // T+ in visual6502 is called T1x in // http://www.weihenstephan.org/~michaste/pagetable/6502/6502.jpg // Notated as T+ for compatibility with PLA node names thisHigh = isNodeHigh( nodenames[ 'clock2' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T+"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't2' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T2"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't3' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T3"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't4' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T4"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't5' ] ) allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T5"; else s += ".."; - s += " ["; + s += _spc + "["; // If all of the time code bits are high (inactive)... if ( allHigh ) { // ...distinguish T1 from T6 @@ -14102,6 +14107,16 @@ function busToString(busname){ return ['clock1','clock2','t2','t3','t4','t5'].map(busToHex).join(""); if(busname=='State') return listActiveTCStates(); + if(busname=='TState') + return allTCStates( true ); + if(busname=='TStateF') + // TState with phase indication tacked on: F1 or F2 + // Prefer latin 'F' because that's what Greek phi really is: + // a single glyph for the "eff" speech sound + // Capitalized because the 'T's in the time state are + // capitalized + return allTCStates( true ) + ' ' + 'F' + + (isNodeHigh( nodenames[ 'cp1' ] ) ? '1' : '2'); if(busname=='Execute') return dis6502toHTML(readBits('ir',8)); if(busname=='Fetch') diff --git a/macros.js b/macros.js index bb05e01..17e80d7 100644 --- a/macros.js +++ b/macros.js @@ -307,37 +307,42 @@ function listActiveTCStates() { // Show all time code node states (active and inactive) in fixed format, // with T1/T6 indication in square brackets. ".." for a node indicates // inactive state, "T"* for a node indicates active state. -function allTCStates() +function allTCStates( useNBSP ) { var s = ""; + var _spc; + useNBSP = (typeof useNBSP === 'undefined') ? false : useNBSP; + // Use Non-Breaking Space for presentation in an HTML (browser) + // context, else use ASCII space for logging context + _spc = useNBSP ? ' ' : ' '; var allHigh, thisHigh; thisHigh = isNodeHigh( nodenames[ 'clock1' ] ); allHigh = thisHigh; if ( !thisHigh ) s += "T0"; else s += ".."; - s += " "; + s += _spc; // T+ in visual6502 is called T1x in // http://www.weihenstephan.org/~michaste/pagetable/6502/6502.jpg // Notated as T+ for compatibility with PLA node names thisHigh = isNodeHigh( nodenames[ 'clock2' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T+"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't2' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T2"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't3' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T3"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't4' ] ); allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T4"; else s += ".."; - s += " "; + s += _spc; thisHigh = isNodeHigh( nodenames[ 't5' ] ) allHigh = allHigh && thisHigh; if ( !thisHigh ) s += "T5"; else s += ".."; - s += " ["; + s += _spc + "["; // If all of the time code bits are high (inactive)... if ( allHigh ) { // ...distinguish T1 from T6 @@ -383,6 +388,16 @@ function busToString(busname){ return ['clock1','clock2','t2','t3','t4','t5'].map(busToHex).join(""); if(busname=='State') return listActiveTCStates(); + if(busname=='TState') + return allTCStates( true ); + if(busname=='TStateF') + // TState with phase indication tacked on: F1 or F2 + // Prefer latin 'F' because that's what Greek phi really is: + // a single glyph for the "eff" speech sound + // Capitalized because the 'T's in the time state are + // capitalized + return allTCStates( true ) + ' ' + 'F' + + (isNodeHigh( nodenames[ 'cp1' ] ) ? '1' : '2'); if(busname=='Execute') return disassemblytoHTML(readBits('ir',8)); if(busname=='Fetch') From 76edc1186a9b7ae31f276b28ad726a428a744620 Mon Sep 17 00:00:00 2001 From: mmfoerster Date: Wed, 25 Oct 2017 11:39:23 -0400 Subject: [PATCH 5/8] Deleted 6502timecodes.txt: content moved to the visual6502 wiki. Documentation is more appropriately stored there instead of the repository. It is also further developed there: http://visual6502.org/wiki/index.php?title=6502_Timing_States --- 6502timecodes.txt | 126 ---------------------------------------------- 1 file changed, 126 deletions(-) delete mode 100644 6502timecodes.txt diff --git a/6502timecodes.txt b/6502timecodes.txt deleted file mode 100644 index add6d70..0000000 --- a/6502timecodes.txt +++ /dev/null @@ -1,126 +0,0 @@ -6502 Time codes. - - There are two things that are critical for correct instruction execution in -the 6502 (indeed, for any CPU chip): the pattern of bits in the instruction -register AND the pattern of "time code" bits from the timing control block of -circuits. - Both sets of bits (IR and time code), in combination, control the output -bits of the PLA block of circuits. PLA outputs, in turn, affect the RCL block -of circuits, and their control outputs directly operate the connections among -the registers, busses, and ALU on the other end of the chip die to actually get -the instructions' work done. - The 6502's timing control has ten states (effectively) and six explicit -output bits. Only the explicit output bits affect the PLA. The output bits are -labelled T0, T+, T2, T3, T4, and T5. The bits are considered active when their -logic states are low. There are two states where two of these explicit output -bits are active at the same time. There are also two states where none of the -explicit output bits are active. All other states have only one output bit -active at a time. - The two states with two bits active together are T0 with T+, and T0 with T2. -The two states with all explicit bits inactive are referred to as T1 and T6. -Those two states can only be distinguished within the timing control block of -circuits by paying attention to a logic node that is responsible for clearing -(making inactive) the explicit output bits T2 through T5. The clearing node -at logic high (active) corresponds to the T1 state, and low corresponds to the -T6 state. For the visual6502, this is node 1357. - - The notation developed for trace/debug output, and the notation presented -hereafter in this document, lists the explicit output bits in numeric order -followed by square brackets around the non-explicit internal state of T1 or T6. -When one or more of the explicit bits is active, the square bracketed label will -be blank. - Wherever one of the explicit bits is inactive, a blank placeholder of ".." -is present for it. This also applies to the bracketed label. - -For example, the T0 state is presented as: - -T0 .. .. .. .. .. [..] - -...and the T1 state is presented as: - -.. .. .. .. .. .. [T1] - - The low-profile "blank" notation of ".." assists visual examination of -trace/debug output by keeping consistent placeholders for bits when they are -inactive, with minimized visual clutter. Aligning everything in fixed positions -contributes to rapid recognition of changes. - -Time codes seen around instruction execution - -All instructions, with a few exceptions, always end with T0 in their time code -for the last cycle. The presence of T0 indicates, "last cycle". - -The strictly 2-cycle instructions always end with the time code: - -T0 .. T2 .. .. .. [..] - -All other instructions end with the time code: - -T0 .. .. .. .. .. [..] - -The mentioned exceptions to last-cycle T0 time codes are the conditional branch -instructions. When they do not take the branch, their last cycle time code is: - -.. .. T2 .. .. .. [..] - -When they do take the branch, and the branch does not cross a memory page, their -last cycle time code is: - -.. .. .. T3 .. .. [..] - -When the branch instructions take the branch, and the branch crosses a memory -page, they end with a T0 last cycle just like all the other instructions do. - -Instructions that vary in the number of cycles required to execute, other than -the conditional branch instructions, end with a T0 cycle for both the minimum -and maximum execution duration. This covers instructions that use indexed -addressing modes that require one more cycle when page crossing is required to -access the correct memory address. This situation is already covered by -statements above ("All instructions ... always end with T0..."): it has been -specifically (re)stated here for such instructions for reassurance emphasis. - -For all instructions, if the previous instruction's last cycle was a cycle with -T0 in it, its opcode fetch cycle will be a time code of: - -.. T+ .. .. .. .. [..] - -If the previous instruction's last cycle did not have T0, its opcode fetch cycle -will be a time code of: - -.. .. .. .. .. .. [T1] - -Restated, instructions begin with T1 instead of T+ after a conditional branch -instruction that did not branch, or that branched without page crossing. - -Instructions appear to work equally well either way. This is because a new -instruction's first actions do not begin during opcode fetch. Their earliest -effect can be only in the first half of the next cycle, T2, when the IR is set -from the predecode register. - -This implies that an instruction's actions may extend as far as the second half -of the opcode fetch of the next instruction, in concert with the T+ time code -bit. Not all instructions may necessarily use this: it could be an unused -constraint for some instructions. - -Branch instructions definitely don't use T+ or T0 (since two cases out of three -don't even cause those time codes to arise). - -In sequence, all of the possible time codes during normal instruction execution -are: - -.. T+ .. .. .. .. [..] OR .. .. .. .. .. .. [T1] -.. .. T2 .. .. .. [..] OR T0 .. T2 .. .. .. [..] -.. .. .. T3 .. .. [..] -.. .. .. .. T4 .. [..] -.. .. .. .. .. T5 [..] -.. .. .. .. .. .. [T6] -T0 .. .. .. .. .. [..] - -The time code: - -T0 T+ .. .. .. .. [..] - -arises when RES is down when a T0 phase 1 clock state is clocked in. This can -be either the T0 that is usually scheduled for an instruction's last cycle, or -the T0 caused by instruction abort (later caused by the RES). - From e0547e6c354bad442c340ed1f31ac343aa69f022 Mon Sep 17 00:00:00 2001 From: BigEd Date: Sat, 28 Oct 2017 13:49:46 +0100 Subject: [PATCH 6/8] merge clock phase display into TState pseudobus --- macros.js | 19 +++++++------------ 1 file changed, 7 insertions(+), 12 deletions(-) diff --git a/macros.js b/macros.js index 17e80d7..a7bfd16 100644 --- a/macros.js +++ b/macros.js @@ -307,14 +307,16 @@ function listActiveTCStates() { // Show all time code node states (active and inactive) in fixed format, // with T1/T6 indication in square brackets. ".." for a node indicates // inactive state, "T"* for a node indicates active state. -function allTCStates( useNBSP ) +function allTCStates( useHTML ) { var s = ""; var _spc; - useNBSP = (typeof useNBSP === 'undefined') ? false : useNBSP; + var _phi; + var useHTML = (typeof useHTML === 'undefined') ? false : useHTML; // Use Non-Breaking Space for presentation in an HTML (browser) // context, else use ASCII space for logging context - _spc = useNBSP ? ' ' : ' '; + _spc = useHTML ? ' ' : ' '; + _phi = useHTML ? 'Φ' : 'F'; var allHigh, thisHigh; thisHigh = isNodeHigh( nodenames[ 'clock1' ] ); allHigh = thisHigh; @@ -358,7 +360,8 @@ function allTCStates( useNBSP ) } else { s += ".."; } - s += "]"; + // indicate the clock phase, Phi1 or Phi2 + s += "]" + _spc + _phi + (isNodeHigh( nodenames[ 'cp1' ] ) ? '1' : '2'); return s; } @@ -390,14 +393,6 @@ function busToString(busname){ return listActiveTCStates(); if(busname=='TState') return allTCStates( true ); - if(busname=='TStateF') - // TState with phase indication tacked on: F1 or F2 - // Prefer latin 'F' because that's what Greek phi really is: - // a single glyph for the "eff" speech sound - // Capitalized because the 'T's in the time state are - // capitalized - return allTCStates( true ) + ' ' + 'F' + - (isNodeHigh( nodenames[ 'cp1' ] ) ? '1' : '2'); if(busname=='Execute') return disassemblytoHTML(readBits('ir',8)); if(busname=='Fetch') From ef0a714a2982588c5c1cecccad4fac1b4163e0e3 Mon Sep 17 00:00:00 2001 From: mmfoerster Date: Mon, 30 Oct 2017 00:49:17 -0400 Subject: [PATCH 7/8] busToString() and allTCStates() changes agreed to online: TState and Phi. The parameter to allTCStates() has had a name change from useNBSP to useHTML. busToString() has had the TStateF pseudobus removed, and a pseudobus called Phi added. Phi pretty-prints the state of the cp1 node (the internal phase 1 node) as Φ1 when high and as Φ2 when low. This is nicer than plain 0 or 1. Logging the TState pseudobus followed by the Phi pseudobus creates the effect intended by the removed TStateF pseudobus, keeping our collection of operations orthogonal (no proliferation of trivially different operations that duplicate each other diagonally). --- expert-allinone.js | 17 +++++++---------- macros.js | 12 +++++++----- 2 files changed, 14 insertions(+), 15 deletions(-) diff --git a/expert-allinone.js b/expert-allinone.js index 139dda1..3aa625b 100644 --- a/expert-allinone.js +++ b/expert-allinone.js @@ -14026,14 +14026,14 @@ function listActiveTCStates() { // Show all time code node states (active and inactive) in fixed format, // with T1/T6 indication in square brackets. ".." for a node indicates // inactive state, "T"* for a node indicates active state. -function allTCStates( useNBSP ) +function allTCStates( useHTML ) { var s = ""; var _spc; - useNBSP = (typeof useNBSP === 'undefined') ? false : useNBSP; + useHTML = (typeof useHTML === 'undefined') ? false : useHTML; // Use Non-Breaking Space for presentation in an HTML (browser) // context, else use ASCII space for logging context - _spc = useNBSP ? ' ' : ' '; + _spc = useHTML ? ' ' : ' '; var allHigh, thisHigh; thisHigh = isNodeHigh( nodenames[ 'clock1' ] ); allHigh = thisHigh; @@ -14109,13 +14109,10 @@ function busToString(busname){ return listActiveTCStates(); if(busname=='TState') return allTCStates( true ); - if(busname=='TStateF') - // TState with phase indication tacked on: F1 or F2 - // Prefer latin 'F' because that's what Greek phi really is: - // a single glyph for the "eff" speech sound - // Capitalized because the 'T's in the time state are - // capitalized - return allTCStates( true ) + ' ' + 'F' + + if(busname=='Phi') + // Pretty-printed phase indication based on the state of cp1, + // the internal Phase 1 node + return 'Φ' + (isNodeHigh( nodenames[ 'cp1' ] ) ? '1' : '2'); if(busname=='Execute') return dis6502toHTML(readBits('ir',8)); diff --git a/macros.js b/macros.js index a7bfd16..0af377c 100644 --- a/macros.js +++ b/macros.js @@ -311,12 +311,10 @@ function allTCStates( useHTML ) { var s = ""; var _spc; - var _phi; - var useHTML = (typeof useHTML === 'undefined') ? false : useHTML; + useHTML = (typeof useHTML === 'undefined') ? false : useHTML; // Use Non-Breaking Space for presentation in an HTML (browser) // context, else use ASCII space for logging context _spc = useHTML ? ' ' : ' '; - _phi = useHTML ? 'Φ' : 'F'; var allHigh, thisHigh; thisHigh = isNodeHigh( nodenames[ 'clock1' ] ); allHigh = thisHigh; @@ -360,8 +358,7 @@ function allTCStates( useHTML ) } else { s += ".."; } - // indicate the clock phase, Phi1 or Phi2 - s += "]" + _spc + _phi + (isNodeHigh( nodenames[ 'cp1' ] ) ? '1' : '2'); + s += "]"; return s; } @@ -393,6 +390,11 @@ function busToString(busname){ return listActiveTCStates(); if(busname=='TState') return allTCStates( true ); + if(busname=='Phi') + // Pretty-printed phase indication based on the state of cp1, + // the internal Phase 1 node + return 'Φ' + + (isNodeHigh( nodenames[ 'cp1' ] ) ? '1' : '2'); if(busname=='Execute') return disassemblytoHTML(readBits('ir',8)); if(busname=='Fetch') From 7efe4fb8c774ab64dad3f230975d19ab9bb2a48b Mon Sep 17 00:00:00 2001 From: mmfoerster Date: Mon, 30 Oct 2017 14:08:57 -0400 Subject: [PATCH 8/8] Added comments to allTCStates() referring to the 6502_Timing_States wiki page. The state labeling is not completely correct or complete regarding T5 and T6 (especially the latter). More investment will be forthcoming. --- expert-allinone.js | 2 ++ macros.js | 2 ++ 2 files changed, 4 insertions(+) diff --git a/expert-allinone.js b/expert-allinone.js index 3aa625b..9ef08d0 100644 --- a/expert-allinone.js +++ b/expert-allinone.js @@ -14026,6 +14026,8 @@ function listActiveTCStates() { // Show all time code node states (active and inactive) in fixed format, // with T1/T6 indication in square brackets. ".." for a node indicates // inactive state, "T"* for a node indicates active state. + // For discussion of this reconstruction, see: + // http://visual6502.org/wiki/index.php?title=6502_Timing_States function allTCStates( useHTML ) { var s = ""; diff --git a/macros.js b/macros.js index 0af377c..3aa26de 100644 --- a/macros.js +++ b/macros.js @@ -307,6 +307,8 @@ function listActiveTCStates() { // Show all time code node states (active and inactive) in fixed format, // with T1/T6 indication in square brackets. ".." for a node indicates // inactive state, "T"* for a node indicates active state. + // For discussion of this reconstruction, see: + // http://visual6502.org/wiki/index.php?title=6502_Timing_States function allTCStates( useHTML ) { var s = "";