mirror of
https://github.com/peterdell/wudsn-ide.git
synced 2024-06-03 06:29:35 +00:00
294 lines
8.3 KiB
NASM
294 lines
8.3 KiB
NASM
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; EXAMPLE.ASM (6502 Microprocessor)
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;
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processor 6502
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mac ldax
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lda [{1}]
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ldx [{1}]+1
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endm
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mac ldaxi
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lda #<[{1}]
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ldx #>[{1}]
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endm
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mac stax
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sta [{1}]
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stx [{1}]+1
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endm
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mac pushxy
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txa
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pha
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tya
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pha
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endm
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mac popxy
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pla
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tay
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pla
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tax
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endm
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mac inc16
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inc {1}
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bne .1
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inc {1}+1
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.1
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endm
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STOP1 equ %00000000 ;CxCTL 1 Stop bit
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STOP2 equ %10000000 ;CxCTL 2 Stop bits (WL5:1.5, WL8&par:1)
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WL5 equ %01100000 ;CxCTL Wordlength
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WL6 equ %01000000
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WL7 equ %00100000
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WL8 equ %00000000
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RCS equ %00010000 ;CxCTL 1=Select baud, 0=ext. receiver clk
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B76800 equ %0000 ;CxCTL Baud rates (1.2288 Mhz clock)
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B75 equ %0001
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B100 equ %0010
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B150 equ %0011
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B200 equ %0100
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B300 equ %0101
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B400 equ %0110
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B600 equ %0111
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B800 equ %1000
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B1200 equ %1001
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B1600 equ %1010
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B2400 equ %1011
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B3200 equ %1100
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B4800 equ %1101
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B6400 equ %1110
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B12800 equ %1111
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PARODD equ %00100000 ;CxCMD Select Parity
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PAREVEN equ %01100000
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PARMARK equ %10100000
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PARSPACE equ %11100000
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PAROFF equ %00000000
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RECECHO equ %00010000 ;CxCMD Receiver Echo mode
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TMASK equ %00001100
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TDISABLE equ %00000000 ;CxCMD Transmitter modes
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TDISABLER equ %00001000 ;RTS stays asserted
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TENABLE equ %00000100
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TBREAK equ %00001100 ;send break
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UA_IRQDSBL equ %00000010
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DTRRDY equ %00000001 ;~DTR output is inverted (low)
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SR_PE equ %00000001 ;CxSTAT Status
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SR_FE equ %00000010 ;NOTE: writing dummy data causes RESET
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SR_OVRUN equ %00000100
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SR_RDRFULL equ %00001000
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SR_TDREMPTY equ %00010000
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SR_DCD equ %00100000
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SR_DSR equ %01000000
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SR_INTPEND equ %10000000
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T1_OEPB7 equ %10000000 ;x_ACR
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T1_FREERUN equ %01000000 ;T1 free running mode
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T1_ONESHOT equ %00000000
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T2_ICPB6 equ %00100000 ;T2 counts pulses on PB6
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T2_ONESHOT equ %00000000 ;T2 counts phase2 transitions
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SRC_OFF equ %00000000 ;shift register control
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SRC_INT2 equ %00000100
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SRC_INPH2 equ %00001000
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SRC_INEXT equ %00001100
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SRC_OUTFR equ %00010000 ;free running output using T2
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SRC_OUTT2 equ %00010100
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SRC_OUTPH2 equ %00011000
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SRC_OUTEXT equ %00011100
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PBLE equ %00000010 ;on CB1 transition (in/out).
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PALE equ %00000001 ;on CA1 transition (in). data retained
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;x_PCR
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CB2_I_NEG equ %00000000 ;interrupt on neg trans, r/w ORB clears
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CB2_I_NEGI equ %00100000 ; same, but r/w ORB does not clear int
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CB2_I_POS equ %01000000 ;interrupt on pos trans, r/w ORB clears
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CB2_I_POSI equ %01100000 ; same, but r/w ORB does not clear int
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CB2_O_HSHAK equ %10000000 ;CB2=0 on r/w ORB, CB2=1 on CB1 transition
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CB2_O_PULSE equ %10100000 ;CB2=0 for one clock after r/w ORB
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CB2_O_MANLO equ %11000000 ;CB2=0
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CB2_O_MANHI equ %11100000 ;CB2=1
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CA2_I_NEG equ %00000000 ;interrupt on neg trans, r/w ORA clears
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CA2_I_NEGI equ %00100000 ; same, but r/w ORA does not clear int
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CA2_I_POS equ %01000000 ;interrupt on pos trans, r/w ORA clears
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CA2_I_POSI equ %01100000 ; same, but r/w ORA does not clear int
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CA2_O_HSHAK equ %10000000 ;CA2=0 on r/w ORA, CA2=1 on CA1 transition
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CA2_O_PULSE equ %10100000 ;CA2=0 for one clock after r/w ORA
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CA2_O_MANLO equ %11000000 ;CA2=0
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CA2_O_MANHI equ %11100000 ;CA2=1
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CB1_THI equ %00010000
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CB1_TLO equ %00000000
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CA1_THI equ %00000001
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CA1_TLO equ %00000000
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VIRPEND equ %10000000 ;x_IFR
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IRENABLE equ %10000000 ;x_IER 1's enable ints 0=no change
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IRDISABLE equ %00000000 ;x_IER 1's disable ints 0=no change
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IRT1 equ %01000000
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IRT2 equ %00100000
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IRCB1 equ %00010000
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IRCB2 equ %00001000
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IRSR equ %00000100
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IRCA1 equ %00000010
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IRCA2 equ %00000001
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seg.u bss
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org $0000 ;RAM (see below)
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org $2000 ;unused
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org $4000 ;unused
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org $6000 ;6551 CHANNEL #1
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C1DATA ds 1
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C1STAT ds 1
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C1CMD ds 1
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C1CTL ds 1
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org $8000 ;6551 CHANNEL #2
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C2DATA ds 1
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C2STAT ds 1
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C2CMD ds 1
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C2CTL ds 1
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org $A000 ;6522 (HOST COMM)
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H_ORB ds 1
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H_ORAHS ds 1 ;with CA2 handshake
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H_DDRB ds 1
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H_DDRA ds 1
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H_T1CL ds 1 ;read clears interrupt flag
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H_T1CH ds 1 ;write clears interrupt flag
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H_T1CLL ds 1
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H_T1CHL ds 1 ;write clears interrupt flag
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H_T2CL ds 1 ;read clears interrupt flag
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H_T2CH ds 1 ;write clears interrupt flag
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H_SR ds 1
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H_ACR ds 1
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H_PCR ds 1
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H_IFR ds 1
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H_IER ds 1
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H_ORA ds 1 ;no CA2 handshake
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org $C000 ;6522 (IO COMM)
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I_ORB ds 1
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I_ORAHS ds 1 ; (same comments apply)
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I_DDRB ds 1
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I_DDRA ds 1
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I_T1CL ds 1
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I_T1CH ds 1
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I_T1CLL ds 1
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I_T1CHL ds 1
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I_T2CL ds 1
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I_T2CH ds 1
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I_SR ds 1
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I_ACR ds 1
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I_PCR ds 1
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I_IFR ds 1
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I_IER ds 1
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I_ORA ds 1
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; -------------------------- ZERO PAGE -------------------
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seg.u data
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org $00
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; -------------------------- NORMAL RAM -------------------
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org $0100
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RAMEND equ $2000
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; -------------------------- CODE -------------------
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seg code
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org $F000
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PROMBEG equ .
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RESET subroutine
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sei ;disable interrupts
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ldx #$FF ;reset stack
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txs
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lda #$FF
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sta H_DDRA
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sta C1STAT2 ;reset 6551#1 (garbage data)
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sta C2STAT ;reset 6551#2
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lda #$7F ;disable all 6522 interrupts
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sta H_IER
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sta I_IER
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lda #%00010000 ;76.8 baud, 8 bits, 1 stop
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sta C1CTL
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lda #%00000101 ;no parity, enable transmitter & int
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sta C1CMD
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lda #$AA ;begin transmision
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sta C1DATA
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lda #%00011111 ;9600 baud, 8 bits, 1 stop
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sta C2CTL
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lda #%00000101
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sta C2CMD
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lda #$41
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sta C2DATA
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cli ;enable interrupts
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.1 jsr LOAD
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jsr SAVE
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jmp .1
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LOAD subroutine
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ldx #0
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.1 txa
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sta $0500,x
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inx
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bne .1
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rts
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SAVE subroutine
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ldx #0
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.2 lda $0500,x
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sta H_ORA
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inx
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bne .2
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rts
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NMI rti
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subroutine
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IRQ bit C1STAT
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bpl .1
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pha
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lda #$AA
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sta C1DATA
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lda C1DATA
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pla
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rti
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.1 bit C2STAT
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bpl .2
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pha
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lda #$41
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sta C2DATA
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lda C2DATA
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pla
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.2 rti
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; VECTOR ------------------------------------------------
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seg vector
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org $FFFA
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dc.w NMI
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dc.w RESET
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dc.w IRQ
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PROMEND equ .
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