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Better logic for what separates code segments

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- Allows jump tables without separating between each instruction
- Branch to instruction after jump instruction does not inject a
function separator
- Jump relative does not reference code
This commit is contained in:
Carl-Henrik Skårstedt 2015-12-09 18:22:07 -08:00
parent a674f7f165
commit 798b657c70
1 changed files with 14 additions and 12 deletions
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24
disassembler/x65dsasm.cpp
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@ -1149,7 +1149,7 @@ void GetReferences(unsigned char *mem, size_t bytes, bool acc_16, bool ind_16, i
reference = (unsigned short)mem[0] + ((unsigned short)mem[1]<<8); reference = (unsigned short)mem[0] + ((unsigned short)mem[1]<<8);
if (op == 0x20 || op == 0xfc || op == 0x22) // jsr opcodes if (op == 0x20 || op == 0xfc || op == 0x22) // jsr opcodes
type = RT_JSR; type = RT_JSR;
else if (op == 0x4c || op == 0x6c || op == 0x7c || op == 0x5c || op == 0xdc) // jmp opcodes else if (op == 0x4c || op == 0x7c || op == 0x5c || op == 0xdc) // jmp opcodes
type = RT_JUMP; type = RT_JUMP;
else else
type = RT_DATA; type = RT_DATA;
@ -1276,7 +1276,7 @@ void GetReferences(unsigned char *mem, size_t bytes, bool acc_16, bool ind_16, i
was_data = refs[curr_label].data==DT_DATA; was_data = refs[curr_label].data==DT_DATA;
} else { } else {
bool prev_data = was_data; bool prev_data = was_data;
was_data = separator && !(!was_data && ((op==0x4c || op==0x6c) && (prev_op==0x4c || prev_op==0x6c))); was_data = separator && !(!was_data && op==0x4c && prev_op==0x4c);
if (!prev_data) { if (!prev_data) {
for (size_t j = 0; j<pRefs.size(); ++j) { for (size_t j = 0; j<pRefs.size(); ++j) {
RefType type = pRefs[j].type; RefType type = pRefs[j].type;
@ -1349,18 +1349,20 @@ void GetReferences(unsigned char *mem, size_t bytes, bool acc_16, bool ind_16, i
if (op == 0x60 || op == 0x40 || op == 0x6b || if (op == 0x60 || op == 0x40 || op == 0x6b ||
((op == 0x4c || op == 0x6c) && (prev_op!=0x4c && prev_op!=0x6c)) || ((op == 0x4c || op == 0x6c) && (prev_op!=0x4c && prev_op!=0x6c)) ||
op == 0x6c || op == 0x7c || op == 0x5c || op == 0xdc) { // rts, rti, rtl or jmp op == 0x6c || op == 0x7c || op == 0x5c || op == 0xdc) { // rts, rti, rtl or jmp
separator = true; bool exit_instr = false;
cutoff = false; int lbl = GetLabelIndex(addr);
for (size_t i = curr_label+1; i<refs.size() && (refs[i].address-curr)<0x7e; i++) { // check no branch crossing if (lbl>=0) {
if (refs[i].address<=curr) { std::vector<RefLink> &links = *refs[lbl].pRefs;
std::vector<RefLink> &pRefs = *refs[i].pRefs; for (std::vector<RefLink>::iterator lnk = links.begin(); lnk!=links.end(); ++lnk) {
for (size_t j = 0; j<pRefs.size() && separator; ++j) { if (lnk->type == RT_BRANCH && lnk->instr_addr<addr) {
if (pRefs[j].type == RT_BRANCH && pRefs[j].instr_addr>curr) { exit_instr = true;
separator = false;
break; break;
} }
} }
} } // branch over rts/jmp or sequential jmp doesn't count as separator
if (!exit_instr && op!=0x4c && bytes && *mem!=0x4c) {
separator = true;
cutoff = false;
} }
} }
} }