diff --git a/.gitignore b/.gitignore
index c036379..5eab121 100644
--- a/.gitignore
+++ b/.gitignore
@@ -1 +1,2 @@
-tmp/
\ No newline at end of file
+tmp/
+design/DesignSpark/gbrl
\ No newline at end of file
diff --git a/docs/memory/32k-Apple-1-EEPROM.hex b/code/memory/32k-Apple-1-EEPROM.hex
similarity index 100%
rename from docs/memory/32k-Apple-1-EEPROM.hex
rename to code/memory/32k-Apple-1-EEPROM.hex
diff --git a/docs/memory/8k-Apple-1-EEPROM.hex b/code/memory/8k-Apple-1-EEPROM.hex
similarity index 100%
rename from docs/memory/8k-Apple-1-EEPROM.hex
rename to code/memory/8k-Apple-1-EEPROM.hex
diff --git a/docs/memory/README.md b/code/memory/README.md
similarity index 100%
rename from docs/memory/README.md
rename to code/memory/README.md
diff --git a/docs/memory/memory-map.jpg b/code/memory/memory-map.jpg
similarity index 100%
rename from docs/memory/memory-map.jpg
rename to code/memory/memory-map.jpg
diff --git a/design/DesignSpark/schematic - Schematic.pdf b/design/DesignSpark/schematic - Schematic.pdf
index 6369137..0cff2f9 100644
Binary files a/design/DesignSpark/schematic - Schematic.pdf and b/design/DesignSpark/schematic - Schematic.pdf differ
diff --git a/design/DesignSpark/schematic.mop b/design/DesignSpark/schematic.mop
new file mode 100644
index 0000000..b0bae4e
--- /dev/null
+++ b/design/DesignSpark/schematic.mop
@@ -0,0 +1,326 @@
+MOPFILE 2
+DESIGN_TYPE PCB_DESIGN
+DESCRIPTION ""
+# ============
+PLOT "Top Silkscreen"
+DEVICETYPE 1
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED Y
+VARIANTNAME ""
+LAYER BOARDUNPLATED Y
+LAYER SIDE SIDE_TOP LAYERTYPE NONELEC NAME "Top Silkscreen" LAYERTYPENAME "Silk Screen"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+BOARD Y
+BOARDPLATED N
+BOARDUNPLATED Y
+PINS N
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+PANELOUTLINES N
+PANELPCBCONTENTS N
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Top Copper"
+DEVICETYPE 1
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED Y
+VARIANTNAME ""
+LAYER SIDE SIDE_TOP LAYERTYPE ELECTRICAL NAME "Top Copper" LAYERTYPENAME "Electrical"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+BOARD N
+BOARDPLATED N
+BOARDUNPLATED N
+PINS N
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+PANELOUTLINES N
+PANELPCBCONTENTS N
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Top Copper (Resist)"
+DEVICETYPE 1
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED Y
+VARIANTNAME ""
+LAYER SIDE SIDE_TOP LAYERTYPE ELECTRICAL NAME "Top Copper" LAYERTYPENAME "Electrical"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 1270 OVERSIZE_PERCENT 10 LARGER TESTLAND_VIAS DRILLED_PADS UNDRILLED_PADS
+BOARD N
+BOARDPLATED Y
+BOARDUNPLATED Y
+PINS Y
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+PANELOUTLINES N
+PANELPCBCONTENTS Y
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Top Copper (Paste)"
+DEVICETYPE 1
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED N
+VARIANTNAME ""
+LAYER SIDE SIDE_TOP LAYERTYPE ELECTRICAL NAME "Top Copper" LAYERTYPENAME "Electrical"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 508 OVERSIZE_PERCENT 10 SMALLER TESTLAND_VIAS UNDRILLED_PADS
+BOARD N
+BOARDPLATED Y
+BOARDUNPLATED Y
+PINS Y
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+PANELOUTLINES N
+PANELPCBCONTENTS Y
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Bottom Copper"
+DEVICETYPE 1
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED Y
+VARIANTNAME ""
+LAYER SIDE SIDE_BOTTOM LAYERTYPE ELECTRICAL NAME "Bottom Copper" LAYERTYPENAME "Electrical"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+BOARD N
+BOARDPLATED N
+BOARDUNPLATED N
+PINS N
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+PANELOUTLINES N
+PANELPCBCONTENTS N
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Bottom Copper (Resist)"
+DEVICETYPE 1
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED Y
+VARIANTNAME ""
+LAYER SIDE SIDE_BOTTOM LAYERTYPE ELECTRICAL NAME "Bottom Copper" LAYERTYPENAME "Electrical"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 1270 OVERSIZE_PERCENT 10 LARGER TESTLAND_VIAS DRILLED_PADS UNDRILLED_PADS
+BOARD N
+BOARDPLATED Y
+BOARDUNPLATED Y
+PINS Y
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+PANELOUTLINES N
+PANELPCBCONTENTS Y
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Bottom Copper (Paste)"
+DEVICETYPE 1
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED N
+VARIANTNAME ""
+LAYER SIDE SIDE_BOTTOM LAYERTYPE ELECTRICAL NAME "Bottom Copper" LAYERTYPENAME "Electrical"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+PADS_ONLY OVERSIZE_ABSOLUTE 1 OVERSIZE 508 OVERSIZE_PERCENT 10 SMALLER TESTLAND_VIAS UNDRILLED_PADS
+BOARD N
+BOARDPLATED Y
+BOARDUNPLATED Y
+PINS Y
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+PANELOUTLINES N
+PANELPCBCONTENTS Y
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Drill Data - [Through Hole]"
+DEVICETYPE 4
+PLOT_TYPE ARTWORK
+OUTPUT_TO FILE
+PLOTENABLED Y
+VARIANTNAME ""
+LAYER LAYERTYPE SPAN NAME "[Through Hole]"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+BOARD N
+BOARDPLATED Y
+BOARDUNPLATED Y
+PINS Y
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+DRILLPLATEDBOARD Y
+DRILLUNPLATEDBOARD Y
+DRILLPLATEDHOLES Y
+DRILLUNPLATEDHOLES Y
+DRILLROUNDHOLES Y
+DRILLSLOTS Y
+PANELOUTLINES N
+PANELPCBCONTENTS Y
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
+# ============
+PLOT "Drill Ident Drawing - [Through Hole]"
+DEVICETYPE 1
+PLOT_TYPE DRILLIDENT
+OUTPUT_TO FILE
+PLOTENABLED Y
+VARIANTNAME ""
+LAYER LAYERTYPE SPAN NAME "[Through Hole]"
+ALL_COLOURS_BLACK Y
+FILL_DRILL_HOLES Y
+FILL_UNPLATED_DRILL_HOLES Y
+BOARD N
+BOARDPLATED Y
+BOARDUNPLATED Y
+PINS Y
+PIN_NAME N
+COMBINE_PLOTS Y
+BOOKMARKS Y
+COMPONENT_DETAILS Y
+SYMBOL_DETAILS Y
+LINK_NET_NAMES Y
+BLOCK_DETAILS Y
+PUSH_INTO_BLOCK Y
+VIEW_PDF Y
+PDF_ALL_COLOURS_BLACK N
+DRILLPLATEDBOARD Y
+DRILLUNPLATEDBOARD Y
+DRILLPLATEDHOLES Y
+DRILLUNPLATEDHOLES Y
+DRILLROUNDHOLES Y
+DRILLSLOTS Y
+PANELOUTLINES N
+PANELPCBCONTENTS Y
+MIRROR N
+ROTATE N
+SCALE 1.000000
+OFFSET 0 0
+PLOT_BOUNDS_TYPE FIT_DESIGN
+PLOT_BOUNDS 1649476 3443224 3271774 1814576
+ENDPLOT
diff --git a/design/DesignSpark/schematic.pcb b/design/DesignSpark/schematic.pcb
index f957fcb..467c01c 100644
Binary files a/design/DesignSpark/schematic.pcb and b/design/DesignSpark/schematic.pcb differ
diff --git a/design/DesignSpark/schematic.sch b/design/DesignSpark/schematic.sch
index d92ee2f..efb8ffd 100644
Binary files a/design/DesignSpark/schematic.sch and b/design/DesignSpark/schematic.sch differ