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ddr processing part 2

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This commit is contained in:
steve 2023-09-27 10:23:14 +01:00
parent 66b83bc77e
commit 3b1bae0581
4 changed files with 63 additions and 44 deletions
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6
io.cpp
View File

@ -79,7 +79,7 @@ void io::down(uint8_t scan) {
void io::enter(uint8_t key) { void io::enter(uint8_t key) {
PIA::write_ca1(false); PIA::write_ca1(false);
PIA::write_porta(key + 0x80); PIA::write_porta_in(key + 0x80);
PIA::write_ca1(true); PIA::write_ca1(true);
} }
@ -141,14 +141,14 @@ void io::write_portb(uint8_t b) {
PIA::write_portb(b); PIA::write_portb(b);
} }
uint8_t io::read_porta_cr() { uint8_t io::read_cra() {
if (_loading) { if (_loading) {
if (files.more()) if (files.more())
enter(files.read()); enter(files.read());
else else
_loading = false; _loading = false;
} }
return PIA::read_porta_cr(); return PIA::read_cra();
} }
void io::checkpoint(Stream &s) { void io::checkpoint(Stream &s) {

2
io.h
View File

@ -16,7 +16,7 @@ public:
virtual void restore(Stream &); virtual void restore(Stream &);
virtual void write_portb(uint8_t); virtual void write_portb(uint8_t);
virtual uint8_t read_porta_cr(); virtual uint8_t read_cra();
void load(); void load();
filer &files; filer &files;

70
pia.cpp
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@ -29,16 +29,16 @@ void PIA::write(Memory::address a, uint8_t b) {
#endif #endif
switch(a % 4) { switch(a % 4) {
case 0: case 0:
output_selected(porta_cr)? write_porta(b): write_ddra(b); output_selected(cra)? write_porta(b): write_ddra(b);
break; break;
case 1: case 1:
write_porta_cr(b); write_cra(b);
break; break;
case 2: case 2:
output_selected(portb_cr)? write_portb(b): write_ddrb(b); output_selected(crb)? write_portb(b): write_ddrb(b);
break; break;
case 3: case 3:
write_portb_cr(b); write_crb(b);
break; break;
} }
} }
@ -51,23 +51,25 @@ uint8_t PIA::read(Memory::address a) {
#endif #endif
switch (a % 4) { switch (a % 4) {
case 0: case 0:
return output_selected(porta_cr)? read_porta(): read_ddra(); return output_selected(cra)? read_porta(): read_ddra();
case 1: case 1:
return read_porta_cr(); return read_cra();
case 2: case 2:
return output_selected(portb_cr)? read_portb(): read_ddrb(); return output_selected(crb)? read_portb(): read_ddrb();
case 3: case 3:
return read_portb_cr(); return read_crb();
} }
return 0xff; return 0xff;
} }
void PIA::checkpoint(Stream &s) { void PIA::checkpoint(Stream &s) {
s.write(portb_cr); s.write(crb);
s.write(portb); s.write(outb);
s.write(inb);
s.write(ddrb); s.write(ddrb);
s.write(porta_cr); s.write(cra);
s.write(porta); s.write(outa);
s.write(ina);
s.write(ddra); s.write(ddra);
s.write(irq_b1); s.write(irq_b1);
s.write(irq_b2); s.write(irq_b2);
@ -80,11 +82,13 @@ void PIA::checkpoint(Stream &s) {
} }
void PIA::restore(Stream &s) { void PIA::restore(Stream &s) {
portb_cr = s.read(); crb = s.read();
portb = s.read(); outb = s.read();
inb = s.read();
ddrb = s.read(); ddrb = s.read();
porta_cr = s.read(); cra = s.read();
porta = s.read(); outa = s.read();
ina = s.read();
ddra = s.read(); ddra = s.read();
irq_b1 = s.read(); irq_b1 = s.read();
irq_b2 = s.read(); irq_b2 = s.read();
@ -101,7 +105,7 @@ void PIA::write_ca1(bool state) {
if (ca1 == state) if (ca1 == state)
return; return;
if ((state && c1_low_to_high(porta_cr)) || (!state && c1_high_to_low(porta_cr))) if ((state && c1_low_to_high(cra)) || (!state && c1_high_to_low(cra)))
irq_a1 = true; irq_a1 = true;
ca1 = state; ca1 = state;
@ -109,10 +113,10 @@ void PIA::write_ca1(bool state) {
void PIA::write_ca2(bool state) { void PIA::write_ca2(bool state) {
if (ca2 == state || !c2_input(porta_cr)) if (ca2 == state || !c2_input(cra))
return; return;
if ((state && c2_low_to_high(porta_cr)) || (!state && c2_high_to_low(porta_cr))) if ((state && c2_low_to_high(cra)) || (!state && c2_high_to_low(cra)))
irq_a2 = true; irq_a2 = true;
ca2 = state; ca2 = state;
@ -123,7 +127,7 @@ void PIA::write_cb1(bool state) {
if (cb1 == state) if (cb1 == state)
return; return;
if ((state && c1_low_to_high(portb_cr)) || (!state && c1_high_to_low(portb_cr))) if ((state && c1_low_to_high(crb)) || (!state && c1_high_to_low(crb)))
irq_b1 = true; irq_b1 = true;
cb1 = state; cb1 = state;
@ -131,35 +135,45 @@ void PIA::write_cb1(bool state) {
void PIA::write_cb2(bool state) { void PIA::write_cb2(bool state) {
if (cb2 == state || !c2_input(portb_cr)) if (cb2 == state || !c2_input(crb))
return; return;
if ((state && c2_low_to_high(portb_cr)) || (!state && c2_high_to_low(portb_cr))) if ((state && c2_low_to_high(crb)) || (!state && c2_high_to_low(crb)))
irq_b2 = true; irq_b2 = true;
cb2 = state; cb2 = state;
} }
uint8_t PIA::read_porta_cr() { uint8_t PIA::read_cra() {
byte b = porta_cr; byte b = cra;
if (irq_a1) if (irq_a1)
b |= IRQ1; b |= IRQ1;
if (irq_a2 && c2_input(porta_cr)) if (irq_a2 && c2_input(cra))
b |= IRQ2; b |= IRQ2;
return b; return b;
} }
uint8_t PIA::read_portb_cr() { uint8_t PIA::read_crb() {
byte b = portb_cr; byte b = crb;
if (irq_b1) if (irq_b1)
b |= IRQ1; b |= IRQ1;
if (irq_b2 && c2_input(portb_cr)) if (irq_b2 && c2_input(crb))
b |= IRQ2; b |= IRQ2;
return b; return b;
} }
uint8_t PIA::read_porta() {
irq_a1 = irq_a2 = false;
return (ina & ~ddra) | (outa & ddra);
}
uint8_t PIA::read_portb() {
irq_b1 = irq_b2 = false;
return (inb & ~ddrb) | (outb & ddrb);
}

29
pia.h
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@ -5,23 +5,27 @@
// https://en.wikipedia.org/wiki/Peripheral_Interface_Adapter // https://en.wikipedia.org/wiki/Peripheral_Interface_Adapter
class PIA { class PIA {
public: public:
PIA(): portb(0), portb_cr(0), porta(0), porta_cr(0), ddrb(0), ddra(0), PIA(): outb(0), inb(0), crb(0), outa(0), ina(0), cra(0), ddrb(0), ddra(0),
ca1(false), ca2(false), cb1(false), cb2(false), ca1(false), ca2(false), cb1(false), cb2(false),
irq_a1(false), irq_a2(false), irq_b1(false), irq_b2(false) {} irq_a1(false), irq_a2(false), irq_b1(false), irq_b2(false) {}
virtual void reset() { virtual void reset() {
portb = portb_cr = ddrb = porta = porta_cr = ddra = 0; outb = inb = crb = ddrb = outa = ina = cra = ddra = 0;
irq_a1 = irq_a2 = irq_b1 = irq_b2 = ca1 = ca2 = cb1 = cb2 = false; irq_a1 = irq_a2 = irq_b1 = irq_b2 = ca1 = ca2 = cb1 = cb2 = false;
} }
// device memory interface
void write(Memory::address, uint8_t); void write(Memory::address, uint8_t);
uint8_t read(Memory::address); uint8_t read(Memory::address);
void checkpoint(Stream &); void checkpoint(Stream &);
void restore(Stream &); void restore(Stream &);
// device input (external) interface
void write_porta_in(uint8_t b) { ina = b; }
void write_ca1(bool); void write_ca1(bool);
void write_ca2(bool); void write_ca2(bool);
void write_portb_in(uint8_t b) { inb = b; }
void write_cb1(bool); void write_cb1(bool);
void write_cb2(bool); void write_cb2(bool);
@ -29,23 +33,24 @@ public:
static const uint8_t IRQ2 = 0x40; static const uint8_t IRQ2 = 0x40;
protected: protected:
// overrideable device memory interface
virtual uint8_t read_ddra() { return ddra; } virtual uint8_t read_ddra() { return ddra; }
virtual uint8_t read_porta() { irq_a1 = irq_a2 = false; return porta; } virtual uint8_t read_porta();
virtual uint8_t read_porta_cr(); virtual uint8_t read_cra();
virtual uint8_t read_ddrb() { return ddrb; } virtual uint8_t read_ddrb() { return ddrb; }
virtual uint8_t read_portb() { irq_b1 = irq_b2 = false; return portb; } virtual uint8_t read_portb();
virtual uint8_t read_portb_cr(); virtual uint8_t read_crb();
virtual void write_ddra(uint8_t b) { ddra = b; } virtual void write_ddra(uint8_t b) { ddra = b; }
virtual void write_porta(uint8_t b) { porta = b; } virtual void write_porta(uint8_t b) { outa = b; }
virtual void write_porta_cr(uint8_t b) { porta_cr = (b & 0x3f); } virtual void write_cra(uint8_t b) { cra = (b & 0x3f); }
virtual void write_ddrb(uint8_t b) { ddrb = b; } virtual void write_ddrb(uint8_t b) { ddrb = b; }
virtual void write_portb(uint8_t b) { portb = b; } virtual void write_portb(uint8_t b) { outb = b; }
virtual void write_portb_cr(uint8_t b) { portb_cr = (b & 0x3f); } virtual void write_crb(uint8_t b) { crb = (b & 0x3f); }
private: private:
uint8_t porta_cr, porta, ddra; uint8_t cra, ina, outa, ddra;
uint8_t portb_cr, portb, ddrb; uint8_t crb, inb, outb, ddrb;
bool ca1, ca2, irq_a1, irq_a2; bool ca1, ca2, irq_a1, irq_a2;
bool cb1, cb2, irq_b1, irq_b2; bool cb1, cb2, irq_b1, irq_b2;
}; };