implement irq_a1 and irq_b1

This commit is contained in:
steve 2023-09-26 17:01:04 +01:00
parent ba05ac5d74
commit 5e4c0867b9
4 changed files with 68 additions and 34 deletions

27
io.cpp
View File

@ -84,8 +84,9 @@ void io::down(uint8_t scan) {
}
void io::enter(uint8_t key) {
PIA::write_ca1(false);
PIA::write_porta(key + 0x80);
PIA::write_porta_cr(0xa7);
PIA::write_ca1(true);
}
void io::up(uint8_t scan) {
@ -146,36 +147,14 @@ void io::write_portb(uint8_t b) {
PIA::write_portb(b);
}
void io::write_portb_cr(uint8_t b) {
if (PIA::read_portb_cr() < 0x80)
PIA::write_portb_cr(b);
}
uint8_t io::read_porta_cr() {
uint8_t b = PIA::read_porta_cr();
if (b & 0x80) {
PIA::write_porta_cr(0);
b = 0xa7;
}
if (b != 0xa7)
return b;
if (_loading) {
if (files.more())
enter(files.read());
else
_loading = false;
}
return b;
}
void io::write_porta_cr(uint8_t b) {
uint8_t cr = PIA::read_porta_cr();
if (!(cr & 0x80) && b >= 0x80)
cr |= 0x80;
else
cr = b;
PIA::write_porta_cr(cr);
return PIA::read_porta_cr();
}
void io::checkpoint(Stream &s) {

2
io.h
View File

@ -16,9 +16,7 @@ public:
virtual void restore(Stream &);
virtual void write_portb(uint8_t);
virtual void write_portb_cr(uint8_t);
virtual uint8_t read_porta_cr();
virtual void write_porta_cr(uint8_t);
void load();
filer &files;

46
pia.cpp
View File

@ -5,6 +5,10 @@
// see: https://github.com/mamedev/mame/blob/master/src/devices/machine/6821pia.cpp
// and: https://github.com/mamedev/mame/blob/master/src/devices/machine/6821pia.h
inline bool c1_low_to_high(uint8_t cr) { return cr & 0x02; }
inline bool c1_high_to_low(uint8_t cr) { return !c1_low_to_high(cr); }
void PIA::write(Memory::address a, uint8_t b) {
#if defined(DEBUGGING)
Serial.print(millis());
@ -53,6 +57,10 @@ void PIA::checkpoint(Stream &s) {
s.write(portb);
s.write(porta_cr);
s.write(porta);
s.write(irq_b1);
s.write(irq_a1);
s.write(cb1);
s.write(ca1);
}
void PIA::restore(Stream &s) {
@ -60,4 +68,42 @@ void PIA::restore(Stream &s) {
portb = s.read();
porta_cr = s.read();
porta = s.read();
irq_b1 = s.read();
irq_a1 = s.read();
cb1 = s.read();
ca1 = s.read();
}
void PIA::write_ca1(bool state) {
if (ca1 == state)
return;
if ((state && c1_low_to_high(porta_cr)) || (!state && c1_high_to_low(porta_cr)))
irq_a1 = true;
ca1 = state;
}
void PIA::write_cb1(bool state) {
if (cb1 == state)
return;
if ((state && c1_low_to_high(portb_cr)) || (!state && c1_high_to_low(portb_cr)))
irq_b1 = true;
cb1 = state;
}
uint8_t PIA::read_porta_cr() {
if (irq_a1)
return porta_cr | IRQ1;
return porta_cr;
}
uint8_t PIA::read_portb_cr() {
if (irq_b1)
return portb_cr | IRQ1;
return portb_cr;
}

27
pia.h
View File

@ -4,8 +4,12 @@
// https://en.wikipedia.org/wiki/Peripheral_Interface_Adapter
class PIA {
public:
PIA(): portb(0), portb_cr(0), porta(0), porta_cr(0) {}
virtual void reset() { portb = portb_cr = porta = porta_cr = 0; }
PIA(): portb(0), portb_cr(0), porta(0), porta_cr(0), irq_a1(false), irq_b1(false) {}
virtual void reset() {
portb = portb_cr = porta = porta_cr = 0;
irq_a1 = irq_b1 = ca1 = cb1 = false;
}
void write(Memory::address, uint8_t);
uint8_t read(Memory::address);
@ -13,19 +17,26 @@ public:
void checkpoint(Stream &);
void restore(Stream &);
void write_ca1(bool);
void write_cb1(bool);
static const uint8_t IRQ1 = 0x80;
protected:
// "device-side" operations (called from memory interface)
virtual uint8_t read_porta() { return porta; }
virtual uint8_t read_porta_cr() { return porta_cr; }
virtual uint8_t read_portb() { return portb; }
virtual uint8_t read_portb_cr() { return portb_cr; }
virtual uint8_t read_porta() { irq_a1 = false; return porta; }
virtual uint8_t read_porta_cr();
virtual uint8_t read_portb() { irq_b1 = false; return portb; }
virtual uint8_t read_portb_cr();
virtual void write_porta(uint8_t b) { porta = b; }
virtual void write_porta_cr(uint8_t b) { porta_cr = b; }
virtual void write_porta_cr(uint8_t b) { porta_cr = (b & 0x3f); }
virtual void write_portb(uint8_t b) { portb = b; }
virtual void write_portb_cr(uint8_t b) { portb_cr = b; }
virtual void write_portb_cr(uint8_t b) { portb_cr = (b & 0x3f); }
private:
uint8_t portb_cr, portb, porta_cr, porta;
bool ca1, irq_a1;
bool cb1, irq_b1;
};
#endif