-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
-- Module  Version: 5.4
-- Thu Aug 08 18:38:02 2019

-- parameterized module component declaration
component sig2513
    port (Address: in  std_logic_vector(8 downto 0); 
        OutClock: in  std_logic; OutClockEn: in  std_logic; 
        Reset: in  std_logic; Q: out  std_logic_vector(4 downto 0));
end component;

-- parameterized module component instance
__ : sig2513
    port map (Address(8 downto 0)=>__, OutClock=>__, OutClockEn=>__, 
        Reset=>__, Q(4 downto 0)=>__);
