First code commit.
|
@ -0,0 +1,14 @@
|
|||
[General]
|
||||
showNCD=true
|
||||
showPgroups=true
|
||||
showCongestion=false
|
||||
showConnsSelect=false
|
||||
showConnsBetween=false
|
||||
showConnsOutside=true
|
||||
showLPF=false
|
||||
showREGIONs=false
|
||||
showUGROUPs=false
|
||||
showPARITIONs=true
|
||||
showLogicalConnections=false
|
||||
dontShowBBoxOverlapWarning=false
|
||||
sceneInViewRect=@Variant(\0\0\0\x14\xc0\xd6\r+\x4\xc6\xce<\xc0\xa9\x33\x9e\xe0\xe3\x34\xd6\x41\nB4\xe9\xekz@\xfb\x11 \x1cz\xc2o)
|
|
@ -0,0 +1,108 @@
|
|||
# courtesy https://github.com/VLSI-EDA/PoC/blob/master/.gitignore
|
||||
|
||||
# general file excludes
|
||||
~*.tmp
|
||||
~*.docx
|
||||
*~
|
||||
*.o
|
||||
~$*
|
||||
|
||||
# ignore Python caches
|
||||
__pycache__
|
||||
|
||||
# ignore build directories
|
||||
docs/_build/
|
||||
docs/pyIPCMI/*
|
||||
!docs/pyIPCMI/.gitempty
|
||||
!docs/pyIPCMI/.publish
|
||||
!docs/pyIPCMI/README.md
|
||||
!docs/pyIPCMI/index.rst
|
||||
|
||||
|
||||
# ignore files in netlist/
|
||||
netlist/
|
||||
!netlist/configuration.ini
|
||||
!netlist/netlist.ps1
|
||||
!netlist/netlist.sh
|
||||
!netlist/template.cgc
|
||||
|
||||
# ignore folders
|
||||
docs/_build/
|
||||
.pyIPCMI/Wrapper/Hooks/*
|
||||
!.pyIPCMI/Wrapper/Hooks/README.md
|
||||
temp/*
|
||||
!temp/.*
|
||||
!temp/*.*
|
||||
temp/precompiled/*
|
||||
!temp/precompiled/.*
|
||||
|
||||
# ignore private files from pyIPCMI
|
||||
.pyIPCMI/config.private.ini
|
||||
|
||||
# ignore private files from PoC
|
||||
tb/common/my_project.vhdl
|
||||
|
||||
|
||||
# ignore external tool files: ActiveHDL, QuestaSim
|
||||
/prj/ActiveHDL/*
|
||||
/prj/ActiveHDL/*.*
|
||||
/prj/ActiveHDL/**/*.*
|
||||
!/prj/ActiveHDL/PoC.adf
|
||||
!/prj/ActiveHDL/PoC.wsp
|
||||
|
||||
/prj/Diamond/*.*
|
||||
/prj/Diamond/*/*
|
||||
/prj/Diamond/**/*.*
|
||||
!/prj/Diamond/**/*.lpf
|
||||
!/prj/Diamond/*.ldf
|
||||
!/prj/Diamond/*.sty
|
||||
!/prj/Diamond/*.vhdl
|
||||
|
||||
/prj/QuestaSim/*
|
||||
/prj/QuestaSim/*.*
|
||||
/prj/QuestaSim/**/*.*
|
||||
!/prj/QuestaSim/PoC.mpf
|
||||
|
||||
# ignore Lattice Diamond files
|
||||
other/diamond/._Real_._Math_.vhd
|
||||
other/diamond/.spread_sheet.ini
|
||||
other/diamond/.spreadsheet_view.ini
|
||||
/other/diamond/*/**/*
|
||||
/other/diamond/*.xml
|
||||
/other/diamond/*.html
|
||||
!/other/diamond/*/**/*.lpf
|
||||
!/other/diamond/*/**/*.ldc
|
||||
!/other/diamond/*/**/*.vhdl
|
||||
|
||||
# ignore Xilinx ISE files
|
||||
/other/ise/**/*.*
|
||||
/other/ise/**/ise
|
||||
!/other/ise/**/*.xise
|
||||
!/other/ise/**/*.xpr
|
||||
!/other/ise/**/iseconfig/filter.filter
|
||||
!/other/ise/**/*.qpf
|
||||
!/other/ise/**/*.qsf
|
||||
|
||||
# ignore Quartus files
|
||||
/other/quartus/**/*.*
|
||||
/other/quartus/**/db/
|
||||
/other/quartus/**/incremental_db/
|
||||
/other/quartus/**/output_files/
|
||||
/other/quartus/**/simulation/
|
||||
/other/quartus/**/greybox_tmp/
|
||||
!/other/quartus/**/*.qpf
|
||||
!/other/quartus/**/*.qsf
|
||||
!/other/quartus/**/*.vhdl
|
||||
|
||||
#ignore Vivado files
|
||||
/other/vivado/**/*.cache
|
||||
/other/vivado/**/*.hw
|
||||
/other/vivado/**/*.runs
|
||||
/other/vivado/**/*.sim
|
||||
/other/vivado/**/*.ip_user_files
|
||||
|
||||
# general whitelist
|
||||
!.git*
|
||||
!.publish
|
||||
!README.md
|
||||
other/PrecisionRTL/
|
|
@ -0,0 +1,9 @@
|
|||
[Runmanager]
|
||||
Geometry=@ByteArray(\x1\xd9\xd0\xcb\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x1\x1c\0\0\0\xd8\0\0\0\0\0\0\0\0\xff\xff\xff\xff\xff\xff\xff\xff\0\0\0\x1\0\0)
|
||||
windowState=@ByteArray(\0\0\0\xff\0\0\0\0\xfd\0\0\0\0\0\0\0\0\0\0\0\0\0\0\0\x4\0\0\0\x4\0\0\0\b\0\0\0\b\xfc\0\0\0\x1\0\0\0\0\0\0\0\x1\xff\xff\xff\xff\x3\0\0\0\0\xff\xff\xff\xff\0\0\0\0\0\0\0\0)
|
||||
headerState=@ByteArray(\0\0\0\xff\0\0\0\0\0\0\0\x1\0\0\0\x1\0\0\0\0\x1\0\0\0\0\0\0\0\0\0\0\0\x16\0\xe0?\0\0\0\t\0\0\0\x10\0\0\0\x64\0\0\0\xf\0\0\0\x64\0\0\0\xe\0\0\0\x64\0\0\0\r\0\0\0\x64\0\0\0\x15\0\0\0\x64\0\0\0\x14\0\0\0\x64\0\0\0\x13\0\0\0\x64\0\0\0\x12\0\0\0\x64\0\0\0\x11\0\0\0\x64\0\0\x4\xd3\0\0\0\x16\x1\x1\0\x1\0\0\0\0\0\0\0\0\0\0\0\0\x64\xff\xff\xff\xff\0\0\0\x81\0\0\0\0\0\0\0\x3\0\0\0#\0\0\0\x1\0\0\0\x2\0\0\x4\xb0\0\0\0\f\0\0\0\0\0\0\0\0\0\0\0\t\0\0\0\0)
|
||||
|
||||
[impl1%3CStrategy1%3E]
|
||||
isChecked=false
|
||||
isHidden=false
|
||||
isExpanded=false
|
|
@ -0,0 +1,5 @@
|
|||
[General]
|
||||
PAR.auto_tasks=PARTrace
|
||||
Export.auto_tasks=Bitgen
|
||||
Map.auto_tasks=MapTrace
|
||||
AutoAssign=true
|
|
@ -0,0 +1,3 @@
|
|||
[General]
|
||||
COLUMN_POS_INFO_NAME_-1_0=Prioritize
|
||||
COLUMN_POS_INFO_NAME_-1_1=PIO Register
|
|
@ -0,0 +1,76 @@
|
|||
[General]
|
||||
pin_sort_type=0
|
||||
pin_sort_ascending=true
|
||||
sig_sort_type=0
|
||||
sig_sort_ascending=true
|
||||
active_Sheet=Port Assignments
|
||||
|
||||
[Port%20Assignments]
|
||||
Name="193,0"
|
||||
Group%20By="84,1"
|
||||
Pin="63,2"
|
||||
BANK="62,3"
|
||||
BANK_VCC="90,4"
|
||||
VREF="60,5"
|
||||
IO_TYPE="169,6"
|
||||
PULLMODE="97,7"
|
||||
DRIVE="67,8"
|
||||
SLEWRATE="92,9"
|
||||
CLAMP="71,10"
|
||||
OPENDRAIN="97,11"
|
||||
DIFFRESISTOR="114,12"
|
||||
DIFFDRIVE="92,13"
|
||||
HYSTERESIS="101,14"
|
||||
Outload%20%28pF%29="103,15"
|
||||
MaxSkew="87,16"
|
||||
Clock%20Load%20Only="121,17"
|
||||
SwitchingID="100,18"
|
||||
Ground%20plane%20PCB%20noise%20%28mV%29="196,19"
|
||||
Power%20plane%20PCB%20noise%20%28mV%29="190,20"
|
||||
SSO%20Allowance%28%25%29="138,21"
|
||||
sort_columns="Name,Ascending"
|
||||
|
||||
[Pin%20Assignments]
|
||||
Pin="90,0"
|
||||
Pad%20Name="89,1"
|
||||
Dual%20Function="158,2"
|
||||
Polarity="77,3"
|
||||
BANK="0,4"
|
||||
BANK_VCC="90,5"
|
||||
IO_TYPE="169,6"
|
||||
Signal%20Name="177,7"
|
||||
Signal%20Type="115,8"
|
||||
sort_columns="Pin,Ascending"
|
||||
|
||||
[Clock%20Resource]
|
||||
Clock%20Type="100,ELLIPSIS"
|
||||
Clock%20Name="100,ELLIPSIS"
|
||||
Selection="100,ELLIPSIS"
|
||||
|
||||
[Global%20Preferences]
|
||||
Preference%20Name="231,ELLIPSIS"
|
||||
Preference%20Value="236,ELLIPSIS"
|
||||
|
||||
[Cell%20Mapping]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Din\Dout="100,ELLIPSIS"
|
||||
PIO%20Register="100,ELLIPSIS"
|
||||
|
||||
[Route%20Priority]
|
||||
Type="100,ELLIPSIS"
|
||||
Name="100,ELLIPSIS"
|
||||
Prioritize="100,ELLIPSIS"
|
||||
|
||||
[Timing%20Preferences]
|
||||
Preference%20Name="182,ELLIPSIS"
|
||||
Preference%20Value="105,ELLIPSIS"
|
||||
Preference%20Unit="98,ELLIPSIS"
|
||||
|
||||
[Group]
|
||||
Group%20Type\Name="134,ELLIPSIS"
|
||||
Value="39,ELLIPSIS"
|
||||
|
||||
[Misc%20Preferences]
|
||||
Preference%20Name="117,ELLIPSIS"
|
||||
Preference%20Value="105,ELLIPSIS"
|
|
@ -0,0 +1,128 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<BaliProject version="3.2" title="Apple1Display" device="LCMXO2-7000HC-4TG144C" default_implementation="impl1">
|
||||
<Options/>
|
||||
<Implementation title="impl1" dir="impl1" description="impl1" synthesis="synplify" default_strategy="Strategy1">
|
||||
<Options def_top="CursorRam" top="FleaFPGA_Uno_E1"/>
|
||||
<Source name="impl1/source/FleaFPGA_Uno_Top.vhd" type="VHDL" type_short="VHDL" syn_sim="SynOnly">
|
||||
<Options top_module="FleaFPGA_Uno_E1"/>
|
||||
</Source>
|
||||
<Source name="impl1/Apple1Display.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="impl1/source/ntsc.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="impl1/divider.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="impl1/master_clk.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7400.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7402.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7404.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7408.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7410.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7427.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7432.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm7450.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm74157.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm74160.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm74161.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm74166.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm74174.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm74175.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/2504.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/2519.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/dm2513.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="CharacterRom.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ScreenRom.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ShiftReg40.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="tests/Apple1Display_tb.vhd" type="VHDL" type_short="VHDL" syn_sim="SimOnly">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="tests/ShiftReg40_tb.vhd" type="VHDL" type_short="VHDL" syn_sim="SimOnly">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="test_entity.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ShiftReg1024.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ScreenRom2.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ScreenRam.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="CursorRam.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="UART_RX.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="ttl/ne555.vhd" type="VHDL" type_short="VHDL">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="sig2504.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="sig2513.ipx" type="IPX_Module" type_short="IPX">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="impl1/impl1.xcf" type="Programming Project File" type_short="Programming">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="impl1/source/FleaFPGA_Uno_Top.lpf" type="Logic Preference" type_short="LPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="simulation/simulation.spf" type="Simulation Project File" type_short="SPF">
|
||||
<Options/>
|
||||
</Source>
|
||||
<Source name="test_entity.pcf" type="Power Calculator" type_short="PCF">
|
||||
<Options/>
|
||||
</Source>
|
||||
</Implementation>
|
||||
<Strategy name="Strategy1" file="Apple1Display1.sty"/>
|
||||
</BaliProject>
|
|
@ -0,0 +1,205 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<!DOCTYPE strategy>
|
||||
<Strategy version="1.0" predefined="0" description="" label="Strategy1">
|
||||
<Property name="PROP_BD_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_BD_EdfInBusNameConv" value="None" time="0"/>
|
||||
<Property name="PROP_BD_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_BD_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_BD_ParSearchPath" value="" time="0"/>
|
||||
<Property name="PROP_BIT_AddressBitGen" value="Increment" time="0"/>
|
||||
<Property name="PROP_BIT_AllowReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ByteWideBitMirror" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CapReadBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ConModBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_CreateBitFile" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisRAMResBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_DisableUESBitgen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_DonePinBitGen" value="Pullup" time="0"/>
|
||||
<Property name="PROP_BIT_DoneSigBitGen" value="4" time="0"/>
|
||||
<Property name="PROP_BIT_EnIOBitGen" value="TriStateDuringReConfig" time="0"/>
|
||||
<Property name="PROP_BIT_EnIntOscBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_ExtClockBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_GSREnableBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_GSRRelOnBitGen" value="DoneIn" time="0"/>
|
||||
<Property name="PROP_BIT_GranTimBitGen" value="0" time="0"/>
|
||||
<Property name="PROP_BIT_IOTriRelBitGen" value="Cycle 2" time="0"/>
|
||||
<Property name="PROP_BIT_JTAGEnableBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_LenBitsBitGen" value="24" time="0"/>
|
||||
<Property name="PROP_BIT_MIFFileBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_NoHeader" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen" value="Bit File (Binary)" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatBitGen_REF" value="" time="0"/>
|
||||
<Property name="PROP_BIT_OutFormatPromGen" value="Intel Hex 32-bit" time="0"/>
|
||||
<Property name="PROP_BIT_ParityCheckBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_ReadBackBitGen" value="Flash" time="0"/>
|
||||
<Property name="PROP_BIT_ReadCaptureBitGen" value="Disable" time="0"/>
|
||||
<Property name="PROP_BIT_RemZeroFramesBitGen" value="False" time="0"/>
|
||||
<Property name="PROP_BIT_RunDRCBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SearchPthBitGen" value="" time="0"/>
|
||||
<Property name="PROP_BIT_StartUpClkBitGen" value="Cclk" time="0"/>
|
||||
<Property name="PROP_BIT_SynchIOBitGen" value="True" time="0"/>
|
||||
<Property name="PROP_BIT_SysClockConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_SysConBitGen" value="Reset" time="0"/>
|
||||
<Property name="PROP_BIT_WaitStTimBitGen" value="5" time="0"/>
|
||||
<Property name="PROP_IOTIMING_AllSpeed" value="False" time="0"/>
|
||||
<Property name="PROP_LST_AllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_LST_CarryChain" value="True" time="0"/>
|
||||
<Property name="PROP_LST_CarryChainLength" value="0" time="0"/>
|
||||
<Property name="PROP_LST_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_LST_DSPStyle" value="DSP" time="0"/>
|
||||
<Property name="PROP_LST_DSPUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_DecodeUnreachableStates" value="False" time="0"/>
|
||||
<Property name="PROP_LST_DisableDistRam" value="False" time="0"/>
|
||||
<Property name="PROP_LST_EBRUtil" value="100" time="0"/>
|
||||
<Property name="PROP_LST_EdfFrequency" value="200" time="0"/>
|
||||
<Property name="PROP_LST_EdfHardtimer" value="Enable" time="0"/>
|
||||
<Property name="PROP_LST_EdfInLibPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_EdfInRemLoc" value="Off" time="0"/>
|
||||
<Property name="PROP_LST_EdfMemPath" value="" time="0"/>
|
||||
<Property name="PROP_LST_FIXGATEDCLKS" value="True" time="0"/>
|
||||
<Property name="PROP_LST_FSMEncodeStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ForceGSRInfer" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_IOInsertion" value="True" time="0"/>
|
||||
<Property name="PROP_LST_InterFileDump" value="False" time="0"/>
|
||||
<Property name="PROP_LST_LoopLimit" value="1950" time="0"/>
|
||||
<Property name="PROP_LST_MaxFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_LST_MuxStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_NumCriticalPaths" value="3" time="0"/>
|
||||
<Property name="PROP_LST_OptimizeGoal" value="Balanced" time="0"/>
|
||||
<Property name="PROP_LST_PropagatConst" value="True" time="0"/>
|
||||
<Property name="PROP_LST_RAMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_ROMStyle" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_RemoveDupRegs" value="True" time="0"/>
|
||||
<Property name="PROP_LST_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_LST_ResourceShare" value="True" time="0"/>
|
||||
<Property name="PROP_LST_UseIOReg" value="Auto" time="0"/>
|
||||
<Property name="PROP_LST_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_LST_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_MAPSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RouteEstAlogtithm" value="0" time="0"/>
|
||||
<Property name="PROP_MAPSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_MAPSTA_WordCasePaths" value="1" time="0"/>
|
||||
<Property name="PROP_MAP_GuideFileMapDes" value="" time="0"/>
|
||||
<Property name="PROP_MAP_IgnorePreErr" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MAPIORegister" value="Auto" time="0"/>
|
||||
<Property name="PROP_MAP_MAPInferGSR" value="True" time="0"/>
|
||||
<Property name="PROP_MAP_MapModArgs" value="" time="0"/>
|
||||
<Property name="PROP_MAP_OvermapDevice" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_PackLogMapDes" value="0" time="0"/>
|
||||
<Property name="PROP_MAP_RegRetiming" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SigCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_SymCrossRef" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDriven" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenNodeRep" value="False" time="0"/>
|
||||
<Property name="PROP_MAP_TimingDrivenPack" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_AnalysisOption" value="Standard Setup and Hold Analysis" time="0"/>
|
||||
<Property name="PROP_PARSTA_AutoTiming" value="True" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedConns" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_CheckUnconstrainedPaths" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_FullName" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_NumUnconstrainedPaths" value="0" time="0"/>
|
||||
<Property name="PROP_PARSTA_ReportStyle" value="Verbose Timing Report" time="0"/>
|
||||
<Property name="PROP_PARSTA_RptAsynTimLoop" value="False" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForHoldAnalysis" value="m" time="0"/>
|
||||
<Property name="PROP_PARSTA_SpeedForSetupAnalysis" value="default" time="0"/>
|
||||
<Property name="PROP_PARSTA_WordCasePaths" value="10" time="0"/>
|
||||
<Property name="PROP_PAR_CrDlyStFileParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_DisableTDParDes" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_EffortParDes" value="5" time="0"/>
|
||||
<Property name="PROP_PAR_MultiSeedSortMode" value="Worst Slack" time="0"/>
|
||||
<Property name="PROP_PAR_NewRouteParDes" value="NBR" time="0"/>
|
||||
<Property name="PROP_PAR_PARClockSkew" value="Off" time="0"/>
|
||||
<Property name="PROP_PAR_PARModArgs" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParGuideRepMatch" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_ParMatchFact" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParMultiNodeList" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParNCDGuideFile" value="" time="0"/>
|
||||
<Property name="PROP_PAR_ParRunPlaceOnly" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_PlcIterParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PlcStCostTblParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_PrefErrorOut" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RemoveDir" value="True" time="0"/>
|
||||
<Property name="PROP_PAR_RouteDlyRedParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutePassParDes" value="6" time="0"/>
|
||||
<Property name="PROP_PAR_RouteResOptParDes" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDP" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RoutingCDR" value="0" time="0"/>
|
||||
<Property name="PROP_PAR_RunParWithTrce" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_SaveBestRsltParDes" value="1" time="0"/>
|
||||
<Property name="PROP_PAR_StopZero" value="False" time="0"/>
|
||||
<Property name="PROP_PAR_parHold" value="On" time="0"/>
|
||||
<Property name="PROP_PAR_parPathBased" value="Off" time="0"/>
|
||||
<Property name="PROP_PRE_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_PRE_EdfArrayBoundsCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfAutoResOfRam" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfClockDomainCross" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfDSPAcrossHie" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfFullCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfIgnoreRamRWCol" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfMissConstraint" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfNetFanout" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfParaCase" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfReencodeFSM" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfTimingViolation" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_EdfUseSafeFSM" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_EdfVlog2001" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynComArea" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynCritcal" value="3" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFSM" value="Auto" time="0"/>
|
||||
<Property name="PROP_PRE_VSynFreq" value="200" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGSR" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynGatedClk" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynIOPad" value="False" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_PRE_VSynOutPref" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRepClkFreq" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynRetime" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTimSum" value="10" time="0"/>
|
||||
<Property name="PROP_PRE_VSynTransform" value="True" time="0"/>
|
||||
<Property name="PROP_PRE_VSyninpd" value="0" time="0"/>
|
||||
<Property name="PROP_PRE_VSynoutd" value="0" time="0"/>
|
||||
<Property name="PROP_SYN_ClockConversion" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_CmdLineArgs" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfAllowDUPMod" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArea" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfArrangeVHDLFiles" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfDefEnumEncode" value="Default" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFanout" value="1000" time="0"/>
|
||||
<Property name="PROP_SYN_EdfFrequency" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfGSR" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfInsertIO" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumCritPath" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfNumStartEnd" value="" time="0"/>
|
||||
<Property name="PROP_SYN_EdfOutNetForm" value="None" time="0"/>
|
||||
<Property name="PROP_SYN_EdfPushTirstates" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfResSharing" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfRunRetiming" value="Pipelining Only" time="0"/>
|
||||
<Property name="PROP_SYN_EdfSymFSM" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_EdfUnconsClk" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_EdfVerilogInput" value="Verilog 2001" time="0"/>
|
||||
<Property name="PROP_SYN_ExportSetting" value="No" time="0"/>
|
||||
<Property name="PROP_SYN_ResolvedMixedDrivers" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UpdateCompilePtTimData" value="False" time="0"/>
|
||||
<Property name="PROP_SYN_UseLPF" value="True" time="0"/>
|
||||
<Property name="PROP_SYN_VHDL2008" value="False" time="0"/>
|
||||
<Property name="PROP_THERMAL_DefaultFreq" value="0" time="0"/>
|
||||
<Property name="PROP_TIM_MaxDelSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_MinSpeedGrade" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_ModPreSimDes" value="" time="0"/>
|
||||
<Property name="PROP_TIM_NegStupHldTim" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenPUR" value="True" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimGenX" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TimSimHierSep" value="" time="0"/>
|
||||
<Property name="PROP_TIM_TransportModeOfPathDelay" value="False" time="0"/>
|
||||
<Property name="PROP_TIM_TrgtSpeedGrade" value="" time="0"/>
|
||||
<Property name="PROP_TIM_WriteVerboseNetlist" value="False" time="0"/>
|
||||
</Strategy>
|
|
@ -0,0 +1,439 @@
|
|||
<HTML>
|
||||
<HEAD><TITLE>Lattice TCL Log</TITLE>
|
||||
<STYLE TYPE="text/css">
|
||||
<!--
|
||||
body,pre{
font-family:'Courier New', monospace;
color: #000000;
font-size:88%;
background-color: #ffffff;
}
h1 {
font-weight: bold;
margin-top: 24px;
margin-bottom: 10px;
border-bottom: 3px solid #000; font-size: 1em;
}
h2 {
font-weight: bold;
margin-top: 18px;
margin-bottom: 5px;
font-size: 0.90em;
}
h3 {
font-weight: bold;
margin-top: 12px;
margin-bottom: 5px;
font-size: 0.80em;
}
p {
font-size:78%;
}
P.Table {
margin-top: 4px;
margin-bottom: 4px;
margin-right: 4px;
margin-left: 4px;
}
table
{
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
border-collapse: collapse;
}
th {
font-weight:bold;
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
text-align:left;
font-size:78%;
}
td {
padding: 4px;
border-width: 1px 1px 1px 1px;
border-style: solid solid solid solid;
border-color: black black black black;
vertical-align:top;
font-size:78%;
}
a {
color:#013C9A;
text-decoration:none;
}
a:visited {
color:#013C9A;
}
a:hover, a:active {
text-decoration:underline;
color:#5BAFD4;
}
.pass
{
background-color: #00ff00;
}
.fail
{
background-color: #ff0000;
}
.comment
{
font-size: 90%;
font-style: italic;
}
|
||||
-->
|
||||
</STYLE>
|
||||
</HEAD>
|
||||
<PRE><A name="pn190801151032"></A><B><U><big>pn190801151032</big></U></B>
|
||||
#Start recording tcl command: 8/1/2019 11:12:43
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/1/2019 15:10:32
|
||||
|
||||
|
||||
|
||||
<A name="pn190801174637"></A><B><U><big>pn190801174637</big></U></B>
|
||||
#Start recording tcl command: 8/1/2019 16:06:08
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/1/2019 17:46:37
|
||||
|
||||
|
||||
|
||||
<A name="pn190805082338"></A><B><U><big>pn190805082338</big></U></B>
|
||||
#Start recording tcl command: 8/4/2019 09:19:57
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_src add "C:/Dev/Apple1Display/CursorRam2.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_src remove "C:/Dev/Apple1Display/CursorRam2.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/5/2019 08:23:38
|
||||
|
||||
|
||||
|
||||
<A name="pn190805164311"></A><B><U><big>pn190805164311</big></U></B>
|
||||
#Start recording tcl command: 8/5/2019 08:27:32
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_src add -exclude "C:/Dev/Apple1Display/timing.tpf"
|
||||
prj_src enable "C:/Dev/Apple1Display/timing.tpf"
|
||||
prj_src remove "C:/Dev/Apple1Display/timing.tpf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_strgy set_value -strategy Strategy1 lse_opt_goal=Timing
|
||||
prj_strgy set "Timing"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
launch_synplify_prj impl1
|
||||
prj_strgy set "Quick"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_strgy set "Timing"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
#Stop recording: 8/5/2019 16:43:11
|
||||
|
||||
|
||||
|
||||
<A name="pn190806090120"></A><B><U><big>pn190806090120</big></U></B>
|
||||
#Start recording tcl command: 8/5/2019 17:06:17
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
launch_synplify_prj impl1
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/6/2019 09:01:20
|
||||
|
||||
|
||||
|
||||
<A name="pn190806194051"></A><B><U><big>pn190806194051</big></U></B>
|
||||
#Start recording tcl command: 8/6/2019 18:47:24
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/6/2019 19:40:51
|
||||
|
||||
|
||||
|
||||
<A name="pn190807230635"></A><B><U><big>pn190807230635</big></U></B>
|
||||
#Start recording tcl command: 8/6/2019 19:55:29
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_strgy set "Area"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_strgy set_value -strategy Strategy1 lse_opt_goal=Balanced
|
||||
prj_strgy set "Strategy1"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
launch_synplify_prj impl1
|
||||
prj_src add "C:/Dev/Apple1Display/ttl/ne555.vhd"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
launch_synplify_prj impl1
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/7/2019 23:06:35
|
||||
|
||||
|
||||
|
||||
<A name="pn190808002818"></A><B><U><big>pn190808002818</big></U></B>
|
||||
#Start recording tcl command: 8/8/2019 00:13:47
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
launch_synplify_prj impl1
|
||||
#Stop recording: 8/8/2019 00:28:18
|
||||
|
||||
|
||||
|
||||
<A name="pn190808205639"></A><B><U><big>pn190808205639</big></U></B>
|
||||
#Start recording tcl command: 8/8/2019 14:02:47
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
launch_synplify_prj impl1
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_src add "C:/Dev/Apple1Display/sig2504.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
launch_synplify_prj impl1
|
||||
launch_synplify_prj impl1
|
||||
prj_src add "C:/Dev/Apple1Display/sig2513.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
launch_synplify_prj impl1
|
||||
#Stop recording: 8/8/2019 20:56:39
|
||||
|
||||
|
||||
|
||||
<A name="pn190811123243"></A><B><U><big>pn190811123243</big></U></B>
|
||||
#Start recording tcl command: 8/11/2019 10:43:31
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
#Stop recording: 8/11/2019 12:32:43
|
||||
|
||||
|
||||
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
<BR>
|
||||
</PRE></FONT>
|
||||
</BODY>
|
||||
</HTML>
|
|
@ -0,0 +1,20 @@
|
|||
#Start recording tcl command: 8/1/2019 16:06:08
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/1/2019 17:46:37
|
|
@ -0,0 +1,48 @@
|
|||
#Start recording tcl command: 8/4/2019 09:19:57
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_src add "C:/Dev/Apple1Display/CursorRam2.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_src remove "C:/Dev/Apple1Display/CursorRam2.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/5/2019 08:23:38
|
|
@ -0,0 +1,60 @@
|
|||
#Start recording tcl command: 8/5/2019 08:27:32
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_src add -exclude "C:/Dev/Apple1Display/timing.tpf"
|
||||
prj_src enable "C:/Dev/Apple1Display/timing.tpf"
|
||||
prj_src remove "C:/Dev/Apple1Display/timing.tpf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_strgy set_value -strategy Strategy1 lse_opt_goal=Timing
|
||||
prj_strgy set "Timing"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
launch_synplify_prj impl1
|
||||
prj_strgy set "Quick"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_strgy set "Timing"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
#Stop recording: 8/5/2019 16:43:11
|
|
@ -0,0 +1,7 @@
|
|||
#Start recording tcl command: 8/5/2019 17:06:17
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
launch_synplify_prj impl1
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/6/2019 09:01:20
|
|
@ -0,0 +1,12 @@
|
|||
#Start recording tcl command: 8/6/2019 18:47:24
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/6/2019 19:40:51
|
|
@ -0,0 +1,99 @@
|
|||
#Start recording tcl command: 8/6/2019 19:55:29
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_strgy set "Area"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_strgy set_value -strategy Strategy1 lse_opt_goal=Balanced
|
||||
prj_strgy set "Strategy1"
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
launch_synplify_prj impl1
|
||||
prj_src add "C:/Dev/Apple1Display/ttl/ne555.vhd"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
launch_synplify_prj impl1
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
#Stop recording: 8/7/2019 23:06:35
|
|
@ -0,0 +1,5 @@
|
|||
#Start recording tcl command: 8/8/2019 00:13:47
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
launch_synplify_prj impl1
|
||||
#Stop recording: 8/8/2019 00:28:18
|
|
@ -0,0 +1,47 @@
|
|||
#Start recording tcl command: 8/8/2019 14:02:47
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen -forceAll
|
||||
launch_synplify_prj impl1
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_src add "C:/Dev/Apple1Display/sig2504.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
launch_synplify_prj impl1
|
||||
launch_synplify_prj impl1
|
||||
prj_src add "C:/Dev/Apple1Display/sig2513.ipx"
|
||||
prj_run Export -impl impl1 -task Bitgen
|
||||
launch_synplify_prj impl1
|
||||
#Stop recording: 8/8/2019 20:56:39
|
|
@ -0,0 +1,4 @@
|
|||
#Start recording tcl command: 8/11/2019 10:43:31
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
#Stop recording: 8/11/2019 12:32:43
|
|
@ -0,0 +1,5 @@
|
|||
#Start recording tcl command: 9/9/2019 21:33:56
|
||||
#Project Location: C:/Dev/Apple1Display; Project name: Apple1Display
|
||||
prj_project open "C:/Dev/Apple1Display/Apple1Display.ldf"
|
||||
prj_project close
|
||||
#Stop recording: 9/11/2019 07:24:15
|
|
@ -0,0 +1,432 @@
|
|||
(edif CharacterRom
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2019 8 5 13 43 51)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.10.2.115"))))
|
||||
(comment "C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n CharacterRom -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 00 -rp 1100 -addr_width 9 -data_width 5 -num_rows 512 -cascade -1 -memfile c:/dev/apple1display/docs/lut_2513.mem -memformat bin ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell CharacterRom
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename Address "Address(8:0)") 9)
|
||||
(direction INPUT))
|
||||
(port OutClock
|
||||
(direction INPUT))
|
||||
(port OutClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(4:0)") 5)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance CharacterRom_0_0_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "SYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "CharacterRom.lpc"))
|
||||
(property MEM_INIT_FILE
|
||||
(string "lut_2513.mem"))
|
||||
(property INITVAL_1F
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_1E
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_1D
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_1C
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_1B
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_1A
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_19
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_18
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_17
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_16
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_15
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_14
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_13
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_12
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_11
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_10
|
||||
(string "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000"))
|
||||
(property INITVAL_0F
|
||||
(string "0x00800008040041101C00010040040100404010000000003E0003E000000000404010100100400400"))
|
||||
(property INITVAL_0E
|
||||
(string "0x0100400800008000000000000008000080000000038020020F0221101C0001C110220E0221101C00"))
|
||||
(property INITVAL_0D
|
||||
(string "0x01008010040040103E0001C110221E0200800E0001C110020103C1003E000040203E120140600400"))
|
||||
(property INITVAL_0C
|
||||
(string "0x01C11002060040103E0003E10010060021101C0001C04008040080C0080001C11032150261101C00"))
|
||||
(property INITVAL_0B
|
||||
(string "0x0001001004004010000000800000000000000000000000001F000000000001004008000000000000"))
|
||||
(property INITVAL_0A
|
||||
(string "0x000040081F00804000000081501C0401C15008000080200201002020080000808020100200800800"))
|
||||
(property INITVAL_09
|
||||
(string "0x0000000000008040080001A1202A080281401000006130100400419030000081E00A0E0280F00800"))
|
||||
(property INITVAL_08
|
||||
(string "0x0140A03E0A03E0A0140000000000000140A014000080000804008040080000000000000000000000"))
|
||||
(property INITVAL_07
|
||||
(string "0x03E00000000000000000000000220A008000000003E03006030060303E0000001004040101000000"))
|
||||
(property INITVAL_06
|
||||
(string "0x03E18030180301803E0003E10010040040103E000080400804014110220002211014040141102200"))
|
||||
(property INITVAL_05
|
||||
(string "0x0221B02A1502211022000080A02211022110220001C1102211022110220000804008040080403E00"))
|
||||
(property INITVAL_04
|
||||
(string "0x01C110020E0201101C00022120281E0221103C0001A1202A110221101C00020100201E0221103C00"))
|
||||
(property INITVAL_03
|
||||
(string "0x01C11022110221101C0002211026150321102200022110221502A1B0220003E10020100201002000"))
|
||||
(property INITVAL_02
|
||||
(string "0x0221202818028120220001C1100201002010020001C04008040080401C00022110221F0221102200"))
|
||||
(property INITVAL_01
|
||||
(string "0x01E11026100201001E00020100201E0201003E0003E100201E0201003E0003C11022110221103C00"))
|
||||
(property INITVAL_00
|
||||
(string "0x01C11020100201101C0003C110221E0221103C000221103E110220A0080001E1002C1702A1101C00"))
|
||||
(property CSDECODE_B
|
||||
(string "0b000"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "NORMAL"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "NOREG"))
|
||||
(property REGMODE_A
|
||||
(string "NOREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "9"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "9")))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef ADB12 (instanceRef CharacterRom_0_0_0))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CSA2 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CSB1 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CSA1 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CSB0 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CSA0 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef WEB (instanceRef CharacterRom_0_0_0))
|
||||
(portRef WEA (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADA12 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB11 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB10 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB9 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB8 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB7 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB6 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB5 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB4 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB3 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB2 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADA2 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB1 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADA1 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADB0 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef ADA0 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB8 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA8 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB7 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA7 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB6 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA6 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB5 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA5 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB4 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA4 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB3 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA3 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB2 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA2 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB1 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA1 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIB0 (instanceRef CharacterRom_0_0_0))
|
||||
(portRef DIA0 (instanceRef CharacterRom_0_0_0))))
|
||||
(net dataout4
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOA4 (instanceRef CharacterRom_0_0_0))))
|
||||
(net dataout3
|
||||
(joined
|
||||
(portRef (member Q 1))
|
||||
(portRef DOA3 (instanceRef CharacterRom_0_0_0))))
|
||||
(net dataout2
|
||||
(joined
|
||||
(portRef (member Q 2))
|
||||
(portRef DOA2 (instanceRef CharacterRom_0_0_0))))
|
||||
(net dataout1
|
||||
(joined
|
||||
(portRef (member Q 3))
|
||||
(portRef DOA1 (instanceRef CharacterRom_0_0_0))))
|
||||
(net dataout0
|
||||
(joined
|
||||
(portRef (member Q 4))
|
||||
(portRef DOA0 (instanceRef CharacterRom_0_0_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef RSTB (instanceRef CharacterRom_0_0_0))
|
||||
(portRef RSTA (instanceRef CharacterRom_0_0_0))))
|
||||
(net RdClockEn
|
||||
(joined
|
||||
(portRef OutClockEn)
|
||||
(portRef OCEB (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CEB (instanceRef CharacterRom_0_0_0))
|
||||
(portRef OCEA (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CEA (instanceRef CharacterRom_0_0_0))))
|
||||
(net rdclk
|
||||
(joined
|
||||
(portRef OutClock)
|
||||
(portRef CLKB (instanceRef CharacterRom_0_0_0))
|
||||
(portRef CLKA (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr8
|
||||
(joined
|
||||
(portRef (member Address 0))
|
||||
(portRef ADA11 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr7
|
||||
(joined
|
||||
(portRef (member Address 1))
|
||||
(portRef ADA10 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr6
|
||||
(joined
|
||||
(portRef (member Address 2))
|
||||
(portRef ADA9 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr5
|
||||
(joined
|
||||
(portRef (member Address 3))
|
||||
(portRef ADA8 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr4
|
||||
(joined
|
||||
(portRef (member Address 4))
|
||||
(portRef ADA7 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr3
|
||||
(joined
|
||||
(portRef (member Address 5))
|
||||
(portRef ADA6 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr2
|
||||
(joined
|
||||
(portRef (member Address 6))
|
||||
(portRef ADA5 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr1
|
||||
(joined
|
||||
(portRef (member Address 7))
|
||||
(portRef ADA4 (instanceRef CharacterRom_0_0_0))))
|
||||
(net raddr0
|
||||
(joined
|
||||
(portRef (member Address 8))
|
||||
(portRef ADA3 (instanceRef CharacterRom_0_0_0))))))))
|
||||
(design CharacterRom
|
||||
(cellRef CharacterRom
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
|
@ -0,0 +1,11 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="CharacterRom" module="CharacterRom" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2019 08 05 13:43:53.728" version="5.4" type="Module" synthesis="synplify" source_format="VHDL">
|
||||
<Package>
|
||||
<File name="" type="" modified="2019 08 05 13:43:53.520"/>
|
||||
<File name="CharacterRom.lpc" type="lpc" modified="2019 08 05 13:43:51.687"/>
|
||||
<File name="CharacterRom.vhd" type="top_level_vhdl" modified="2019 08 05 13:43:51.824"/>
|
||||
<File name="CharacterRom_tmpl.vhd" type="template_vhdl" modified="2019 08 05 13:43:51.839"/>
|
||||
<File name="c:/dev/apple1display/docs/lut_2513.mem" type="mem" modified="2019 07 13 15:34:01.017"/>
|
||||
<File name="tb_CharacterRom_tmpl.vhd" type="testbench_vhdl" modified="2019 08 05 13:43:51.870"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
|
@ -0,0 +1,7 @@
|
|||
MODULE CharacterRom DEFIN CharacterRom.vhd
|
||||
SUBMODULE DP8KC
|
||||
INSTANCE CharacterRom_0_0_0
|
||||
SUBMODULE VLO
|
||||
INSTANCE scuba_vlo_inst
|
||||
SUBMODULE VHI
|
||||
INSTANCE scuba_vhi_inst
|
|
@ -0,0 +1,51 @@
|
|||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-7000HC
|
||||
PartName=LCMXO2-7000HC-4TG144C
|
||||
SpeedGrade=4
|
||||
Package=TQFP144
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=ROM
|
||||
CoreRevision=5.4
|
||||
ModuleName=CharacterRom
|
||||
SourceFormat=VHDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=08/05/2019
|
||||
Time=13:43:51
|
||||
|
||||
[Parameters]
|
||||
Verilog=0
|
||||
VHDL=1
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
Address=512
|
||||
Data=5
|
||||
enByte=0
|
||||
ByteSize=9
|
||||
OutputEn=0
|
||||
ClockEn=0
|
||||
Optimization=Speed
|
||||
Reset=Sync
|
||||
Reset1=Sync
|
||||
Init=0
|
||||
MemFile=c:/dev/apple1display/docs/lut_2513.mem
|
||||
MemFormat=bin
|
||||
EnECC=0
|
||||
Pipeline=0
|
||||
Write=Normal
|
||||
init_data=0
|
||||
|
||||
[FilesGenerated]
|
||||
c:/dev/apple1display/docs/lut_2513.mem=mem
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n CharacterRom -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-7000HC -addr_width 9 -data_width 5 -num_words 512 -cascade -1 -memfile "c:/dev/apple1display/docs/lut_2513.mem" -memformat bin
|
|
@ -0,0 +1,17 @@
|
|||
Address[8] i
|
||||
Address[7] i
|
||||
Address[6] i
|
||||
Address[5] i
|
||||
Address[4] i
|
||||
Address[3] i
|
||||
Address[2] i
|
||||
Address[1] i
|
||||
Address[0] i
|
||||
OutClock i
|
||||
OutClockEn i
|
||||
Reset i
|
||||
Q[4] o
|
||||
Q[3] o
|
||||
Q[2] o
|
||||
Q[1] o
|
||||
Q[0] o
|
|
@ -0,0 +1 @@
|
|||
CharacterRom.vhd
|
|
@ -0,0 +1,29 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.10.2.115
|
||||
Mon Aug 05 13:43:51 2019
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n CharacterRom -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type romblk -device LCMXO2-7000HC -addr_width 9 -data_width 5 -num_words 512 -cascade -1 -memfile c:/dev/apple1display/docs/lut_2513.mem -memformat bin
|
||||
Circuit name : CharacterRom
|
||||
Module type : EBR_ROM
|
||||
Module Version : 5.4
|
||||
Ports :
|
||||
Inputs : Address[8:0], OutClock, OutClockEn, Reset
|
||||
Outputs : Q[4:0]
|
||||
I/O buffer : not inserted
|
||||
Memory file : c:/dev/apple1display/docs/lut_2513.mem
|
||||
EDIF output : CharacterRom.edn
|
||||
VHDL output : CharacterRom.vhd
|
||||
VHDL template : CharacterRom_tmpl.vhd
|
||||
VHDL testbench : tb_CharacterRom_tmpl.vhd
|
||||
VHDL purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : CharacterRom.srp
|
||||
Element Usage :
|
||||
DP8KC : 1
|
||||
Estimated Resource Usage:
|
||||
EBR : 1
|
|
@ -0,0 +1,187 @@
|
|||
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.2.115
|
||||
-- Module Version: 5.4
|
||||
--C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n CharacterRom -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type bram -wp 00 -rp 1100 -addr_width 9 -data_width 5 -num_rows 512 -cascade -1 -memfile c:/dev/apple1display/docs/lut_2513.mem -memformat bin
|
||||
|
||||
-- Mon Aug 05 13:43:51 2019
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- synopsys translate_off
|
||||
library MACHXO2;
|
||||
use MACHXO2.components.all;
|
||||
-- synopsys translate_on
|
||||
|
||||
entity CharacterRom is
|
||||
port (
|
||||
Address: in std_logic_vector(8 downto 0);
|
||||
OutClock: in std_logic;
|
||||
OutClockEn: in std_logic;
|
||||
Reset: in std_logic;
|
||||
Q: out std_logic_vector(4 downto 0));
|
||||
end CharacterRom;
|
||||
|
||||
architecture Structure of CharacterRom is
|
||||
|
||||
-- internal signal declarations
|
||||
signal scuba_vhi: std_logic;
|
||||
signal scuba_vlo: std_logic;
|
||||
|
||||
-- local component declarations
|
||||
component VHI
|
||||
port (Z: out std_logic);
|
||||
end component;
|
||||
component VLO
|
||||
port (Z: out std_logic);
|
||||
end component;
|
||||
component DP8KC
|
||||
generic (INIT_DATA : in String; INITVAL_1F : in String;
|
||||
INITVAL_1E : in String; INITVAL_1D : in String;
|
||||
INITVAL_1C : in String; INITVAL_1B : in String;
|
||||
INITVAL_1A : in String; INITVAL_19 : in String;
|
||||
INITVAL_18 : in String; INITVAL_17 : in String;
|
||||
INITVAL_16 : in String; INITVAL_15 : in String;
|
||||
INITVAL_14 : in String; INITVAL_13 : in String;
|
||||
INITVAL_12 : in String; INITVAL_11 : in String;
|
||||
INITVAL_10 : in String; INITVAL_0F : in String;
|
||||
INITVAL_0E : in String; INITVAL_0D : in String;
|
||||
INITVAL_0C : in String; INITVAL_0B : in String;
|
||||
INITVAL_0A : in String; INITVAL_09 : in String;
|
||||
INITVAL_08 : in String; INITVAL_07 : in String;
|
||||
INITVAL_06 : in String; INITVAL_05 : in String;
|
||||
INITVAL_04 : in String; INITVAL_03 : in String;
|
||||
INITVAL_02 : in String; INITVAL_01 : in String;
|
||||
INITVAL_00 : in String; ASYNC_RESET_RELEASE : in String;
|
||||
RESETMODE : in String; GSR : in String;
|
||||
WRITEMODE_B : in String; WRITEMODE_A : in String;
|
||||
CSDECODE_B : in String; CSDECODE_A : in String;
|
||||
REGMODE_B : in String; REGMODE_A : in String;
|
||||
DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
|
||||
port (DIA8: in std_logic; DIA7: in std_logic;
|
||||
DIA6: in std_logic; DIA5: in std_logic;
|
||||
DIA4: in std_logic; DIA3: in std_logic;
|
||||
DIA2: in std_logic; DIA1: in std_logic;
|
||||
DIA0: in std_logic; ADA12: in std_logic;
|
||||
ADA11: in std_logic; ADA10: in std_logic;
|
||||
ADA9: in std_logic; ADA8: in std_logic;
|
||||
ADA7: in std_logic; ADA6: in std_logic;
|
||||
ADA5: in std_logic; ADA4: in std_logic;
|
||||
ADA3: in std_logic; ADA2: in std_logic;
|
||||
ADA1: in std_logic; ADA0: in std_logic; CEA: in std_logic;
|
||||
OCEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
|
||||
CSA2: in std_logic; CSA1: in std_logic;
|
||||
CSA0: in std_logic; RSTA: in std_logic;
|
||||
DIB8: in std_logic; DIB7: in std_logic;
|
||||
DIB6: in std_logic; DIB5: in std_logic;
|
||||
DIB4: in std_logic; DIB3: in std_logic;
|
||||
DIB2: in std_logic; DIB1: in std_logic;
|
||||
DIB0: in std_logic; ADB12: in std_logic;
|
||||
ADB11: in std_logic; ADB10: in std_logic;
|
||||
ADB9: in std_logic; ADB8: in std_logic;
|
||||
ADB7: in std_logic; ADB6: in std_logic;
|
||||
ADB5: in std_logic; ADB4: in std_logic;
|
||||
ADB3: in std_logic; ADB2: in std_logic;
|
||||
ADB1: in std_logic; ADB0: in std_logic; CEB: in std_logic;
|
||||
OCEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
|
||||
CSB2: in std_logic; CSB1: in std_logic;
|
||||
CSB0: in std_logic; RSTB: in std_logic;
|
||||
DOA8: out std_logic; DOA7: out std_logic;
|
||||
DOA6: out std_logic; DOA5: out std_logic;
|
||||
DOA4: out std_logic; DOA3: out std_logic;
|
||||
DOA2: out std_logic; DOA1: out std_logic;
|
||||
DOA0: out std_logic; DOB8: out std_logic;
|
||||
DOB7: out std_logic; DOB6: out std_logic;
|
||||
DOB5: out std_logic; DOB4: out std_logic;
|
||||
DOB3: out std_logic; DOB2: out std_logic;
|
||||
DOB1: out std_logic; DOB0: out std_logic);
|
||||
end component;
|
||||
attribute MEM_LPC_FILE : string;
|
||||
attribute MEM_INIT_FILE : string;
|
||||
attribute MEM_LPC_FILE of CharacterRom_0_0_0 : label is "CharacterRom.lpc";
|
||||
attribute MEM_INIT_FILE of CharacterRom_0_0_0 : label is "lut_2513.mem";
|
||||
attribute NGD_DRC_MASK : integer;
|
||||
attribute NGD_DRC_MASK of Structure : architecture is 1;
|
||||
|
||||
begin
|
||||
-- component instantiation statements
|
||||
scuba_vhi_inst: VHI
|
||||
port map (Z=>scuba_vhi);
|
||||
|
||||
scuba_vlo_inst: VLO
|
||||
port map (Z=>scuba_vlo);
|
||||
|
||||
CharacterRom_0_0_0: DP8KC
|
||||
generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
|
||||
INITVAL_1F=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_1E=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_1D=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_1C=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_1B=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_1A=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_19=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_18=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_17=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_16=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_15=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_14=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_13=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_12=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_11=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_10=> "0x00000000000000000000000000000000000000000000000000000000000000000000000000000000",
|
||||
INITVAL_0F=> "0x00800008040041101C00010040040100404010000000003E0003E000000000404010100100400400",
|
||||
INITVAL_0E=> "0x0100400800008000000000000008000080000000038020020F0221101C0001C110220E0221101C00",
|
||||
INITVAL_0D=> "0x01008010040040103E0001C110221E0200800E0001C110020103C1003E000040203E120140600400",
|
||||
INITVAL_0C=> "0x01C11002060040103E0003E10010060021101C0001C04008040080C0080001C11032150261101C00",
|
||||
INITVAL_0B=> "0x0001001004004010000000800000000000000000000000001F000000000001004008000000000000",
|
||||
INITVAL_0A=> "0x000040081F00804000000081501C0401C15008000080200201002020080000808020100200800800",
|
||||
INITVAL_09=> "0x0000000000008040080001A1202A080281401000006130100400419030000081E00A0E0280F00800",
|
||||
INITVAL_08=> "0x0140A03E0A03E0A0140000000000000140A014000080000804008040080000000000000000000000",
|
||||
INITVAL_07=> "0x03E00000000000000000000000220A008000000003E03006030060303E0000001004040101000000",
|
||||
INITVAL_06=> "0x03E18030180301803E0003E10010040040103E000080400804014110220002211014040141102200",
|
||||
INITVAL_05=> "0x0221B02A1502211022000080A02211022110220001C1102211022110220000804008040080403E00",
|
||||
INITVAL_04=> "0x01C110020E0201101C00022120281E0221103C0001A1202A110221101C00020100201E0221103C00",
|
||||
INITVAL_03=> "0x01C11022110221101C0002211026150321102200022110221502A1B0220003E10020100201002000",
|
||||
INITVAL_02=> "0x0221202818028120220001C1100201002010020001C04008040080401C00022110221F0221102200",
|
||||
INITVAL_01=> "0x01E11026100201001E00020100201E0201003E0003E100201E0201003E0003C11022110221103C00",
|
||||
INITVAL_00=> "0x01C11020100201101C0003C110221E0221103C000221103E110220A0080001E1002C1702A1101C00",
|
||||
CSDECODE_B=> "0b000", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
|
||||
WRITEMODE_A=> "NORMAL", GSR=> "ENABLED", RESETMODE=> "ASYNC",
|
||||
REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 9,
|
||||
DATA_WIDTH_A=> 9)
|
||||
port map (DIA8=>scuba_vlo, DIA7=>scuba_vlo, DIA6=>scuba_vlo,
|
||||
DIA5=>scuba_vlo, DIA4=>scuba_vlo, DIA3=>scuba_vlo,
|
||||
DIA2=>scuba_vlo, DIA1=>scuba_vlo, DIA0=>scuba_vlo,
|
||||
ADA12=>scuba_vlo, ADA11=>Address(8), ADA10=>Address(7),
|
||||
ADA9=>Address(6), ADA8=>Address(5), ADA7=>Address(4),
|
||||
ADA6=>Address(3), ADA5=>Address(2), ADA4=>Address(1),
|
||||
ADA3=>Address(0), ADA2=>scuba_vlo, ADA1=>scuba_vlo,
|
||||
ADA0=>scuba_vlo, CEA=>OutClockEn, OCEA=>OutClockEn,
|
||||
CLKA=>OutClock, WEA=>scuba_vlo, CSA2=>scuba_vlo,
|
||||
CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset,
|
||||
DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
|
||||
DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
|
||||
DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
|
||||
ADB12=>scuba_vhi, ADB11=>scuba_vlo, ADB10=>scuba_vlo,
|
||||
ADB9=>scuba_vlo, ADB8=>scuba_vlo, ADB7=>scuba_vlo,
|
||||
ADB6=>scuba_vlo, ADB5=>scuba_vlo, ADB4=>scuba_vlo,
|
||||
ADB3=>scuba_vlo, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
|
||||
ADB0=>scuba_vlo, CEB=>OutClockEn, OCEB=>OutClockEn,
|
||||
CLKB=>OutClock, WEB=>scuba_vlo, CSB2=>scuba_vlo,
|
||||
CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>Reset, DOA8=>open,
|
||||
DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>Q(4), DOA3=>Q(3),
|
||||
DOA2=>Q(2), DOA1=>Q(1), DOA0=>Q(0), DOB8=>open, DOB7=>open,
|
||||
DOB6=>open, DOB5=>open, DOB4=>open, DOB3=>open, DOB2=>open,
|
||||
DOB1=>open, DOB0=>open);
|
||||
|
||||
end Structure;
|
||||
|
||||
-- synopsys translate_off
|
||||
library MACHXO2;
|
||||
configuration Structure_CON of CharacterRom is
|
||||
for Structure
|
||||
for all:VHI use entity MACHXO2.VHI(V); end for;
|
||||
for all:VLO use entity MACHXO2.VLO(V); end for;
|
||||
for all:DP8KC use entity MACHXO2.DP8KC(V); end for;
|
||||
end for;
|
||||
end Structure_CON;
|
||||
|
||||
-- synopsys translate_on
|
|
@ -0,0 +1,15 @@
|
|||
-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
|
||||
-- Module Version: 5.4
|
||||
-- Mon Aug 05 13:43:51 2019
|
||||
|
||||
-- parameterized module component declaration
|
||||
component CharacterRom
|
||||
port (Address: in std_logic_vector(8 downto 0);
|
||||
OutClock: in std_logic; OutClockEn: in std_logic;
|
||||
Reset: in std_logic; Q: out std_logic_vector(4 downto 0));
|
||||
end component;
|
||||
|
||||
-- parameterized module component instance
|
||||
__ : CharacterRom
|
||||
port map (Address(8 downto 0)=>__, OutClock=>__, OutClockEn=>__,
|
||||
Reset=>__, Q(4 downto 0)=>__);
|
|
@ -0,0 +1,692 @@
|
|||
(edif CursorRam
|
||||
(edifVersion 2 0 0)
|
||||
(edifLevel 0)
|
||||
(keywordMap (keywordLevel 0))
|
||||
(status
|
||||
(written
|
||||
(timestamp 2019 8 8 17 25 26)
|
||||
(program "SCUBA" (version "Diamond (64-bit) 3.10.2.115"))))
|
||||
(comment "C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n CursorRam -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 1 -depth 1024 -mode 8 ")
|
||||
(library ORCLIB
|
||||
(edifLevel 0)
|
||||
(technology
|
||||
(numberDefinition))
|
||||
(cell CU2
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port CI
|
||||
(direction INPUT))
|
||||
(port PC0
|
||||
(direction INPUT))
|
||||
(port PC1
|
||||
(direction INPUT))
|
||||
(port CO
|
||||
(direction OUTPUT))
|
||||
(port NC0
|
||||
(direction OUTPUT))
|
||||
(port NC1
|
||||
(direction OUTPUT)))))
|
||||
(cell FADD2B
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port A0
|
||||
(direction INPUT))
|
||||
(port A1
|
||||
(direction INPUT))
|
||||
(port B0
|
||||
(direction INPUT))
|
||||
(port B1
|
||||
(direction INPUT))
|
||||
(port CI
|
||||
(direction INPUT))
|
||||
(port COUT
|
||||
(direction OUTPUT))
|
||||
(port S0
|
||||
(direction OUTPUT))
|
||||
(port S1
|
||||
(direction OUTPUT)))))
|
||||
(cell FD1P3IX
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port D
|
||||
(direction INPUT))
|
||||
(port SP
|
||||
(direction INPUT))
|
||||
(port CK
|
||||
(direction INPUT))
|
||||
(port CD
|
||||
(direction INPUT))
|
||||
(port Q
|
||||
(direction OUTPUT)))))
|
||||
(cell INV
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port A
|
||||
(direction INPUT))
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell OR2
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port A
|
||||
(direction INPUT))
|
||||
(port B
|
||||
(direction INPUT))
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell ROM16X1A
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port AD3
|
||||
(direction INPUT))
|
||||
(port AD2
|
||||
(direction INPUT))
|
||||
(port AD1
|
||||
(direction INPUT))
|
||||
(port AD0
|
||||
(direction INPUT))
|
||||
(port DO0
|
||||
(direction OUTPUT)))))
|
||||
(cell VHI
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell VLO
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port Z
|
||||
(direction OUTPUT)))))
|
||||
(cell DP8KC
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port DIA8
|
||||
(direction INPUT))
|
||||
(port DIA7
|
||||
(direction INPUT))
|
||||
(port DIA6
|
||||
(direction INPUT))
|
||||
(port DIA5
|
||||
(direction INPUT))
|
||||
(port DIA4
|
||||
(direction INPUT))
|
||||
(port DIA3
|
||||
(direction INPUT))
|
||||
(port DIA2
|
||||
(direction INPUT))
|
||||
(port DIA1
|
||||
(direction INPUT))
|
||||
(port DIA0
|
||||
(direction INPUT))
|
||||
(port ADA12
|
||||
(direction INPUT))
|
||||
(port ADA11
|
||||
(direction INPUT))
|
||||
(port ADA10
|
||||
(direction INPUT))
|
||||
(port ADA9
|
||||
(direction INPUT))
|
||||
(port ADA8
|
||||
(direction INPUT))
|
||||
(port ADA7
|
||||
(direction INPUT))
|
||||
(port ADA6
|
||||
(direction INPUT))
|
||||
(port ADA5
|
||||
(direction INPUT))
|
||||
(port ADA4
|
||||
(direction INPUT))
|
||||
(port ADA3
|
||||
(direction INPUT))
|
||||
(port ADA2
|
||||
(direction INPUT))
|
||||
(port ADA1
|
||||
(direction INPUT))
|
||||
(port ADA0
|
||||
(direction INPUT))
|
||||
(port CEA
|
||||
(direction INPUT))
|
||||
(port OCEA
|
||||
(direction INPUT))
|
||||
(port CLKA
|
||||
(direction INPUT))
|
||||
(port WEA
|
||||
(direction INPUT))
|
||||
(port CSA2
|
||||
(direction INPUT))
|
||||
(port CSA1
|
||||
(direction INPUT))
|
||||
(port CSA0
|
||||
(direction INPUT))
|
||||
(port RSTA
|
||||
(direction INPUT))
|
||||
(port DIB8
|
||||
(direction INPUT))
|
||||
(port DIB7
|
||||
(direction INPUT))
|
||||
(port DIB6
|
||||
(direction INPUT))
|
||||
(port DIB5
|
||||
(direction INPUT))
|
||||
(port DIB4
|
||||
(direction INPUT))
|
||||
(port DIB3
|
||||
(direction INPUT))
|
||||
(port DIB2
|
||||
(direction INPUT))
|
||||
(port DIB1
|
||||
(direction INPUT))
|
||||
(port DIB0
|
||||
(direction INPUT))
|
||||
(port ADB12
|
||||
(direction INPUT))
|
||||
(port ADB11
|
||||
(direction INPUT))
|
||||
(port ADB10
|
||||
(direction INPUT))
|
||||
(port ADB9
|
||||
(direction INPUT))
|
||||
(port ADB8
|
||||
(direction INPUT))
|
||||
(port ADB7
|
||||
(direction INPUT))
|
||||
(port ADB6
|
||||
(direction INPUT))
|
||||
(port ADB5
|
||||
(direction INPUT))
|
||||
(port ADB4
|
||||
(direction INPUT))
|
||||
(port ADB3
|
||||
(direction INPUT))
|
||||
(port ADB2
|
||||
(direction INPUT))
|
||||
(port ADB1
|
||||
(direction INPUT))
|
||||
(port ADB0
|
||||
(direction INPUT))
|
||||
(port CEB
|
||||
(direction INPUT))
|
||||
(port OCEB
|
||||
(direction INPUT))
|
||||
(port CLKB
|
||||
(direction INPUT))
|
||||
(port WEB
|
||||
(direction INPUT))
|
||||
(port CSB2
|
||||
(direction INPUT))
|
||||
(port CSB1
|
||||
(direction INPUT))
|
||||
(port CSB0
|
||||
(direction INPUT))
|
||||
(port RSTB
|
||||
(direction INPUT))
|
||||
(port DOA8
|
||||
(direction OUTPUT))
|
||||
(port DOA7
|
||||
(direction OUTPUT))
|
||||
(port DOA6
|
||||
(direction OUTPUT))
|
||||
(port DOA5
|
||||
(direction OUTPUT))
|
||||
(port DOA4
|
||||
(direction OUTPUT))
|
||||
(port DOA3
|
||||
(direction OUTPUT))
|
||||
(port DOA2
|
||||
(direction OUTPUT))
|
||||
(port DOA1
|
||||
(direction OUTPUT))
|
||||
(port DOA0
|
||||
(direction OUTPUT))
|
||||
(port DOB8
|
||||
(direction OUTPUT))
|
||||
(port DOB7
|
||||
(direction OUTPUT))
|
||||
(port DOB6
|
||||
(direction OUTPUT))
|
||||
(port DOB5
|
||||
(direction OUTPUT))
|
||||
(port DOB4
|
||||
(direction OUTPUT))
|
||||
(port DOB3
|
||||
(direction OUTPUT))
|
||||
(port DOB2
|
||||
(direction OUTPUT))
|
||||
(port DOB1
|
||||
(direction OUTPUT))
|
||||
(port DOB0
|
||||
(direction OUTPUT)))))
|
||||
(cell CursorRam
|
||||
(cellType GENERIC)
|
||||
(view view1
|
||||
(viewType NETLIST)
|
||||
(interface
|
||||
(port (array (rename Din "Din(0:0)") 1)
|
||||
(direction INPUT))
|
||||
(port Clock
|
||||
(direction INPUT))
|
||||
(port ClockEn
|
||||
(direction INPUT))
|
||||
(port Reset
|
||||
(direction INPUT))
|
||||
(port (array (rename Q "Q(0:0)") 1)
|
||||
(direction OUTPUT)))
|
||||
(property NGD_DRC_MASK (integer 1))
|
||||
(contents
|
||||
(instance INV_1
|
||||
(viewRef view1
|
||||
(cellRef INV)))
|
||||
(instance LUT4_3
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance LUT4_2
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance LUT4_1
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance LUT4_0
|
||||
(viewRef view1
|
||||
(cellRef ROM16X1A))
|
||||
(property initval
|
||||
(string "0x8000")))
|
||||
(instance OR2_t0
|
||||
(viewRef view1
|
||||
(cellRef OR2)))
|
||||
(instance INV_0
|
||||
(viewRef view1
|
||||
(cellRef INV)))
|
||||
(instance sram_1_0_0_0
|
||||
(viewRef view1
|
||||
(cellRef DP8KC))
|
||||
(property INIT_DATA
|
||||
(string "STATIC"))
|
||||
(property ASYNC_RESET_RELEASE
|
||||
(string "SYNC"))
|
||||
(property MEM_LPC_FILE
|
||||
(string "CursorRam.lpc"))
|
||||
(property MEM_INIT_FILE
|
||||
(string ""))
|
||||
(property CSDECODE_B
|
||||
(string "0b111"))
|
||||
(property CSDECODE_A
|
||||
(string "0b000"))
|
||||
(property WRITEMODE_B
|
||||
(string "NORMAL"))
|
||||
(property WRITEMODE_A
|
||||
(string "READBEFOREWRITE"))
|
||||
(property GSR
|
||||
(string "ENABLED"))
|
||||
(property RESETMODE
|
||||
(string "ASYNC"))
|
||||
(property REGMODE_B
|
||||
(string "NOREG"))
|
||||
(property REGMODE_A
|
||||
(string "NOREG"))
|
||||
(property DATA_WIDTH_B
|
||||
(string "1"))
|
||||
(property DATA_WIDTH_A
|
||||
(string "1")))
|
||||
(instance FF_9
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_8
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_7
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_6
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_5
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_4
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_3
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_2
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_1
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance FF_0
|
||||
(viewRef view1
|
||||
(cellRef FD1P3IX))
|
||||
(property GSR
|
||||
(string "ENABLED")))
|
||||
(instance scuba_vlo_inst
|
||||
(viewRef view1
|
||||
(cellRef VLO)))
|
||||
(instance scuba_vhi_inst
|
||||
(viewRef view1
|
||||
(cellRef VHI)))
|
||||
(instance sreg_0_ctr_1_cia
|
||||
(viewRef view1
|
||||
(cellRef FADD2B)))
|
||||
(instance sreg_0_ctr_1_0
|
||||
(viewRef view1
|
||||
(cellRef CU2)))
|
||||
(instance sreg_0_ctr_1_1
|
||||
(viewRef view1
|
||||
(cellRef CU2)))
|
||||
(instance sreg_0_ctr_1_2
|
||||
(viewRef view1
|
||||
(cellRef CU2)))
|
||||
(instance sreg_0_ctr_1_3
|
||||
(viewRef view1
|
||||
(cellRef CU2)))
|
||||
(instance sreg_0_ctr_1_4
|
||||
(viewRef view1
|
||||
(cellRef CU2)))
|
||||
(net shreg_addr_w0_inv
|
||||
(joined
|
||||
(portRef AD3 (instanceRef LUT4_3))
|
||||
(portRef Z (instanceRef INV_1))))
|
||||
(net func_and_inet_2
|
||||
(joined
|
||||
(portRef AD1 (instanceRef LUT4_0))
|
||||
(portRef DO0 (instanceRef LUT4_1))))
|
||||
(net func_and_inet_1
|
||||
(joined
|
||||
(portRef AD2 (instanceRef LUT4_0))
|
||||
(portRef DO0 (instanceRef LUT4_2))))
|
||||
(net func_and_inet
|
||||
(joined
|
||||
(portRef AD3 (instanceRef LUT4_0))
|
||||
(portRef DO0 (instanceRef LUT4_3))))
|
||||
(net dec0_r2046
|
||||
(joined
|
||||
(portRef B (instanceRef OR2_t0))
|
||||
(portRef DO0 (instanceRef LUT4_0))))
|
||||
(net Reset_inv
|
||||
(joined
|
||||
(portRef WEA (instanceRef sram_1_0_0_0))
|
||||
(portRef Z (instanceRef INV_0))))
|
||||
(net srrst_ctr
|
||||
(joined
|
||||
(portRef CD (instanceRef FF_0))
|
||||
(portRef Z (instanceRef OR2_t0))
|
||||
(portRef CD (instanceRef FF_9))
|
||||
(portRef CD (instanceRef FF_8))
|
||||
(portRef CD (instanceRef FF_7))
|
||||
(portRef CD (instanceRef FF_6))
|
||||
(portRef CD (instanceRef FF_5))
|
||||
(portRef CD (instanceRef FF_4))
|
||||
(portRef CD (instanceRef FF_3))
|
||||
(portRef CD (instanceRef FF_2))
|
||||
(portRef CD (instanceRef FF_1))))
|
||||
(net scuba_vlo
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vlo_inst))
|
||||
(portRef CSB2 (instanceRef sram_1_0_0_0))
|
||||
(portRef CSA2 (instanceRef sram_1_0_0_0))
|
||||
(portRef CSB1 (instanceRef sram_1_0_0_0))
|
||||
(portRef CSA1 (instanceRef sram_1_0_0_0))
|
||||
(portRef CSB0 (instanceRef sram_1_0_0_0))
|
||||
(portRef CSA0 (instanceRef sram_1_0_0_0))
|
||||
(portRef RSTB (instanceRef sram_1_0_0_0))
|
||||
(portRef WEB (instanceRef sram_1_0_0_0))
|
||||
(portRef CLKB (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB12 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADA12 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB11 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADA11 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB10 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADA10 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB9 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB8 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB7 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB6 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB5 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB4 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB3 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB2 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB1 (instanceRef sram_1_0_0_0))
|
||||
(portRef ADB0 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB8 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA8 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB7 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA7 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB6 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA6 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB5 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA5 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB4 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA4 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB3 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA3 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB2 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA2 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB1 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIB0 (instanceRef sram_1_0_0_0))
|
||||
(portRef DIA0 (instanceRef sram_1_0_0_0))
|
||||
(portRef CI (instanceRef sreg_0_ctr_1_cia))
|
||||
(portRef B0 (instanceRef sreg_0_ctr_1_cia))
|
||||
(portRef A0 (instanceRef sreg_0_ctr_1_cia))))
|
||||
(net scuba_vhi
|
||||
(joined
|
||||
(portRef Z (instanceRef scuba_vhi_inst))
|
||||
(portRef AD0 (instanceRef LUT4_1))
|
||||
(portRef AD0 (instanceRef LUT4_0))
|
||||
(portRef OCEB (instanceRef sram_1_0_0_0))
|
||||
(portRef CEB (instanceRef sram_1_0_0_0))
|
||||
(portRef B1 (instanceRef sreg_0_ctr_1_cia))
|
||||
(portRef A1 (instanceRef sreg_0_ctr_1_cia))))
|
||||
(net ishreg_addr_w0
|
||||
(joined
|
||||
(portRef NC0 (instanceRef sreg_0_ctr_1_0))
|
||||
(portRef D (instanceRef FF_9))))
|
||||
(net ishreg_addr_w1
|
||||
(joined
|
||||
(portRef NC1 (instanceRef sreg_0_ctr_1_0))
|
||||
(portRef D (instanceRef FF_8))))
|
||||
(net sreg_0_ctr_1_ci
|
||||
(joined
|
||||
(portRef CI (instanceRef sreg_0_ctr_1_0))
|
||||
(portRef COUT (instanceRef sreg_0_ctr_1_cia))))
|
||||
(net shreg_addr_w0
|
||||
(joined
|
||||
(portRef PC0 (instanceRef sreg_0_ctr_1_0))
|
||||
(portRef A (instanceRef INV_1))
|
||||
(portRef ADA0 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_9))))
|
||||
(net shreg_addr_w1
|
||||
(joined
|
||||
(portRef PC1 (instanceRef sreg_0_ctr_1_0))
|
||||
(portRef AD2 (instanceRef LUT4_3))
|
||||
(portRef ADA1 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_8))))
|
||||
(net ishreg_addr_w2
|
||||
(joined
|
||||
(portRef NC0 (instanceRef sreg_0_ctr_1_1))
|
||||
(portRef D (instanceRef FF_7))))
|
||||
(net ishreg_addr_w3
|
||||
(joined
|
||||
(portRef NC1 (instanceRef sreg_0_ctr_1_1))
|
||||
(portRef D (instanceRef FF_6))))
|
||||
(net co0
|
||||
(joined
|
||||
(portRef CI (instanceRef sreg_0_ctr_1_1))
|
||||
(portRef CO (instanceRef sreg_0_ctr_1_0))))
|
||||
(net shreg_addr_w2
|
||||
(joined
|
||||
(portRef PC0 (instanceRef sreg_0_ctr_1_1))
|
||||
(portRef AD1 (instanceRef LUT4_3))
|
||||
(portRef ADA2 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_7))))
|
||||
(net shreg_addr_w3
|
||||
(joined
|
||||
(portRef PC1 (instanceRef sreg_0_ctr_1_1))
|
||||
(portRef AD0 (instanceRef LUT4_3))
|
||||
(portRef ADA3 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_6))))
|
||||
(net ishreg_addr_w4
|
||||
(joined
|
||||
(portRef NC0 (instanceRef sreg_0_ctr_1_2))
|
||||
(portRef D (instanceRef FF_5))))
|
||||
(net ishreg_addr_w5
|
||||
(joined
|
||||
(portRef NC1 (instanceRef sreg_0_ctr_1_2))
|
||||
(portRef D (instanceRef FF_4))))
|
||||
(net co1
|
||||
(joined
|
||||
(portRef CI (instanceRef sreg_0_ctr_1_2))
|
||||
(portRef CO (instanceRef sreg_0_ctr_1_1))))
|
||||
(net shreg_addr_w4
|
||||
(joined
|
||||
(portRef PC0 (instanceRef sreg_0_ctr_1_2))
|
||||
(portRef AD3 (instanceRef LUT4_2))
|
||||
(portRef ADA4 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_5))))
|
||||
(net shreg_addr_w5
|
||||
(joined
|
||||
(portRef PC1 (instanceRef sreg_0_ctr_1_2))
|
||||
(portRef AD2 (instanceRef LUT4_2))
|
||||
(portRef ADA5 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_4))))
|
||||
(net ishreg_addr_w6
|
||||
(joined
|
||||
(portRef NC0 (instanceRef sreg_0_ctr_1_3))
|
||||
(portRef D (instanceRef FF_3))))
|
||||
(net ishreg_addr_w7
|
||||
(joined
|
||||
(portRef NC1 (instanceRef sreg_0_ctr_1_3))
|
||||
(portRef D (instanceRef FF_2))))
|
||||
(net co2
|
||||
(joined
|
||||
(portRef CI (instanceRef sreg_0_ctr_1_3))
|
||||
(portRef CO (instanceRef sreg_0_ctr_1_2))))
|
||||
(net shreg_addr_w6
|
||||
(joined
|
||||
(portRef PC0 (instanceRef sreg_0_ctr_1_3))
|
||||
(portRef AD1 (instanceRef LUT4_2))
|
||||
(portRef ADA6 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_3))))
|
||||
(net shreg_addr_w7
|
||||
(joined
|
||||
(portRef PC1 (instanceRef sreg_0_ctr_1_3))
|
||||
(portRef AD0 (instanceRef LUT4_2))
|
||||
(portRef ADA7 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_2))))
|
||||
(net ishreg_addr_w8
|
||||
(joined
|
||||
(portRef NC0 (instanceRef sreg_0_ctr_1_4))
|
||||
(portRef D (instanceRef FF_1))))
|
||||
(net ishreg_addr_w9
|
||||
(joined
|
||||
(portRef NC1 (instanceRef sreg_0_ctr_1_4))
|
||||
(portRef D (instanceRef FF_0))))
|
||||
(net co4
|
||||
(joined
|
||||
(portRef CO (instanceRef sreg_0_ctr_1_4))))
|
||||
(net co3
|
||||
(joined
|
||||
(portRef CI (instanceRef sreg_0_ctr_1_4))
|
||||
(portRef CO (instanceRef sreg_0_ctr_1_3))))
|
||||
(net shreg_addr_w8
|
||||
(joined
|
||||
(portRef PC0 (instanceRef sreg_0_ctr_1_4))
|
||||
(portRef AD3 (instanceRef LUT4_1))
|
||||
(portRef ADA8 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_1))))
|
||||
(net shreg_addr_w9
|
||||
(joined
|
||||
(portRef PC1 (instanceRef sreg_0_ctr_1_4))
|
||||
(portRef AD2 (instanceRef LUT4_1))
|
||||
(portRef ADA9 (instanceRef sram_1_0_0_0))
|
||||
(portRef Q (instanceRef FF_0))))
|
||||
(net Q0
|
||||
(joined
|
||||
(portRef (member Q 0))
|
||||
(portRef DOA0 (instanceRef sram_1_0_0_0))))
|
||||
(net Reset
|
||||
(joined
|
||||
(portRef Reset)
|
||||
(portRef A (instanceRef OR2_t0))
|
||||
(portRef A (instanceRef INV_0))
|
||||
(portRef RSTA (instanceRef sram_1_0_0_0))))
|
||||
(net ClockEn
|
||||
(joined
|
||||
(portRef ClockEn)
|
||||
(portRef AD1 (instanceRef LUT4_1))
|
||||
(portRef OCEA (instanceRef sram_1_0_0_0))
|
||||
(portRef CEA (instanceRef sram_1_0_0_0))
|
||||
(portRef SP (instanceRef FF_9))
|
||||
(portRef SP (instanceRef FF_8))
|
||||
(portRef SP (instanceRef FF_7))
|
||||
(portRef SP (instanceRef FF_6))
|
||||
(portRef SP (instanceRef FF_5))
|
||||
(portRef SP (instanceRef FF_4))
|
||||
(portRef SP (instanceRef FF_3))
|
||||
(portRef SP (instanceRef FF_2))
|
||||
(portRef SP (instanceRef FF_1))
|
||||
(portRef SP (instanceRef FF_0))))
|
||||
(net Clock
|
||||
(joined
|
||||
(portRef Clock)
|
||||
(portRef CLKA (instanceRef sram_1_0_0_0))
|
||||
(portRef CK (instanceRef FF_9))
|
||||
(portRef CK (instanceRef FF_8))
|
||||
(portRef CK (instanceRef FF_7))
|
||||
(portRef CK (instanceRef FF_6))
|
||||
(portRef CK (instanceRef FF_5))
|
||||
(portRef CK (instanceRef FF_4))
|
||||
(portRef CK (instanceRef FF_3))
|
||||
(portRef CK (instanceRef FF_2))
|
||||
(portRef CK (instanceRef FF_1))
|
||||
(portRef CK (instanceRef FF_0))))
|
||||
(net Din0
|
||||
(joined
|
||||
(portRef (member Din 0))
|
||||
(portRef DIA1 (instanceRef sram_1_0_0_0))))))))
|
||||
(design CursorRam
|
||||
(cellRef CursorRam
|
||||
(libraryRef ORCLIB)))
|
||||
)
|
|
@ -0,0 +1,10 @@
|
|||
<?xml version="1.0" encoding="UTF-8"?>
|
||||
<DiamondModule name="CursorRam" module="CursorRam" VendorName="Lattice Semiconductor Corporation" generator="IPexpress" date="2019 08 08 17:25:27.878" version="5.2" type="Module" synthesis="synplify" source_format="VHDL">
|
||||
<Package>
|
||||
<File name="" type="" modified="2019 08 08 17:25:27.708"/>
|
||||
<File name="CursorRam.lpc" type="lpc" modified="2019 08 08 17:25:26.221"/>
|
||||
<File name="CursorRam.vhd" type="top_level_vhdl" modified="2019 08 08 17:25:26.292"/>
|
||||
<File name="CursorRam_tmpl.vhd" type="template_vhdl" modified="2019 08 08 17:25:26.297"/>
|
||||
<File name="tb_CursorRam_tmpl.vhd" type="testbench_vhdl" modified="2019 08 08 17:25:26.308"/>
|
||||
</Package>
|
||||
</DiamondModule>
|
|
@ -0,0 +1,53 @@
|
|||
MODULE CursorRam DEFIN CursorRam.vhd
|
||||
SUBMODULE CU2
|
||||
INSTANCE sreg_0_ctr_1_4
|
||||
SUBMODULE CU2
|
||||
INSTANCE sreg_0_ctr_1_3
|
||||
SUBMODULE CU2
|
||||
INSTANCE sreg_0_ctr_1_2
|
||||
SUBMODULE CU2
|
||||
INSTANCE sreg_0_ctr_1_1
|
||||
SUBMODULE CU2
|
||||
INSTANCE sreg_0_ctr_1_0
|
||||
SUBMODULE FADD2B
|
||||
INSTANCE sreg_0_ctr_1_cia
|
||||
SUBMODULE VHI
|
||||
INSTANCE scuba_vhi_inst
|
||||
SUBMODULE VLO
|
||||
INSTANCE scuba_vlo_inst
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_0
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_1
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_2
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_3
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_4
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_5
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_6
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_7
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_8
|
||||
SUBMODULE FD1P3IX
|
||||
INSTANCE FF_9
|
||||
SUBMODULE DP8KC
|
||||
INSTANCE sram_1_0_0_0
|
||||
SUBMODULE INV
|
||||
INSTANCE INV_0
|
||||
SUBMODULE OR2
|
||||
INSTANCE OR2_t0
|
||||
SUBMODULE ROM16X1A
|
||||
INSTANCE LUT4_0
|
||||
SUBMODULE ROM16X1A
|
||||
INSTANCE LUT4_1
|
||||
SUBMODULE ROM16X1A
|
||||
INSTANCE LUT4_2
|
||||
SUBMODULE ROM16X1A
|
||||
INSTANCE LUT4_3
|
||||
SUBMODULE INV
|
||||
INSTANCE INV_1
|
|
@ -0,0 +1,44 @@
|
|||
[Device]
|
||||
Family=machxo2
|
||||
PartType=LCMXO2-7000HC
|
||||
PartName=LCMXO2-7000HC-4TG144C
|
||||
SpeedGrade=4
|
||||
Package=TQFP144
|
||||
OperatingCondition=COM
|
||||
Status=S
|
||||
|
||||
[IP]
|
||||
VendorName=Lattice Semiconductor Corporation
|
||||
CoreType=LPM
|
||||
CoreStatus=Demo
|
||||
CoreName=RAM_Based_Shift_Register
|
||||
CoreRevision=5.2
|
||||
ModuleName=CursorRam
|
||||
SourceFormat=VHDL
|
||||
ParameterFileVersion=1.0
|
||||
Date=08/08/2019
|
||||
Time=17:25:26
|
||||
|
||||
[Parameters]
|
||||
Verilog=0
|
||||
VHDL=1
|
||||
EDIF=1
|
||||
Destination=Synplicity
|
||||
Expression=BusA(0 to 7)
|
||||
Order=Big Endian [MSB:LSB]
|
||||
IO=0
|
||||
DataWidth=1
|
||||
Type=Fixed
|
||||
NoOfShifts=1024
|
||||
MaxLossyShifts=16
|
||||
MaxLosslessShifts=16
|
||||
EOR=0
|
||||
MemFile=
|
||||
MemFormat=bin
|
||||
RamType=bram
|
||||
|
||||
[FilesGenerated]
|
||||
=mem
|
||||
|
||||
[Command]
|
||||
cmd_line= -w -n CursorRam -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 1 -depth 1024 -mode 8
|
|
@ -0,0 +1,5 @@
|
|||
Din[0] i
|
||||
Clock i
|
||||
ClockEn i
|
||||
Reset i
|
||||
Q[0] o
|
|
@ -0,0 +1 @@
|
|||
CursorRam.vhd
|
|
@ -0,0 +1,36 @@
|
|||
SCUBA, Version Diamond (64-bit) 3.10.2.115
|
||||
Thu Aug 08 17:25:26 2019
|
||||
|
||||
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
|
||||
Copyright (c) 1995 AT&T Corp. All rights reserved.
|
||||
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
|
||||
Copyright (c) 2001 Agere Systems All rights reserved.
|
||||
Copyright (c) 2002-2017 Lattice Semiconductor Corporation, All rights reserved.
|
||||
|
||||
Issued command : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n CursorRam -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 1 -depth 1024 -mode 8
|
||||
Circuit name : CursorRam
|
||||
Module type : shiftreg
|
||||
Module Version : 5.2
|
||||
Ports :
|
||||
Inputs : Din[0:0], Clock, ClockEn, Reset
|
||||
Outputs : Q[0:0]
|
||||
I/O buffer : not inserted
|
||||
EDIF output : CursorRam.edn
|
||||
VHDL output : CursorRam.vhd
|
||||
VHDL template : CursorRam_tmpl.vhd
|
||||
VHDL testbench : tb_CursorRam_tmpl.vhd
|
||||
VHDL purpose : for synthesis and simulation
|
||||
Bus notation : big endian
|
||||
Report output : CursorRam.srp
|
||||
Element Usage :
|
||||
CU2 : 5
|
||||
FADD2B : 1
|
||||
FD1P3IX : 10
|
||||
INV : 2
|
||||
OR2 : 1
|
||||
ROM16X1A : 4
|
||||
DP8KC : 1
|
||||
Estimated Resource Usage:
|
||||
LUT : 17
|
||||
EBR : 1
|
||||
Reg : 10
|
|
@ -0,0 +1,309 @@
|
|||
-- VHDL netlist generated by SCUBA Diamond (64-bit) 3.10.2.115
|
||||
-- Module Version: 5.2
|
||||
--C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n CursorRam -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 1 -depth 1024 -mode 8
|
||||
|
||||
-- Thu Aug 08 17:25:26 2019
|
||||
|
||||
library IEEE;
|
||||
use IEEE.std_logic_1164.all;
|
||||
-- synopsys translate_off
|
||||
library MACHXO2;
|
||||
use MACHXO2.components.all;
|
||||
-- synopsys translate_on
|
||||
|
||||
entity CursorRam is
|
||||
port (
|
||||
Din: in std_logic_vector(0 downto 0);
|
||||
Clock: in std_logic;
|
||||
ClockEn: in std_logic;
|
||||
Reset: in std_logic;
|
||||
Q: out std_logic_vector(0 downto 0));
|
||||
end CursorRam;
|
||||
|
||||
architecture Structure of CursorRam is
|
||||
|
||||
-- internal signal declarations
|
||||
signal shreg_addr_w0_inv: std_logic;
|
||||
signal func_and_inet_2: std_logic;
|
||||
signal func_and_inet_1: std_logic;
|
||||
signal func_and_inet: std_logic;
|
||||
signal dec0_r2046: std_logic;
|
||||
signal Reset_inv: std_logic;
|
||||
signal srrst_ctr: std_logic;
|
||||
signal scuba_vlo: std_logic;
|
||||
signal scuba_vhi: std_logic;
|
||||
signal ishreg_addr_w0: std_logic;
|
||||
signal ishreg_addr_w1: std_logic;
|
||||
signal sreg_0_ctr_1_ci: std_logic;
|
||||
signal shreg_addr_w0: std_logic;
|
||||
signal shreg_addr_w1: std_logic;
|
||||
signal ishreg_addr_w2: std_logic;
|
||||
signal ishreg_addr_w3: std_logic;
|
||||
signal co0: std_logic;
|
||||
signal shreg_addr_w2: std_logic;
|
||||
signal shreg_addr_w3: std_logic;
|
||||
signal ishreg_addr_w4: std_logic;
|
||||
signal ishreg_addr_w5: std_logic;
|
||||
signal co1: std_logic;
|
||||
signal shreg_addr_w4: std_logic;
|
||||
signal shreg_addr_w5: std_logic;
|
||||
signal ishreg_addr_w6: std_logic;
|
||||
signal ishreg_addr_w7: std_logic;
|
||||
signal co2: std_logic;
|
||||
signal shreg_addr_w6: std_logic;
|
||||
signal shreg_addr_w7: std_logic;
|
||||
signal ishreg_addr_w8: std_logic;
|
||||
signal ishreg_addr_w9: std_logic;
|
||||
signal co4: std_logic;
|
||||
signal co3: std_logic;
|
||||
signal shreg_addr_w8: std_logic;
|
||||
signal shreg_addr_w9: std_logic;
|
||||
|
||||
-- local component declarations
|
||||
component CU2
|
||||
port (CI: in std_logic; PC0: in std_logic; PC1: in std_logic;
|
||||
CO: out std_logic; NC0: out std_logic; NC1: out std_logic);
|
||||
end component;
|
||||
component FADD2B
|
||||
port (A0: in std_logic; A1: in std_logic; B0: in std_logic;
|
||||
B1: in std_logic; CI: in std_logic; COUT: out std_logic;
|
||||
S0: out std_logic; S1: out std_logic);
|
||||
end component;
|
||||
component FD1P3IX
|
||||
port (D: in std_logic; SP: in std_logic; CK: in std_logic;
|
||||
CD: in std_logic; Q: out std_logic);
|
||||
end component;
|
||||
component INV
|
||||
port (A: in std_logic; Z: out std_logic);
|
||||
end component;
|
||||
component OR2
|
||||
port (A: in std_logic; B: in std_logic; Z: out std_logic);
|
||||
end component;
|
||||
component ROM16X1A
|
||||
generic (INITVAL : in std_logic_vector(15 downto 0));
|
||||
port (AD3: in std_logic; AD2: in std_logic; AD1: in std_logic;
|
||||
AD0: in std_logic; DO0: out std_logic);
|
||||
end component;
|
||||
component VHI
|
||||
port (Z: out std_logic);
|
||||
end component;
|
||||
component VLO
|
||||
port (Z: out std_logic);
|
||||
end component;
|
||||
component DP8KC
|
||||
generic (INIT_DATA : in String; ASYNC_RESET_RELEASE : in String;
|
||||
RESETMODE : in String; GSR : in String;
|
||||
WRITEMODE_B : in String; WRITEMODE_A : in String;
|
||||
CSDECODE_B : in String; CSDECODE_A : in String;
|
||||
REGMODE_B : in String; REGMODE_A : in String;
|
||||
DATA_WIDTH_B : in Integer; DATA_WIDTH_A : in Integer);
|
||||
port (DIA8: in std_logic; DIA7: in std_logic;
|
||||
DIA6: in std_logic; DIA5: in std_logic;
|
||||
DIA4: in std_logic; DIA3: in std_logic;
|
||||
DIA2: in std_logic; DIA1: in std_logic;
|
||||
DIA0: in std_logic; ADA12: in std_logic;
|
||||
ADA11: in std_logic; ADA10: in std_logic;
|
||||
ADA9: in std_logic; ADA8: in std_logic;
|
||||
ADA7: in std_logic; ADA6: in std_logic;
|
||||
ADA5: in std_logic; ADA4: in std_logic;
|
||||
ADA3: in std_logic; ADA2: in std_logic;
|
||||
ADA1: in std_logic; ADA0: in std_logic; CEA: in std_logic;
|
||||
OCEA: in std_logic; CLKA: in std_logic; WEA: in std_logic;
|
||||
CSA2: in std_logic; CSA1: in std_logic;
|
||||
CSA0: in std_logic; RSTA: in std_logic;
|
||||
DIB8: in std_logic; DIB7: in std_logic;
|
||||
DIB6: in std_logic; DIB5: in std_logic;
|
||||
DIB4: in std_logic; DIB3: in std_logic;
|
||||
DIB2: in std_logic; DIB1: in std_logic;
|
||||
DIB0: in std_logic; ADB12: in std_logic;
|
||||
ADB11: in std_logic; ADB10: in std_logic;
|
||||
ADB9: in std_logic; ADB8: in std_logic;
|
||||
ADB7: in std_logic; ADB6: in std_logic;
|
||||
ADB5: in std_logic; ADB4: in std_logic;
|
||||
ADB3: in std_logic; ADB2: in std_logic;
|
||||
ADB1: in std_logic; ADB0: in std_logic; CEB: in std_logic;
|
||||
OCEB: in std_logic; CLKB: in std_logic; WEB: in std_logic;
|
||||
CSB2: in std_logic; CSB1: in std_logic;
|
||||
CSB0: in std_logic; RSTB: in std_logic;
|
||||
DOA8: out std_logic; DOA7: out std_logic;
|
||||
DOA6: out std_logic; DOA5: out std_logic;
|
||||
DOA4: out std_logic; DOA3: out std_logic;
|
||||
DOA2: out std_logic; DOA1: out std_logic;
|
||||
DOA0: out std_logic; DOB8: out std_logic;
|
||||
DOB7: out std_logic; DOB6: out std_logic;
|
||||
DOB5: out std_logic; DOB4: out std_logic;
|
||||
DOB3: out std_logic; DOB2: out std_logic;
|
||||
DOB1: out std_logic; DOB0: out std_logic);
|
||||
end component;
|
||||
attribute MEM_LPC_FILE : string;
|
||||
attribute MEM_INIT_FILE : string;
|
||||
attribute GSR : string;
|
||||
attribute MEM_LPC_FILE of sram_1_0_0_0 : label is "CursorRam.lpc";
|
||||
attribute MEM_INIT_FILE of sram_1_0_0_0 : label is "";
|
||||
attribute GSR of FF_9 : label is "ENABLED";
|
||||
attribute GSR of FF_8 : label is "ENABLED";
|
||||
attribute GSR of FF_7 : label is "ENABLED";
|
||||
attribute GSR of FF_6 : label is "ENABLED";
|
||||
attribute GSR of FF_5 : label is "ENABLED";
|
||||
attribute GSR of FF_4 : label is "ENABLED";
|
||||
attribute GSR of FF_3 : label is "ENABLED";
|
||||
attribute GSR of FF_2 : label is "ENABLED";
|
||||
attribute GSR of FF_1 : label is "ENABLED";
|
||||
attribute GSR of FF_0 : label is "ENABLED";
|
||||
attribute NGD_DRC_MASK : integer;
|
||||
attribute NGD_DRC_MASK of Structure : architecture is 1;
|
||||
|
||||
begin
|
||||
-- component instantiation statements
|
||||
INV_1: INV
|
||||
port map (A=>shreg_addr_w0, Z=>shreg_addr_w0_inv);
|
||||
|
||||
LUT4_3: ROM16X1A
|
||||
generic map (initval=> X"8000")
|
||||
port map (AD3=>shreg_addr_w0_inv, AD2=>shreg_addr_w1,
|
||||
AD1=>shreg_addr_w2, AD0=>shreg_addr_w3, DO0=>func_and_inet);
|
||||
|
||||
LUT4_2: ROM16X1A
|
||||
generic map (initval=> X"8000")
|
||||
port map (AD3=>shreg_addr_w4, AD2=>shreg_addr_w5,
|
||||
AD1=>shreg_addr_w6, AD0=>shreg_addr_w7, DO0=>func_and_inet_1);
|
||||
|
||||
LUT4_1: ROM16X1A
|
||||
generic map (initval=> X"8000")
|
||||
port map (AD3=>shreg_addr_w8, AD2=>shreg_addr_w9, AD1=>ClockEn,
|
||||
AD0=>scuba_vhi, DO0=>func_and_inet_2);
|
||||
|
||||
LUT4_0: ROM16X1A
|
||||
generic map (initval=> X"8000")
|
||||
port map (AD3=>func_and_inet, AD2=>func_and_inet_1,
|
||||
AD1=>func_and_inet_2, AD0=>scuba_vhi, DO0=>dec0_r2046);
|
||||
|
||||
OR2_t0: OR2
|
||||
port map (A=>Reset, B=>dec0_r2046, Z=>srrst_ctr);
|
||||
|
||||
INV_0: INV
|
||||
port map (A=>Reset, Z=>Reset_inv);
|
||||
|
||||
sram_1_0_0_0: DP8KC
|
||||
generic map (INIT_DATA=> "STATIC", ASYNC_RESET_RELEASE=> "SYNC",
|
||||
CSDECODE_B=> "0b111", CSDECODE_A=> "0b000", WRITEMODE_B=> "NORMAL",
|
||||
WRITEMODE_A=> "READBEFOREWRITE", GSR=> "ENABLED", RESETMODE=> "ASYNC",
|
||||
REGMODE_B=> "NOREG", REGMODE_A=> "NOREG", DATA_WIDTH_B=> 1,
|
||||
DATA_WIDTH_A=> 1)
|
||||
port map (DIA8=>scuba_vlo, DIA7=>scuba_vlo, DIA6=>scuba_vlo,
|
||||
DIA5=>scuba_vlo, DIA4=>scuba_vlo, DIA3=>scuba_vlo,
|
||||
DIA2=>scuba_vlo, DIA1=>Din(0), DIA0=>scuba_vlo,
|
||||
ADA12=>scuba_vlo, ADA11=>scuba_vlo, ADA10=>scuba_vlo,
|
||||
ADA9=>shreg_addr_w9, ADA8=>shreg_addr_w8,
|
||||
ADA7=>shreg_addr_w7, ADA6=>shreg_addr_w6,
|
||||
ADA5=>shreg_addr_w5, ADA4=>shreg_addr_w4,
|
||||
ADA3=>shreg_addr_w3, ADA2=>shreg_addr_w2,
|
||||
ADA1=>shreg_addr_w1, ADA0=>shreg_addr_w0, CEA=>ClockEn,
|
||||
OCEA=>ClockEn, CLKA=>Clock, WEA=>Reset_inv, CSA2=>scuba_vlo,
|
||||
CSA1=>scuba_vlo, CSA0=>scuba_vlo, RSTA=>Reset,
|
||||
DIB8=>scuba_vlo, DIB7=>scuba_vlo, DIB6=>scuba_vlo,
|
||||
DIB5=>scuba_vlo, DIB4=>scuba_vlo, DIB3=>scuba_vlo,
|
||||
DIB2=>scuba_vlo, DIB1=>scuba_vlo, DIB0=>scuba_vlo,
|
||||
ADB12=>scuba_vlo, ADB11=>scuba_vlo, ADB10=>scuba_vlo,
|
||||
ADB9=>scuba_vlo, ADB8=>scuba_vlo, ADB7=>scuba_vlo,
|
||||
ADB6=>scuba_vlo, ADB5=>scuba_vlo, ADB4=>scuba_vlo,
|
||||
ADB3=>scuba_vlo, ADB2=>scuba_vlo, ADB1=>scuba_vlo,
|
||||
ADB0=>scuba_vlo, CEB=>scuba_vhi, OCEB=>scuba_vhi,
|
||||
CLKB=>scuba_vlo, WEB=>scuba_vlo, CSB2=>scuba_vlo,
|
||||
CSB1=>scuba_vlo, CSB0=>scuba_vlo, RSTB=>scuba_vlo,
|
||||
DOA8=>open, DOA7=>open, DOA6=>open, DOA5=>open, DOA4=>open,
|
||||
DOA3=>open, DOA2=>open, DOA1=>open, DOA0=>Q(0), DOB8=>open,
|
||||
DOB7=>open, DOB6=>open, DOB5=>open, DOB4=>open, DOB3=>open,
|
||||
DOB2=>open, DOB1=>open, DOB0=>open);
|
||||
|
||||
FF_9: FD1P3IX
|
||||
port map (D=>ishreg_addr_w0, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w0);
|
||||
|
||||
FF_8: FD1P3IX
|
||||
port map (D=>ishreg_addr_w1, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w1);
|
||||
|
||||
FF_7: FD1P3IX
|
||||
port map (D=>ishreg_addr_w2, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w2);
|
||||
|
||||
FF_6: FD1P3IX
|
||||
port map (D=>ishreg_addr_w3, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w3);
|
||||
|
||||
FF_5: FD1P3IX
|
||||
port map (D=>ishreg_addr_w4, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w4);
|
||||
|
||||
FF_4: FD1P3IX
|
||||
port map (D=>ishreg_addr_w5, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w5);
|
||||
|
||||
FF_3: FD1P3IX
|
||||
port map (D=>ishreg_addr_w6, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w6);
|
||||
|
||||
FF_2: FD1P3IX
|
||||
port map (D=>ishreg_addr_w7, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w7);
|
||||
|
||||
FF_1: FD1P3IX
|
||||
port map (D=>ishreg_addr_w8, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w8);
|
||||
|
||||
FF_0: FD1P3IX
|
||||
port map (D=>ishreg_addr_w9, SP=>ClockEn, CK=>Clock,
|
||||
CD=>srrst_ctr, Q=>shreg_addr_w9);
|
||||
|
||||
scuba_vlo_inst: VLO
|
||||
port map (Z=>scuba_vlo);
|
||||
|
||||
scuba_vhi_inst: VHI
|
||||
port map (Z=>scuba_vhi);
|
||||
|
||||
sreg_0_ctr_1_cia: FADD2B
|
||||
port map (A0=>scuba_vlo, A1=>scuba_vhi, B0=>scuba_vlo,
|
||||
B1=>scuba_vhi, CI=>scuba_vlo, COUT=>sreg_0_ctr_1_ci,
|
||||
S0=>open, S1=>open);
|
||||
|
||||
sreg_0_ctr_1_0: CU2
|
||||
port map (CI=>sreg_0_ctr_1_ci, PC0=>shreg_addr_w0,
|
||||
PC1=>shreg_addr_w1, CO=>co0, NC0=>ishreg_addr_w0,
|
||||
NC1=>ishreg_addr_w1);
|
||||
|
||||
sreg_0_ctr_1_1: CU2
|
||||
port map (CI=>co0, PC0=>shreg_addr_w2, PC1=>shreg_addr_w3,
|
||||
CO=>co1, NC0=>ishreg_addr_w2, NC1=>ishreg_addr_w3);
|
||||
|
||||
sreg_0_ctr_1_2: CU2
|
||||
port map (CI=>co1, PC0=>shreg_addr_w4, PC1=>shreg_addr_w5,
|
||||
CO=>co2, NC0=>ishreg_addr_w4, NC1=>ishreg_addr_w5);
|
||||
|
||||
sreg_0_ctr_1_3: CU2
|
||||
port map (CI=>co2, PC0=>shreg_addr_w6, PC1=>shreg_addr_w7,
|
||||
CO=>co3, NC0=>ishreg_addr_w6, NC1=>ishreg_addr_w7);
|
||||
|
||||
sreg_0_ctr_1_4: CU2
|
||||
port map (CI=>co3, PC0=>shreg_addr_w8, PC1=>shreg_addr_w9,
|
||||
CO=>co4, NC0=>ishreg_addr_w8, NC1=>ishreg_addr_w9);
|
||||
|
||||
end Structure;
|
||||
|
||||
-- synopsys translate_off
|
||||
library MACHXO2;
|
||||
configuration Structure_CON of CursorRam is
|
||||
for Structure
|
||||
for all:CU2 use entity MACHXO2.CU2(V); end for;
|
||||
for all:FADD2B use entity MACHXO2.FADD2B(V); end for;
|
||||
for all:FD1P3IX use entity MACHXO2.FD1P3IX(V); end for;
|
||||
for all:INV use entity MACHXO2.INV(V); end for;
|
||||
for all:OR2 use entity MACHXO2.OR2(V); end for;
|
||||
for all:ROM16X1A use entity MACHXO2.ROM16X1A(V); end for;
|
||||
for all:VHI use entity MACHXO2.VHI(V); end for;
|
||||
for all:VLO use entity MACHXO2.VLO(V); end for;
|
||||
for all:DP8KC use entity MACHXO2.DP8KC(V); end for;
|
||||
end for;
|
||||
end Structure_CON;
|
||||
|
||||
-- synopsys translate_on
|
|
@ -0,0 +1,14 @@
|
|||
-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
|
||||
-- Module Version: 5.2
|
||||
-- Thu Aug 08 17:25:26 2019
|
||||
|
||||
-- parameterized module component declaration
|
||||
component CursorRam
|
||||
port (Din: in std_logic_vector(0 downto 0); Clock: in std_logic;
|
||||
ClockEn: in std_logic; Reset: in std_logic;
|
||||
Q: out std_logic_vector(0 downto 0));
|
||||
end component;
|
||||
|
||||
-- parameterized module component instance
|
||||
__ : CursorRam
|
||||
port map (Din(0 downto 0)=>__, Clock=>__, ClockEn=>__, Reset=>__, Q(0 downto 0)=>__);
|
|
@ -0,0 +1,250 @@
|
|||
@@@@@@@@@@@@@@@@&^-;,;^&#@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@#**+ ..:;^*@@@@@@@@@@@@@
|
||||
@@@@@@@@@@&-:.. ... .+@@@@@@@@@@@@
|
||||
@@@@@@@@%! .. ....+%@@@@@@@@@@
|
||||
@@@@@@@#; . :^#@@@@@@@@
|
||||
@@@@@@@= .:;;: =@@@@@@@@
|
||||
@@@@@@@; ,,. .. :!+=-: :=@@@@@@@
|
||||
@@@@@@*. :=?^!!--;;;^??=^, .&@@@@@@
|
||||
@@@@@@+ ,??=+++=+^^++^^+^: +@@@@@@
|
||||
@@@@@@? !=^;,::,-^-,..:;^! ,%@@@@@@
|
||||
@@@@@@* :++!,. :++: .:;^+: ?@@@@@@@
|
||||
@@@@@@%: ;?=+^!!!!-&%+--^+?&!.*@@@@@@@
|
||||
@@@@@@@+ ,:,=====+^^=&**?^^=??^:+@@@@@@@
|
||||
@@@@@@@#:,,.!-!!!;;!!!-^-;,;!-!.+@@@@@@@
|
||||
@@@@@@@@^ :;;,..,,. ..::..,;:,%@@@@@@@
|
||||
@@@@@@@@%-. ..::.::,;;!!;,,....?@@@@@@@@
|
||||
@@@@@@@@@%-! ...,;;!-^^^^,. :=@@@@@@@@@
|
||||
@@@@@@@@%?*=,. ..,;;,,,;;..,?@@@@@@@@@@
|
||||
@@@@##%*&%#&-,.....:....:..:+?%@@@@@@@@@
|
||||
@#%***%%####?;::. .......,!^**%#@@@@@@@
|
||||
%%%%##%%##%##=,,:::...::,!-;^##%%%##@@@@
|
||||
##%%%%%%%##%##?;,,,,;,;!-^!;+%####%%####
|
||||
%%%%%%%%%####*?+!;,,,,!--!,-?###%%%%%%%%
|
||||
WOZ @
|
||||
|
||||
@@@@@@@@#&+!;;;!^+=&%#@@@@@@@@@@@@@@@@@@
|
||||
@@@@#?^;. .. ...:-*@@@@@@@@@@@@@@@@
|
||||
@@@*-. .. .:. .^%@@@@@@@@@@@@@@
|
||||
@@&; ..:. .. ,?@@@@@@@@@@@@@
|
||||
@=. .:!^, ..... .^#@@@@@@@@@@@
|
||||
? .:,!+! ...... -#@@@@@@@@@@
|
||||
+ .:;!!?=, .... +@@@@@@@@@@
|
||||
- .:;^^-+?-. !@@@@@@@@@@
|
||||
- .:,,;;,:::,,. ,#@@@@@@@@@
|
||||
+ ...:,;,. :;!;,. .*@@@@@@@@@
|
||||
? ... :+^,:..:-=?&?+, -#@@@@@@@@
|
||||
*. .;,,::;&%?+^^+=&&&&?+, .+@@@@@@@@
|
||||
@^ .^=^^^-?##&++====++++^!;. ^@@@@@@@@
|
||||
@%! -++++--==+^^^^+^^+++=^,. ?@@@@@@@@
|
||||
@@#! :--^+^;,,;^^!;-^^++++! !#@@@@@@@
|
||||
@@@#! ;^^-!;,:,!!;,!-^^^+^!. :!*@@@@@@@
|
||||
@@@@*:.--!,,;;,;!--!!---!;^; :-?@@@@@@@
|
||||
@@@@@?::!!;!!;,!-^^--!;,:!+^. .;^&@@@@@@
|
||||
@@@@@@&-;;!!--!!----;,::,-++, .,!^*@@@@@
|
||||
@@@@@@@%;::;!;;,,,,,:::,!-^+;..,!!=@@@@@
|
||||
@@@@@@@&,,..:,,,,,,,,,;;!-^^,.:;!-=&#@@@
|
||||
@@@@@@@=,;,:::,,,;,,;;;!!!-!,:,!!^++*#%#
|
||||
@@@@##%=!;;;,,,;;;;;;;;;!!!;,;-!!^=%##%#
|
||||
STEVE JOBS @
|
||||
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@@^^@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@@@^^^^^@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@@^^^^^@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@^^^^^@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@^^^^^@@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@^^^@@@@^^@@@@^^^^@@@@@@@@@@@
|
||||
@@@@@@@@^^^^^^^^^^^^^^^^^^^^^^^^^@@@@@@@
|
||||
@@@@@@^^^^^^^^^^^^^^^^^^^^^^^^^^^^@@@@@@
|
||||
@@@@@***************************@@@@@@@@
|
||||
@@@@***************************@@@@@@@@@
|
||||
@@@@**************************@@@@@@@@@@
|
||||
@@@+++++++++++++++++++++++++++@@@@@@@@@@
|
||||
@@@+++++++++++++++++++++++++++@@@@@@@@@@
|
||||
@@@++++++++++++++++++++++++++++@@@@@@@@@
|
||||
@@@@;;;;;;;;;;;;;;;;;;;;;;;;;;;;@@@@@@@@
|
||||
@@@@;;;;;;;;;;;;;;;;;;;;;;;;;;;;;@@@@@@@
|
||||
@@@@@;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;@@@@@
|
||||
@@@@@,,,,,,,,,,,,,,,,,,,,,,,,,,,,,,@@@@@
|
||||
@@@@@@,,,,,,,,,,,,,,,,,,,,,,,,,,,,@@@@@@
|
||||
@@@@@@@,,,,,,,,,,,,,,,,,,,,,,,,,,@@@@@@@
|
||||
@@@@@@@@@;;;;;;;;;;;;;;;;;;;;;;;@@@@@@@@
|
||||
@@@@@@@@@@;;;;;;;;@@@@;;;;;;;;@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
||||
HAPPY 30TH BIRTHDAY APPLE! @
|
||||
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@@#=!,;=%@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@#+,...,^%@@@@@@@
|
||||
@@@@@@@#%*%@@@@@@@@@@@@@*-::;;,!?@@@@@@@
|
||||
@@@@@@*^:.!?@@@@@@@@@@@@%+!!++^^=#@@@@@@
|
||||
@@@@@*-. .:!?@@@@@@@@@@@@*=^^+^^=%@@@@@@
|
||||
@@@@@?!;!^--+*@@@@@@@@@@@@&-;;!!+*@@@@@@
|
||||
@@@@@&^!-+^+?#@@@@@@@@@@@@*^;,;!+&@@@@@@
|
||||
@@@@@%+!!!!^&#@@@@@@@@@@@@#*=^^=&#@@@@@@
|
||||
@@@@@@&!::,^*@@@@@@@@@@@@@@@@%%#@@@@@@@@
|
||||
@@@@@@#=,.;=#@@@@@@@@@@##@@@@@@@@@@###@@
|
||||
@@@####&^;-?%@@@@@@@@@@#%#@@@@@@@@#%%%#@
|
||||
@@#%%%%*&&?&*%%##@@@@@#%%#@@@@@@@#%**%##
|
||||
@#%%%######%%%%%#@@@@@@%*%#@@@##@#%**%##
|
||||
#%%%%%#########%******&?===??=?*##%&&*#@
|
||||
@#%%%%%%%###%%#%?^!!-!!!!!;!!-+&#@%&&*%#
|
||||
##%%*&**%#@#%%*&+-!;;;;;;;;!!-+&#@#***%#
|
||||
*%%%***%#@@@#%&=+^-!;;!!;;;;,,-?%@@@#%%*
|
||||
%**%%####@@%&=+^^!;,;--;,,,:,;^?*%###%%%
|
||||
%&=?&%###%*=^-^+++^-^+==^--!-^^+++=?%@@@
|
||||
@%&===?====+++=?*#@##@#%&???=+^^+=?*#@@@
|
||||
@@%?+^^+==???=+?%@@@@@@*=+======?&?&%@@@
|
||||
@@%=-!-----!;:,-*@@@@@@#=!,,;;;;!!!-?#@@
|
||||
@@#+, ..:,,:. .!&@@@@@@@?!::::,,;!-+&#@@
|
||||
WOZ AND JOBS HOLDING APPLE I @
|
||||
|
||||
@@@@@@@@@@@@@@@@@@###@@@@@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@#%%%%%%%#@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@#%%%######%%%%#@@@@@@@@@@@
|
||||
@@@@@@@@@@@@#%%##############%%%##@@@@@@
|
||||
@@@@@@@@@@@#%###################%%%%%#@@
|
||||
@@@@@@@@@@#%######################%%%&=@
|
||||
@@@@@@@@*%%######%#@@@##@@#######%#%?^!#
|
||||
@@@@@@@#*??*%###=-+=*#@@@@#@######*=-;-@
|
||||
@@@@@@%%###*&&&%&?+^^^?@####@####&+!!-^@
|
||||
@@@@#%%%=;+*##%&&&*&??%########@&-;!^^+@
|
||||
@@@#%#%! .;=*#@%*&&*########@#+;-^^^^@
|
||||
@@%%#&; .... .;+*#@#*&&&%##@@#=--^^^!&@
|
||||
#%%%#?. ..... .;+*#@#*&?&*%?-^^^-!*@@
|
||||
*-=%##%,... ....... .;+*#@#%*=^^^^--%@@@
|
||||
@%-:^&#?;..... .:......&%%#@*^^^^!^@@@@@
|
||||
@@@?;:;?%*^,..:. ::..*@###&^^^^!=@@@@@@
|
||||
@@@@@%^,,^*%&-:.:. ;#@##@&^^^^!&@@@@@@@
|
||||
@@@@@@@@&!:;=%%?##?^#@##@*^^^-!*@@@@@@@@
|
||||
@@@@@@@@@@#+,,-&%#@@###@*^^^--#@@@@@@@@@
|
||||
@@@@@@@@@@@@@*-:,^*#@#@%^^^!^@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@#=;:;=**+^^!=@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@%^:.:,,;&@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@@&=++*@@@@@@@@@@@@@@
|
||||
APPLE II @
|
||||
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@@#@@@@@@@
|
||||
@@@@@@@@@@@@@@@#%%%%%%*******&&&?%@@@@@@
|
||||
@@@@@@@@@@@@@@@%!;!!!;;;;;;;;;;??%@@@@@@
|
||||
@@@@@@@@@@@@@@@%!+===??=======;?=%@@@@@@
|
||||
@@@@@@@@@@@@@@@*;+=?&=?&===???;==%@@@@@@
|
||||
@@@@@@@@@@@@@@#&;==?=-+=^-^++?;++%@@@@@@
|
||||
@@@@@@@@@@@@@@#?;++===++++++=?;++%@@@@@@
|
||||
@@@@@@@@@@@@@@#?;++===???????=;+^%@@@@@@
|
||||
@@@@@@@@@@@@@@%=,--!!!!!----!!,+^*@@@@@@
|
||||
@@@@@@@@@@@@@@%=?=++^^^^-^^^^^+?-*@@@@@@
|
||||
@@@@@@@@@@@@@@*=???=======+++++^-*@@@@@@
|
||||
@@@@@@@@@@@@@@&++++++^^^^^---!!--*@@@@@@
|
||||
@@@@@@@@@@@@@@&^^^^^^^^^^^^^---^-*@@@@@@
|
||||
@@@@@@@@@@@@@@?^-^^^^--------^--!&@@@@@@
|
||||
@@@@@@@@@@@@@@=!!!!!!;;;;;;;!!!!!?%#@@@@
|
||||
@@@@%*******&&^;;;;,;,,,,,!-,::,;%@#%#@@
|
||||
@@@%^^---!!!!!!;;;,,;,,,,;?*; .:,%@@@%#@
|
||||
@@@&-^!^!-^---!;;;;;,,,,,;?*-.,;^@#@@@#@
|
||||
@@@#%?=?=========+++++^^+&&&+^&%%%%%&=&@
|
||||
#=++++=++++++++^^^^^^^-----!!?%?=?&?^;?@
|
||||
@*????===========+++++++++++=*%^--!;!^%@
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@@@@@@###%*&&%@@@
|
||||
MACINTOSH @
|
||||
|
||||
@@@@@@@@@@@@@@#%%@@@@@@@@@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@%=+==^*#%@@@@@@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@=!=?==^+#&*#@@@@@@@@@@@@@@@@@@
|
||||
@@@@@@@@*--&&?=++-#-;=*@@@@@@@@@@@@@@@@@
|
||||
@@@@@@@=;=**&==+^!?& :-?@@@@@@@@@@@@@@@@
|
||||
@@@@@#-^***&?=+^-!-#;.;+&@@@@@@@@@@@@@@@
|
||||
@@@@*!+**&&&=+-!!!,%= :^?#@@@@@@@@@@@@@@
|
||||
@@@&;=*&&??==^!;;;:?*..;+*@@@@@@@@@@@@@@
|
||||
@@?;=&??==+++-;;,;:!#, :-?@@@@@@@@@@@@@@
|
||||
@&:^===++^^^-!,,,,,,#^ .!+#@@@@@@@@@@@@@
|
||||
@,:-^^^^--!!!!,::,,.??. ,^*@@@@@@@@@@@@@
|
||||
? .;!!!!;;;;;;,::::.-%: :-=@@@@@@@@@@@@@
|
||||
^ ...:,,,,,,,,,::::.;#; .!^#@@@@@@@@@@@@
|
||||
%&?=^-!!:.:,,,,:,::.:%- ,-*@@@@@@@@@@@@
|
||||
%%#####%*=^-!;,::::..?&,:,!?@@@@@@@@@@@@
|
||||
#*%#######%*&?==+-;: ^#*&??*@@@@@@@@@@@@
|
||||
@%*%##%%*****%%*%*&&+=*=?=?*@@@@@@@@@@@@
|
||||
@@%****%%%%%%%***%%#%%= !+^+&@@@@@@@@@@@
|
||||
@@@#%%&*%###%%**%##%%*= !=+=?@@@@@@@@@@@
|
||||
@@@@@@#%**%##%%%%#%%#&+-^+&&%%%%**#@@@@@
|
||||
@@@@@###%*&&&&&?&&+^^==&?==;,,,,,:,-+==%
|
||||
@@@##%*&&????==++^-----!+*=,,,,::;^++==*
|
||||
@@@@@@@@@@@@@@@@@@@@@#*&&*##%***&&%#@@@@
|
||||
IMAC @
|
||||
|
||||
,;;;;;;!!!!!!!!!!!!!:
|
||||
=#*%%%%%******%%%%%*%@-
|
||||
%&=***%%&?&???*%*%*?+@?
|
||||
***&&&###@@@@@@@@@@@?@?
|
||||
***^;=^;?#%%%%%%@@@@?@?
|
||||
*&*&!%^^%#***@@@@@@@?@?
|
||||
*&*+,&-;&#*%%%*@@@@@?@?
|
||||
*&*=+==+?%%%%#@@@@@@?@?
|
||||
*&%&&********%@@@#%#?@?
|
||||
*&&&&******%%%%%%*&*?@?
|
||||
&#%%%%%%############@@?
|
||||
&#####@@@@@@@@@@@@@@@@?
|
||||
&######%%*%%**%#@@@@@@?
|
||||
&####%**&&&&&&***@@@@@?
|
||||
&###%&&&&&%%%&&&&*@@@@?
|
||||
&#%%*&&?&@@@@#?&&&#@@@?
|
||||
?%%%&????#@@@%????#@@@?
|
||||
?%*%*?=?=?&&?=??=&@@@@?
|
||||
?***%*?========?&#@@@@?
|
||||
=****%%*&?&&?&*%###@@@?
|
||||
?*****%%%%%%#######@@@=
|
||||
!&&&*****%%%%%%%%####%,
|
||||
.:::::::::::::::::::.
|
||||
IPOD @
|
||||
|
||||
@@@@@@@@@@@@@@%****&**&&&&?????==?===++&
|
||||
@@@@@@@@@@@@@%!-^^^^+=?====??====++++=^=
|
||||
@@@@@@@@@@@@@*;,;;!!-^+^^+++++++^^^^^^-=
|
||||
@@@@@@@@@@@@@?,::,;!----^+^^^^^^^^^^^--?
|
||||
@@@@@@@@@@@@@=,::,!!--^^^^^^^^^^^----^-&
|
||||
@@@@@@@@@@@@@^,:::;--^^------------^^^-*
|
||||
@@@@@@@@@@@@@-::::;!^+!!--!!---!-------%
|
||||
@@@@@@@@@@@@@!::::,-=!!!!!;---!!!!!!!;!#
|
||||
@@@@@@@@@@@@#;....,^^;;;;;-^-!!;!;;,,,!#
|
||||
@@@@@@@@@@@@%,....;^;,,,,-^!!;;;;,,::,!@
|
||||
@@@@@@@@@@@@*,....;,,::,--!;,,,,:::::,-@
|
||||
@@@@@@@@@@@@?: ::::::;;;;,,::...::.:-@
|
||||
@@@@@@@@@@@@+. ......::::::.........:^@
|
||||
@@@@@@@@@@@@^. ............ ....:+@
|
||||
@@@@@@@@@@@@- ...:+@
|
||||
@@@@@@@@@@@@! ;.,:,::..... . :=@
|
||||
@@@@@@@@@@%=;,,,--^++=?!!^-^^!,?;: :?@
|
||||
@@@@@@*=-;,!^----^--^^^!-+++++^^-;:..,&@
|
||||
@#*?++====???++^+^^^^-!-!!;!!!!;,...,-%@
|
||||
==&***%%%#####*&?==^-^++-!!;;,;:..,!!&@@
|
||||
?----^+=???*&?=+&*&????==+^-!!;,;=-&@@@@
|
||||
@@@@@#%*&?=+^-!;!!;,,;;;;;;;;,,;-&@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@#%*&?=+^!!;,;?@@@@@@@@
|
||||
MACBOOK PRO @
|
||||
|
||||
@@@@@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@@
|
||||
@@@@@@@@@@@@@@@@@@@ @@@@@@@@@@@@@@@@
|
||||
@@@@@@@@@@ @@@@@ @@@@@ @@@@@@@@
|
||||
@@@@@@ @@@@
|
||||
@@@@ @@@
|
||||
@@ @@@@
|
||||
@ @@@@@@
|
||||
@ @@@@@@@
|
||||
@ @@@@@@@
|
||||
@ @@@@@@@
|
||||
@ @@@@@@@
|
||||
@ @@@@@@
|
||||
@ @@@@
|
||||
@@ @@
|
||||
@@@ @@
|
||||
@@@ @@@
|
||||
@@@@@ @@@@
|
||||
@@@@@@ @@@@@
|
||||
@@@@@@@@ @@@@@@
|
||||
@@@@@@@@@ @@@@@@@ @@@@@@@@
|
||||
THE NEXT THIRTY... @
|
||||
|
After Width: | Height: | Size: 24 KiB |
After Width: | Height: | Size: 16 KiB |
After Width: | Height: | Size: 26 KiB |
After Width: | Height: | Size: 24 KiB |
After Width: | Height: | Size: 19 KiB |
After Width: | Height: | Size: 20 KiB |
After Width: | Height: | Size: 12 KiB |
After Width: | Height: | Size: 21 KiB |
After Width: | Height: | Size: 20 KiB |
After Width: | Height: | Size: 20 KiB |
After Width: | Height: | Size: 14 KiB |
After Width: | Height: | Size: 10 KiB |
After Width: | Height: | Size: 63 KiB |
After Width: | Height: | Size: 49 KiB |
After Width: | Height: | Size: 24 KiB |
After Width: | Height: | Size: 1.8 MiB |
After Width: | Height: | Size: 101 KiB |
After Width: | Height: | Size: 148 KiB |
|
@ -0,0 +1,639 @@
|
|||
# @
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10101
|
||||
10111
|
||||
10110
|
||||
10000
|
||||
01111
|
||||
|
||||
# A
|
||||
00000
|
||||
00100
|
||||
01010
|
||||
10001
|
||||
10001
|
||||
11111
|
||||
10001
|
||||
10001
|
||||
|
||||
# B
|
||||
00000
|
||||
11110
|
||||
10001
|
||||
10001
|
||||
11110
|
||||
10001
|
||||
10001
|
||||
11110
|
||||
|
||||
# C
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
10001
|
||||
01110
|
||||
|
||||
# D
|
||||
00000
|
||||
11110
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
11110
|
||||
|
||||
# E
|
||||
00000
|
||||
11111
|
||||
10000
|
||||
10000
|
||||
11110
|
||||
10000
|
||||
10000
|
||||
11111
|
||||
|
||||
# F
|
||||
00000
|
||||
11111
|
||||
10000
|
||||
10000
|
||||
11110
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
|
||||
# G
|
||||
00000
|
||||
01111
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
10011
|
||||
10001
|
||||
01111
|
||||
|
||||
# H
|
||||
00000
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
11111
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
|
||||
# I
|
||||
00000
|
||||
01110
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
01110
|
||||
|
||||
# J
|
||||
00000
|
||||
00001
|
||||
00001
|
||||
00001
|
||||
00001
|
||||
00001
|
||||
10001
|
||||
01110
|
||||
|
||||
# K
|
||||
00000
|
||||
10001
|
||||
10010
|
||||
10100
|
||||
11000
|
||||
10100
|
||||
10010
|
||||
10001
|
||||
|
||||
# L
|
||||
00000
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
11111
|
||||
|
||||
# M
|
||||
00000
|
||||
10001
|
||||
11011
|
||||
10101
|
||||
10101
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
|
||||
# N
|
||||
00000
|
||||
10001
|
||||
10001
|
||||
11001
|
||||
10101
|
||||
10011
|
||||
10001
|
||||
10001
|
||||
|
||||
# O
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
01110
|
||||
|
||||
# P
|
||||
00000
|
||||
11110
|
||||
10001
|
||||
10001
|
||||
11110
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
|
||||
# Q
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10101
|
||||
10010
|
||||
01101
|
||||
|
||||
# R
|
||||
00000
|
||||
11110
|
||||
10001
|
||||
10001
|
||||
11110
|
||||
10100
|
||||
10010
|
||||
10001
|
||||
|
||||
# S
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10000
|
||||
01110
|
||||
00001
|
||||
10001
|
||||
01110
|
||||
|
||||
# T
|
||||
00000
|
||||
11111
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
|
||||
# U
|
||||
00000
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
01110
|
||||
|
||||
# V
|
||||
00000
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
01010
|
||||
00100
|
||||
|
||||
# W
|
||||
00000
|
||||
10001
|
||||
10001
|
||||
10001
|
||||
10101
|
||||
10101
|
||||
11011
|
||||
10001
|
||||
|
||||
# X
|
||||
00000
|
||||
10001
|
||||
10001
|
||||
01010
|
||||
00100
|
||||
01010
|
||||
10001
|
||||
10001
|
||||
|
||||
# Y
|
||||
00000
|
||||
10001
|
||||
10001
|
||||
01010
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
|
||||
# Z
|
||||
00000
|
||||
11111
|
||||
00001
|
||||
00010
|
||||
00100
|
||||
01000
|
||||
10000
|
||||
11111
|
||||
|
||||
# [
|
||||
00000
|
||||
11111
|
||||
11000
|
||||
11000
|
||||
11000
|
||||
11000
|
||||
11000
|
||||
11111
|
||||
|
||||
# \
|
||||
00000
|
||||
00000
|
||||
10000
|
||||
01000
|
||||
00100
|
||||
00010
|
||||
00001
|
||||
00000
|
||||
|
||||
# ]
|
||||
00000
|
||||
11111
|
||||
00011
|
||||
00011
|
||||
00011
|
||||
00011
|
||||
00011
|
||||
11111
|
||||
|
||||
# ^
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00100
|
||||
01010
|
||||
10001
|
||||
00000
|
||||
00000
|
||||
|
||||
# _
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
11111
|
||||
|
||||
#
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
|
||||
# !
|
||||
00000
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00000
|
||||
00100
|
||||
|
||||
# "
|
||||
00000
|
||||
01010
|
||||
01010
|
||||
01010
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
|
||||
# #
|
||||
00000
|
||||
01010
|
||||
01010
|
||||
11111
|
||||
01010
|
||||
11111
|
||||
01010
|
||||
01010
|
||||
|
||||
# $
|
||||
00000
|
||||
00100
|
||||
01111
|
||||
10100
|
||||
01110
|
||||
00101
|
||||
11110
|
||||
00100
|
||||
|
||||
# %
|
||||
00000
|
||||
11000
|
||||
11001
|
||||
00010
|
||||
00100
|
||||
01000
|
||||
10011
|
||||
00011
|
||||
|
||||
# &
|
||||
00000
|
||||
01000
|
||||
10100
|
||||
10100
|
||||
01000
|
||||
10101
|
||||
10010
|
||||
01101
|
||||
|
||||
# '
|
||||
00000
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
|
||||
# (
|
||||
00000
|
||||
00100
|
||||
01000
|
||||
10000
|
||||
10000
|
||||
10000
|
||||
01000
|
||||
00100
|
||||
|
||||
# )
|
||||
00000
|
||||
00100
|
||||
00010
|
||||
00001
|
||||
00001
|
||||
00001
|
||||
00010
|
||||
00100
|
||||
|
||||
# *
|
||||
00000
|
||||
00100
|
||||
10101
|
||||
01110
|
||||
00100
|
||||
01110
|
||||
10101
|
||||
00100
|
||||
|
||||
# +
|
||||
00000
|
||||
00000
|
||||
00100
|
||||
00100
|
||||
11111
|
||||
00100
|
||||
00100
|
||||
00000
|
||||
|
||||
# ,
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00100
|
||||
00100
|
||||
01000
|
||||
|
||||
# -
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
11111
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
|
||||
# .
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00100
|
||||
|
||||
# /
|
||||
00000
|
||||
00000
|
||||
00001
|
||||
00010
|
||||
00100
|
||||
01000
|
||||
10000
|
||||
00000
|
||||
|
||||
# 0
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10011
|
||||
10101
|
||||
11001
|
||||
10001
|
||||
01110
|
||||
|
||||
# 1
|
||||
00000
|
||||
00100
|
||||
01100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
00100
|
||||
01110
|
||||
|
||||
# 2
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
00001
|
||||
00110
|
||||
01000
|
||||
10000
|
||||
11111
|
||||
|
||||
# 3
|
||||
00000
|
||||
11111
|
||||
00001
|
||||
00010
|
||||
00110
|
||||
00001
|
||||
10001
|
||||
01110
|
||||
|
||||
# 4
|
||||
00000
|
||||
00010
|
||||
00110
|
||||
01010
|
||||
10010
|
||||
11111
|
||||
00010
|
||||
00010
|
||||
|
||||
# 5
|
||||
00000
|
||||
11111
|
||||
10000
|
||||
11110
|
||||
00001
|
||||
00001
|
||||
10001
|
||||
01110
|
||||
|
||||
# 6
|
||||
00000
|
||||
00111
|
||||
01000
|
||||
10000
|
||||
11110
|
||||
10001
|
||||
10001
|
||||
01110
|
||||
|
||||
# 7
|
||||
00000
|
||||
11111
|
||||
00001
|
||||
00010
|
||||
00100
|
||||
01000
|
||||
01000
|
||||
01000
|
||||
|
||||
# 8
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10001
|
||||
01110
|
||||
10001
|
||||
10001
|
||||
01110
|
||||
|
||||
# 9
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
10001
|
||||
01111
|
||||
00001
|
||||
00010
|
||||
11100
|
||||
|
||||
# :
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00100
|
||||
00000
|
||||
00100
|
||||
00000
|
||||
00000
|
||||
|
||||
# ;
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
00100
|
||||
00000
|
||||
00100
|
||||
00100
|
||||
01000
|
||||
|
||||
# <
|
||||
00000
|
||||
00010
|
||||
00100
|
||||
01000
|
||||
10000
|
||||
01000
|
||||
00100
|
||||
00010
|
||||
|
||||
# =
|
||||
00000
|
||||
00000
|
||||
00000
|
||||
11111
|
||||
00000
|
||||
11111
|
||||
00000
|
||||
00000
|
||||
|
||||
# >
|
||||
00000
|
||||
01000
|
||||
00100
|
||||
00010
|
||||
00001
|
||||
00010
|
||||
00100
|
||||
01000
|
||||
|
||||
# ?
|
||||
00000
|
||||
01110
|
||||
10001
|
||||
00010
|
||||
00100
|
||||
00100
|
||||
00000
|
||||
00100
|
|
@ -0,0 +1,39 @@
|
|||
000001
|
||||
000010
|
||||
000011
|
||||
000100
|
||||
000101
|
||||
000110
|
||||
000111
|
||||
001000
|
||||
001001
|
||||
001010
|
||||
001011
|
||||
001100
|
||||
001101
|
||||
001110
|
||||
001111
|
||||
010000
|
||||
010001
|
||||
010010
|
||||
010011
|
||||
010100
|
||||
010101
|
||||
010110
|
||||
010111
|
||||
011000
|
||||
011001
|
||||
011010
|
||||
011011
|
||||
011100
|
||||
011101
|
||||
011110
|
||||
011111
|
||||
100000
|
||||
100001
|
||||
100010
|
||||
100011
|
||||
100100
|
||||
100101
|
||||
100110
|
||||
100111
|