SCUBA, Version Diamond (64-bit) 3.10.2.115
Thu Aug 08 17:25:32 2019

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Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n ScreenRam -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 6 -depth 1024 -mode 8 
    Circuit name     : ScreenRam
    Module type      : shiftreg
    Module Version   : 5.2
    Ports            : 
	Inputs       : Din[5:0], Clock, ClockEn, Reset
	Outputs      : Q[5:0]
    I/O buffer       : not inserted
    EDIF output      : ScreenRam.edn
    VHDL output      : ScreenRam.vhd
    VHDL template    : ScreenRam_tmpl.vhd
    VHDL testbench    : tb_ScreenRam_tmpl.vhd
    VHDL purpose     : for synthesis and simulation
    Bus notation     : big endian
    Report output    : ScreenRam.srp
    Element Usage    :
            CU2 : 5
         FADD2B : 1
        FD1P3IX : 10
            INV : 2
            OR2 : 1
       ROM16X1A : 4
          DP8KC : 1
    Estimated Resource Usage:
            LUT : 17
            EBR : 1
            Reg : 10