SCUBA, Version Diamond (64-bit) 3.10.2.115
Mon Aug 05 13:43:30 2019

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2017 Lattice Semiconductor Corporation,  All rights reserved.

    Issued command   : C:\lscc\diamond\3.10_x64\ispfpga\bin\nt64\scuba.exe -w -n ShiftReg40 -lang vhdl -synth synplify -bus_exp 7 -bb -arch xo2c00 -type shiftreg -width 6 -depth 40 -mode 8 -memfile c:/dev/apple1display/docs/lut_2519.mem -memformat bin 
    Circuit name     : ShiftReg40
    Module type      : shiftreg
    Module Version   : 5.2
    Ports            : 
	Inputs       : Din[5:0], Clock, ClockEn, Reset
	Outputs      : Q[5:0]
    I/O buffer       : not inserted
    Memory file      : c:/dev/apple1display/docs/lut_2519.mem
    EDIF output      : ShiftReg40.edn
    VHDL output      : ShiftReg40.vhd
    VHDL template    : ShiftReg40_tmpl.vhd
    VHDL testbench    : tb_ShiftReg40_tmpl.vhd
    VHDL purpose     : for synthesis and simulation
    Bus notation     : big endian
    Report output    : ShiftReg40.srp
    Element Usage    :
            CU2 : 3
         FADD2B : 1
        FD1P3IX : 6
            INV : 4
            OR2 : 1
       ROM16X1A : 2
          DP8KC : 1
    Estimated Resource Usage:
            LUT : 11
            EBR : 1
            Reg : 6