-- VHDL module instantiation generated by SCUBA Diamond (64-bit) 3.10.2.115
-- Module  Version: 5.2
-- Mon Aug 05 13:43:30 2019

-- parameterized module component declaration
component ShiftReg40
    port (Din: in  std_logic_vector(5 downto 0); Clock: in  std_logic; 
        ClockEn: in  std_logic; Reset: in  std_logic; 
        Q: out  std_logic_vector(5 downto 0));
end component;

-- parameterized module component instance
__ : ShiftReg40
    port map (Din(5 downto 0)=>__, Clock=>__, ClockEn=>__, Reset=>__, Q(5 downto 0)=>__);